fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP

Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP
Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu · Michal Simek
1 parent 5242772c51
Showing 13 changed files with 301 additions and 0 deletions Side-by-side Diff
configs/xilinx_zynqmp_ep_defconfig
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
configs/xilinx_zynqmp_zcu102_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig
drivers/fpga/Kconfig
drivers/fpga/Makefile
drivers/fpga/xilinx.c
drivers/fpga/zynqmppl.c
include/xilinx.h
include/zynqmppl.h
@@ -46,6 +46,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
@@ -38,6 +38,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
@@ -41,6 +41,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
@@ -34,6 +34,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
@@ -33,6 +33,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
@@ -38,6 +38,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_MMC_OPS=y
@@ -38,6 +38,8 @@
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_MMC_OPS=y
 menu "FPGA support"
  
+config FPGA
+	bool
+
+config FPGA_XILINX
+	bool "Enable Xilinx FPGA drivers"
+	select FPGA
+	help
+	  Enable Xilinx FPGA specific functions which includes bitstream
+	  (in BIT format), fpga and device validation.
+
+config FPGA_ZYNQMPPL
+	bool "Enable Xilinx FPGA driver for ZynqMP"
+	depends on FPGA_XILINX
+	help
+	  Enable FPGA driver for loading bitstream in BIT and BIN format
+	  on Xilinx Zynq UltraScale+ (ZynqMP) device.
+
 endmenu
@@ -10,6 +10,7 @@
 obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
 obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
 obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
+obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
 obj-$(CONFIG_FPGA_XILINX) += xilinx.o
 obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
 ifdef CONFIG_FPGA_ALTERA
@@ -199,6 +199,9 @@
 		case xilinx_zynq:
 			printf("Zynq PL\n");
 			break;
+		case xilinx_zynqmp:
+			printf("ZynqMP PL\n");
+			break;
 			/* Add new family types here */
 		default:
 			printf ("Unknown family type, %d\n", desc->family);
@@ -226,6 +229,9 @@
 			break;
 		case devcfg:
 			printf("Device configuration interface (Zynq)\n");
+			break;
+		case csu_dma:
+			printf("csu_dma configuration interface (ZynqMP)\n");
 			break;
 			/* Add new interface types here */
 		default:
+/*
+ * (C) Copyright 2015 - 2016, Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <console.h>
+#include <common.h>
+#include <zynqmppl.h>
+#include <linux/sizes.h>
+
+#define DUMMY_WORD	0xffffffff
+
+/* Xilinx binary format header */
+static const u32 bin_format[] = {
+	DUMMY_WORD, /* Dummy words */
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	DUMMY_WORD,
+	0x000000bb, /* Sync word */
+	0x11220044, /* Sync word */
+	DUMMY_WORD,
+	DUMMY_WORD,
+	0xaa995566, /* Sync word */
+};
+
+#define SWAP_NO		1
+#define SWAP_DONE	2
+
+/*
+ * Load the whole word from unaligned buffer
+ * Keep in your mind that it is byte loading on little-endian system
+ */
+static u32 load_word(const void *buf, u32 swap)
+{
+	u32 word = 0;
+	u8 *bitc = (u8 *)buf;
+	int p;
+
+	if (swap == SWAP_NO) {
+		for (p = 0; p < 4; p++) {
+			word <<= 8;
+			word |= bitc[p];
+		}
+	} else {
+		for (p = 3; p >= 0; p--) {
+			word <<= 8;
+			word |= bitc[p];
+		}
+	}
+
+	return word;
+}
+
+static u32 check_header(const void *buf)
+{
+	u32 i, pattern;
+	int swap = SWAP_NO;
+	u32 *test = (u32 *)buf;
+
+	debug("%s: Let's check bitstream header\n", __func__);
+
+	/* Checking that passing bin is not a bitstream */
+	for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
+		pattern = load_word(&test[i], swap);
+
+		/*
+		 * Bitstreams in binary format are swapped
+		 * compare to regular bistream.
+		 * Do not swap dummy word but if swap is done assume
+		 * that parsing buffer is binary format
+		 */
+		if ((__swab32(pattern) != DUMMY_WORD) &&
+		    (__swab32(pattern) == bin_format[i])) {
+			swap = SWAP_DONE;
+			debug("%s: data swapped - let's swap\n", __func__);
+		}
+
+		debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
+		      &test[i], pattern, bin_format[i]);
+	}
+	debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
+	      buf, swap == SWAP_NO ? "without" : "with");
+
+	return swap;
+}
+
+static void *check_data(u8 *buf, size_t bsize, u32 *swap)
+{
+	u32 word, p = 0; /* possition */
+
+	/* Because buf doesn't need to be aligned let's read it by chars */
+	for (p = 0; p < bsize; p++) {
+		word = load_word(&buf[p], SWAP_NO);
+		debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
+
+		/* Find the first bitstream dummy word */
+		if (word == DUMMY_WORD) {
+			debug("%s: Found dummy word at position %x/%px\n",
+			      __func__, p, &buf[p]);
+			*swap = check_header(&buf[p]);
+			if (*swap) {
+				/* FIXME add full bitstream checking here */
+				return &buf[p];
+			}
+		}
+		/* Loop can be huge - support CTRL + C */
+		if (ctrlc())
+			return NULL;
+	}
+	return NULL;
+}
+
+static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+	u32 *new_buf;
+	u32 i;
+
+	if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
+		new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
+
+		/*
+		 * This might be dangerous but permits to flash if
+		 * ARCH_DMA_MINALIGN is greater than header size
+		 */
+		if (new_buf > (u32 *)buf) {
+			debug("%s: Aligned buffer is after buffer start\n",
+			      __func__);
+			new_buf -= ARCH_DMA_MINALIGN;
+		}
+		printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
+		       buf, new_buf, swap);
+
+		for (i = 0; i < (len/4); i++)
+			new_buf[i] = load_word(&buf[i], swap);
+
+		buf = new_buf;
+	} else if (swap != SWAP_DONE) {
+		/* For bitstream which are aligned */
+		u32 *new_buf = (u32 *)buf;
+
+		printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+		       swap);
+
+		for (i = 0; i < (len/4); i++)
+			new_buf[i] = load_word(&buf[i], swap);
+	}
+
+	return (ulong)buf;
+}
+
+static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
+				   size_t bsize, u32 blocksize, u32 *swap)
+{
+	ulong *buf_start;
+	ulong diff;
+
+	buf_start = check_data((u8 *)buf, blocksize, swap);
+
+	if (!buf_start)
+		return FPGA_FAIL;
+
+	/* Check if data is postpone from start */
+	diff = (ulong)buf_start - (ulong)buf;
+	if (diff) {
+		printf("%s: Bitstream is not validated yet (diff %lx)\n",
+		       __func__, diff);
+		return FPGA_FAIL;
+	}
+
+	if ((ulong)buf < SZ_1M) {
+		printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
+		       __func__, buf);
+		return FPGA_FAIL;
+	}
+
+	return 0;
+}
+
+static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
+{
+	struct pt_regs regs;
+	regs.regs[0] = id;
+	regs.regs[1] = reg0;
+	regs.regs[2] = reg1;
+	regs.regs[3] = reg2;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}
+
+static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
+		     bitstream_type bstype)
+{
+	u32 swap;
+	ulong bin_buf, flags;
+	int ret;
+
+	if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
+		return FPGA_FAIL;
+
+	bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+
+	debug("%s called!\n", __func__);
+	flush_dcache_range(bin_buf, bin_buf + bsize);
+
+	if (bsize % 4)
+		bsize = bsize / 4 + 1;
+	else
+		bsize = bsize / 4;
+
+	flags = (u32)bsize | ((u64)bstype << 32);
+
+	ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
+	if (ret)
+		debug("PL FPGA LOAD fail\n");
+
+	return ret;
+}
+
+struct xilinx_fpga_op zynqmp_op = {
+	.load = zynqmp_load,
+};
@@ -21,6 +21,7 @@
 	master_selectmap,	/* master SelectMap (virtex2)           */
 	slave_selectmap,	/* slave SelectMap (virtex2)            */
 	devcfg,			/* devcfg interface (zynq) */
+	csu_dma,		/* csu_dma interface (zynqmp) */
 	max_xilinx_iface_type	/* insert all new types before this */
 } xilinx_iface;			/* end, typedef xilinx_iface */
  
@@ -31,6 +32,7 @@
 	xilinx_virtex2,		/* Virtex2 Family */
 	xilinx_spartan3,	/* Spartan-III Family */
 	xilinx_zynq,		/* Zynq Family */
+	xilinx_zynqmp,		/* ZynqMP Family */
 	max_xilinx_type		/* insert all new types before this */
 } xilinx_family;		/* end, typedef xilinx_family */
  
+/*
+ * (C) Copyright 2015 Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ZYNQMPPL_H_
+#define _ZYNQMPPL_H_
+
+#include <xilinx.h>
+
+#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
+#define ZYNQMP_FPGA_OP_INIT			(1 << 0)
+#define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
+#define ZYNQMP_FPGA_OP_DONE			(1 << 2)
+
+extern struct xilinx_fpga_op zynqmp_op;
+
+#define XILINX_ZYNQMP_DESC \
+{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+
+#endif /* _ZYNQMPPL_H_ */
...	...	@@ -46,6 +46,8 @@
46	46	CONFIG_SPL_DM=y
47	47	CONFIG_SPL_DM_SEQ_ALIAS=y
48	48	CONFIG_BLK=y
	49	+CONFIG_FPGA_XILINX=y
	50	+CONFIG_FPGA_ZYNQMPPL=y
49	51	CONFIG_DM_GPIO=y
50	52	CONFIG_DM_I2C=y
51	53	CONFIG_SYS_I2C_CADENCE=y
...	...	@@ -38,6 +38,8 @@
38	38	CONFIG_SPL_DM=y
39	39	CONFIG_SPL_DM_SEQ_ALIAS=y
40	40	CONFIG_BLK=y
	41	+CONFIG_FPGA_XILINX=y
	42	+CONFIG_FPGA_ZYNQMPPL=y
41	43	CONFIG_DM_GPIO=y
42	44	CONFIG_DM_I2C=y
43	45	CONFIG_SYS_I2C_CADENCE=y
...	...	@@ -41,6 +41,8 @@
41	41	CONFIG_SPL_DM=y
42	42	CONFIG_SPL_DM_SEQ_ALIAS=y
43	43	CONFIG_BLK=y
	44	+CONFIG_FPGA_XILINX=y
	45	+CONFIG_FPGA_ZYNQMPPL=y
44	46	CONFIG_DM_GPIO=y
45	47	CONFIG_DM_I2C=y
46	48	CONFIG_SYS_I2C_CADENCE=y
...	...	@@ -34,6 +34,8 @@
34	34	CONFIG_SPL_DM=y
35	35	CONFIG_SPL_DM_SEQ_ALIAS=y
36	36	CONFIG_BLK=y
	37	+CONFIG_FPGA_XILINX=y
	38	+CONFIG_FPGA_ZYNQMPPL=y
37	39	CONFIG_DM_GPIO=y
38	40	CONFIG_DM_I2C=y
39	41	CONFIG_SYS_I2C_CADENCE=y
...	...	@@ -33,6 +33,8 @@
33	33	CONFIG_SPL_DM=y
34	34	CONFIG_SPL_DM_SEQ_ALIAS=y
35	35	CONFIG_BLK=y
	36	+CONFIG_FPGA_XILINX=y
	37	+CONFIG_FPGA_ZYNQMPPL=y
36	38	CONFIG_DM_GPIO=y
37	39	CONFIG_DM_I2C=y
38	40	CONFIG_SYS_I2C_CADENCE=y
1	1	menu "FPGA support"
2	2
	3	+config FPGA
	4	+ bool
	5	+
	6	+config FPGA_XILINX
	7	+ bool "Enable Xilinx FPGA drivers"
	8	+ select FPGA
	9	+ help
	10	+ Enable Xilinx FPGA specific functions which includes bitstream
	11	+ (in BIT format), fpga and device validation.
	12	+
	13	+config FPGA_ZYNQMPPL
	14	+ bool "Enable Xilinx FPGA driver for ZynqMP"
	15	+ depends on FPGA_XILINX
	16	+ help
	17	+ Enable FPGA driver for loading bitstream in BIT and BIN format
	18	+ on Xilinx Zynq UltraScale+ (ZynqMP) device.
	19	+
3	20	endmenu
...	...	@@ -10,6 +10,7 @@
10	10	obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
11	11	obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
12	12	obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
	13	+obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
13	14	obj-$(CONFIG_FPGA_XILINX) += xilinx.o
14	15	obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
15	16	ifdef CONFIG_FPGA_ALTERA
...	...	@@ -199,6 +199,9 @@
199	199	case xilinx_zynq:
200	200	printf("Zynq PL\n");
201	201	break;
	202	+ case xilinx_zynqmp:
	203	+ printf("ZynqMP PL\n");
	204	+ break;
202	205	/* Add new family types here */
203	206	default:
204	207	printf ("Unknown family type, %d\n", desc->family);
...	...	@@ -226,6 +229,9 @@
226	229	break;
227	230	case devcfg:
228	231	printf("Device configuration interface (Zynq)\n");
	232	+ break;
	233	+ case csu_dma:
	234	+ printf("csu_dma configuration interface (ZynqMP)\n");
229	235	break;
230	236	/* Add new interface types here */
231	237	default:
	1	+/*
	2	+ * (C) Copyright 2015 - 2016, Xilinx, Inc,
	3	+ * Michal Simek <michal.simek@xilinx.com>
	4	+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0
	7	+ */
	8	+
	9	+#include <console.h>
	10	+#include <common.h>
	11	+#include <zynqmppl.h>
	12	+#include <linux/sizes.h>
	13	+
	14	+#define DUMMY_WORD 0xffffffff
	15	+
	16	+/* Xilinx binary format header */
	17	+static const u32 bin_format[] = {
	18	+ DUMMY_WORD, /* Dummy words */
	19	+ DUMMY_WORD,
	20	+ DUMMY_WORD,
	21	+ DUMMY_WORD,
	22	+ DUMMY_WORD,
	23	+ DUMMY_WORD,
	24	+ DUMMY_WORD,
	25	+ DUMMY_WORD,
	26	+ DUMMY_WORD,
	27	+ DUMMY_WORD,
	28	+ DUMMY_WORD,
	29	+ DUMMY_WORD,
	30	+ DUMMY_WORD,
	31	+ DUMMY_WORD,
	32	+ DUMMY_WORD,
	33	+ DUMMY_WORD,
	34	+ 0x000000bb, /* Sync word */
	35	+ 0x11220044, /* Sync word */
	36	+ DUMMY_WORD,
	37	+ DUMMY_WORD,
	38	+ 0xaa995566, /* Sync word */
	39	+};
	40	+
	41	+#define SWAP_NO 1
	42	+#define SWAP_DONE 2
	43	+
	44	+/*
	45	+ * Load the whole word from unaligned buffer
	46	+ * Keep in your mind that it is byte loading on little-endian system
	47	+ */
	48	+static u32 load_word(const void *buf, u32 swap)
	49	+{
	50	+ u32 word = 0;
	51	+ u8 bitc = (u8 )buf;
	52	+ int p;
	53	+
	54	+ if (swap == SWAP_NO) {
	55	+ for (p = 0; p < 4; p++) {
	56	+ word <<= 8;
	57	+ word \|= bitc[p];
	58	+ }
	59	+ } else {
	60	+ for (p = 3; p >= 0; p--) {
	61	+ word <<= 8;
	62	+ word \|= bitc[p];
	63	+ }
	64	+ }
	65	+
	66	+ return word;
	67	+}
	68	+
	69	+static u32 check_header(const void *buf)
	70	+{
	71	+ u32 i, pattern;
	72	+ int swap = SWAP_NO;
	73	+ u32 test = (u32 )buf;
	74	+
	75	+ debug("%s: Let's check bitstream header\n", __func__);
	76	+
	77	+ /* Checking that passing bin is not a bitstream */
	78	+ for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
	79	+ pattern = load_word(&test[i], swap);
	80	+
	81	+ /*
	82	+ * Bitstreams in binary format are swapped
	83	+ * compare to regular bistream.
	84	+ * Do not swap dummy word but if swap is done assume
	85	+ * that parsing buffer is binary format
	86	+ */
	87	+ if ((__swab32(pattern) != DUMMY_WORD) &&
	88	+ (__swab32(pattern) == bin_format[i])) {
	89	+ swap = SWAP_DONE;
	90	+ debug("%s: data swapped - let's swap\n", __func__);
	91	+ }
	92	+
	93	+ debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
	94	+ &test[i], pattern, bin_format[i]);
	95	+ }
	96	+ debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
	97	+ buf, swap == SWAP_NO ? "without" : "with");
	98	+
	99	+ return swap;
	100	+}
	101	+
	102	+static void check_data(u8 buf, size_t bsize, u32 *swap)
	103	+{
	104	+ u32 word, p = 0; /* possition */
	105	+
	106	+ /* Because buf doesn't need to be aligned let's read it by chars */
	107	+ for (p = 0; p < bsize; p++) {
	108	+ word = load_word(&buf[p], SWAP_NO);
	109	+ debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
	110	+
	111	+ /* Find the first bitstream dummy word */
	112	+ if (word == DUMMY_WORD) {
	113	+ debug("%s: Found dummy word at position %x/%px\n",
	114	+ __func__, p, &buf[p]);
	115	+ *swap = check_header(&buf[p]);
	116	+ if (*swap) {
	117	+ /* FIXME add full bitstream checking here */
	118	+ return &buf[p];
	119	+ }
	120	+ }
	121	+ /* Loop can be huge - support CTRL + C */
	122	+ if (ctrlc())
	123	+ return NULL;
	124	+ }
	125	+ return NULL;
	126	+}
	127	+
	128	+static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
	129	+{
	130	+ u32 *new_buf;
	131	+ u32 i;
	132	+
	133	+ if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
	134	+ new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
	135	+
	136	+ /*
	137	+ * This might be dangerous but permits to flash if
	138	+ * ARCH_DMA_MINALIGN is greater than header size
	139	+ */
	140	+ if (new_buf > (u32 *)buf) {
	141	+ debug("%s: Aligned buffer is after buffer start\n",
	142	+ __func__);
	143	+ new_buf -= ARCH_DMA_MINALIGN;
	144	+ }
	145	+ printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
	146	+ buf, new_buf, swap);
	147	+
	148	+ for (i = 0; i < (len/4); i++)
	149	+ new_buf[i] = load_word(&buf[i], swap);
	150	+
	151	+ buf = new_buf;
	152	+ } else if (swap != SWAP_DONE) {
	153	+ /* For bitstream which are aligned */
	154	+ u32 new_buf = (u32 )buf;
	155	+
	156	+ printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
	157	+ swap);
	158	+
	159	+ for (i = 0; i < (len/4); i++)
	160	+ new_buf[i] = load_word(&buf[i], swap);
	161	+ }
	162	+
	163	+ return (ulong)buf;
	164	+}
	165	+
	166	+static int zynqmp_validate_bitstream(xilinx_desc desc, const void buf,
	167	+ size_t bsize, u32 blocksize, u32 *swap)
	168	+{
	169	+ ulong *buf_start;
	170	+ ulong diff;
	171	+
	172	+ buf_start = check_data((u8 *)buf, blocksize, swap);
	173	+
	174	+ if (!buf_start)
	175	+ return FPGA_FAIL;
	176	+
	177	+ /* Check if data is postpone from start */
	178	+ diff = (ulong)buf_start - (ulong)buf;
	179	+ if (diff) {
	180	+ printf("%s: Bitstream is not validated yet (diff %lx)\n",
	181	+ __func__, diff);
	182	+ return FPGA_FAIL;
	183	+ }
	184	+
	185	+ if ((ulong)buf < SZ_1M) {
	186	+ printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
	187	+ __func__, buf);
	188	+ return FPGA_FAIL;
	189	+ }
	190	+
	191	+ return 0;
	192	+}
	193	+
	194	+static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
	195	+{
	196	+ struct pt_regs regs;
	197	+ regs.regs[0] = id;
	198	+ regs.regs[1] = reg0;
	199	+ regs.regs[2] = reg1;
	200	+ regs.regs[3] = reg2;
	201	+
	202	+ smc_call(&regs);
	203	+
	204	+ return regs.regs[0];
	205	+}
	206	+
	207	+static int zynqmp_load(xilinx_desc desc, const void buf, size_t bsize,
	208	+ bitstream_type bstype)
	209	+{
	210	+ u32 swap;
	211	+ ulong bin_buf, flags;
	212	+ int ret;
	213	+
	214	+ if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
	215	+ return FPGA_FAIL;
	216	+
	217	+ bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
	218	+
	219	+ debug("%s called!\n", __func__);
	220	+ flush_dcache_range(bin_buf, bin_buf + bsize);
	221	+
	222	+ if (bsize % 4)
	223	+ bsize = bsize / 4 + 1;
	224	+ else
	225	+ bsize = bsize / 4;
	226	+
	227	+ flags = (u32)bsize \| ((u64)bstype << 32);
	228	+
	229	+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
	230	+ if (ret)
	231	+ debug("PL FPGA LOAD fail\n");
	232	+
	233	+ return ret;
	234	+}
	235	+
	236	+struct xilinx_fpga_op zynqmp_op = {
	237	+ .load = zynqmp_load,
	238	+};
...	...	@@ -21,6 +21,7 @@
21	21	master_selectmap, /* master SelectMap (virtex2) */
22	22	slave_selectmap, /* slave SelectMap (virtex2) */
23	23	devcfg, /* devcfg interface (zynq) */
	24	+ csu_dma, /* csu_dma interface (zynqmp) */
24	25	max_xilinx_iface_type /* insert all new types before this */
25	26	} xilinx_iface; /* end, typedef xilinx_iface */
26	27
...	...	@@ -31,6 +32,7 @@
31	32	xilinx_virtex2, /* Virtex2 Family */
32	33	xilinx_spartan3, /* Spartan-III Family */
33	34	xilinx_zynq, /* Zynq Family */
	35	+ xilinx_zynqmp, /* ZynqMP Family */
34	36	max_xilinx_type /* insert all new types before this */
35	37	} xilinx_family; /* end, typedef xilinx_family */
36	38