usb: dwc3: Add phy interface for dwc3_uboot

U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

usb: dwc3: Add phy interface for dwc3_uboot
U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki · Kever Yang · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent 35172ac02f
Showing 4 changed files with 60 additions and 0 deletions Side-by-side Diff
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
include/dwc3-uboot.h
include/linux/usb/phy.h
@@ -613,6 +613,31 @@
 	dwc3_gadget_run(dwc);
 }
  
+static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
+				  struct dwc3 *dwc)
+{
+	enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
+	u32 reg;
+
+	/* Set dwc3 usb2 phy config */
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+	reg |= DWC3_GUSB2PHYCFG_PHYIF;
+	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
+
+	switch (hsphy_mode) {
+	case USBPHY_INTERFACE_MODE_UTMI:
+		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
+		break;
+	case USBPHY_INTERFACE_MODE_UTMIW:
+		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
+		break;
+	default:
+		break;
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+}
+
 #define DWC3_ALIGN_MASK		(16 - 1)
  
 /**
@@ -720,6 +745,8 @@
 		dev_err(dev, "failed to initialize core\n");
 		goto err0;
 	}
+
+	dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
  
 	ret = dwc3_event_buffers_setup(dwc);
 	if (ret) {
@@ -162,6 +162,18 @@
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
+#define DWC3_GUSB2PHYCFG_PHYIF		BIT(3)
+
+/* Global USB2 PHY Configuration Mask */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK		(0xf << 10)
+
+/* Global USB2 PHY Configuration Offset */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET	10
+
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT	(0x5 << \
+		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT		(0x9 << \
+		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
  
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
@@ -10,10 +10,12 @@
 #define __DWC3_UBOOT_H_
  
 #include <linux/usb/otg.h>
+#include <linux/usb/phy.h>
  
 struct dwc3_device {
 	unsigned long base;
 	enum usb_dr_mode dr_mode;
+	enum usb_phy_interface hsphy_mode;
 	u32 maximum_speed;
 	unsigned tx_fifo_resize:1;
 	unsigned has_lpm_erratum;
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * USB PHY defines
+ *
+ * These APIs may be used between USB controllers.  USB device drivers
+ * (for either host or peripheral roles) don't use these calls; they
+ * continue to use just usb_device and usb_gadget.
+ */
+
+#ifndef __LINUX_USB_PHY_H
+#define __LINUX_USB_PHY_H
+
+enum usb_phy_interface {
+	USBPHY_INTERFACE_MODE_UNKNOWN,
+	USBPHY_INTERFACE_MODE_UTMI,
+	USBPHY_INTERFACE_MODE_UTMIW,
+};
+
+#endif /* __LINUX_USB_PHY_H */
...	...	@@ -613,6 +613,31 @@
613	613	dwc3_gadget_run(dwc);
614	614	}
615	615
	616	+static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
	617	+ struct dwc3 *dwc)
	618	+{
	619	+ enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
	620	+ u32 reg;
	621	+
	622	+ /* Set dwc3 usb2 phy config */
	623	+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	624	+ reg \|= DWC3_GUSB2PHYCFG_PHYIF;
	625	+ reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	626	+
	627	+ switch (hsphy_mode) {
	628	+ case USBPHY_INTERFACE_MODE_UTMI:
	629	+ reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
	630	+ break;
	631	+ case USBPHY_INTERFACE_MODE_UTMIW:
	632	+ reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	633	+ break;
	634	+ default:
	635	+ break;
	636	+ }
	637	+
	638	+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	639	+}
	640	+
616	641	#define DWC3_ALIGN_MASK (16 - 1)
617	642
618	643	/**
...	...	@@ -720,6 +745,8 @@
720	745	dev_err(dev, "failed to initialize core\n");
721	746	goto err0;
722	747	}
	748	+
	749	+ dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
723	750
724	751	ret = dwc3_event_buffers_setup(dwc);
725	752	if (ret) {
...	...	@@ -162,6 +162,18 @@
162	162	/* Global USB2 PHY Configuration Register */
163	163	#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
164	164	#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
	165	+#define DWC3_GUSB2PHYCFG_PHYIF BIT(3)
	166	+
	167	+/* Global USB2 PHY Configuration Mask */
	168	+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
	169	+
	170	+/* Global USB2 PHY Configuration Offset */
	171	+#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
	172	+
	173	+#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
	174	+ DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
	175	+#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
	176	+ DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
165	177
166	178	/* Global USB3 PIPE Control Register */
167	179	#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
...	...	@@ -10,10 +10,12 @@
10	10	#define __DWC3_UBOOT_H_
11	11
12	12	#include <linux/usb/otg.h>
	13	+#include <linux/usb/phy.h>
13	14
14	15	struct dwc3_device {
15	16	unsigned long base;
16	17	enum usb_dr_mode dr_mode;
	18	+ enum usb_phy_interface hsphy_mode;
17	19	u32 maximum_speed;
18	20	unsigned tx_fifo_resize:1;
19	21	unsigned has_lpm_erratum;
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * USB PHY defines
	4	+ *
	5	+ * These APIs may be used between USB controllers. USB device drivers
	6	+ * (for either host or peripheral roles) don't use these calls; they
	7	+ * continue to use just usb_device and usb_gadget.
	8	+ */
	9	+
	10	+#ifndef __LINUX_USB_PHY_H
	11	+#define __LINUX_USB_PHY_H
	12	+
	13	+enum usb_phy_interface {
	14	+ USBPHY_INTERFACE_MODE_UNKNOWN,
	15	+ USBPHY_INTERFACE_MODE_UTMI,
	16	+ USBPHY_INTERFACE_MODE_UTMIW,
	17	+};
	18	+
	19	+#endif /* __LINUX_USB_PHY_H */