Driver/ddr: Add support of different DDR base address

DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com>

Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun <yorksun@freescale.com>
York Sun · Tom Rini
1 parent 4e5b1bd0df
Showing 2 changed files with 19 additions and 2 deletions Side-by-side Diff
README
drivers/ddr/fsl/main.c
@@ -492,6 +492,11 @@
 		CONFIG_SYS_FSL_DDR_LE
 		Defines the DDR controller register space as Little Endian
  
+		CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+		Physical address from the view of DDR controllers. It is the
+		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+		it could be different for ARM SoCs.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
  
@@ -17,6 +17,18 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
  
+/*
+ * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
+ * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
+ * all Power SoCs. But it could be different for ARM SoCs. For example,
+ * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
+ * 0x00_8000_0000 ~ 0x00_ffff_ffff
+ * 0x80_8000_0000 ~ 0xff_ffff_ffff
+ */
+#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#endif
+
 #ifdef CONFIG_PPC
 #include <asm/fsl_law.h>
  
@@ -255,7 +267,7 @@
 		debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 	}
  
-	current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
+	current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 	total_mem = 0;
 	if (pinfo->memctl_opts[0].memctl_interleaving) {
 		rank_density = pinfo->dimm_params[0][0].rank_density >>
@@ -536,7 +548,7 @@
 		}
  
 		total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
-			    0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
+			    0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 	}
  
 	return total_mem;
...	...	@@ -492,6 +492,11 @@
492	492	CONFIG_SYS_FSL_DDR_LE
493	493	Defines the DDR controller register space as Little Endian
494	494
	495	+ CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
	496	+ Physical address from the view of DDR controllers. It is the
	497	+ same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
	498	+ it could be different for ARM SoCs.
	499	+
495	500	- Intel Monahans options:
496	501	CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
497	502
...	...	@@ -17,6 +17,18 @@
17	17	#include <fsl_ddr_sdram.h>
18	18	#include <fsl_ddr.h>
19	19
	20	+/*
	21	+ * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
	22	+ * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
	23	+ * all Power SoCs. But it could be different for ARM SoCs. For example,
	24	+ * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
	25	+ * 0x00_8000_0000 ~ 0x00_ffff_ffff
	26	+ * 0x80_8000_0000 ~ 0xff_ffff_ffff
	27	+ */
	28	+#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
	29	+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
	30	+#endif
	31	+
20	32	#ifdef CONFIG_PPC
21	33	#include <asm/fsl_law.h>
22	34
...	...	@@ -255,7 +267,7 @@
255	267	debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
256	268	}
257	269
258		- current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
	270	+ current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
259	271	total_mem = 0;
260	272	if (pinfo->memctl_opts[0].memctl_interleaving) {
261	273	rank_density = pinfo->dimm_params[0][0].rank_density >>
...	...	@@ -536,7 +548,7 @@
536	548	}
537	549
538	550	total_mem = 1 + (((unsigned long long)max_end << 24ULL) \|
539		- 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
	551	+ 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
540	552	}
541	553
542	554	return total_mem;