Eric Lee / smarc-uboot

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Commit 6bdf430660531aca5f88faeac8657d91595f5b38

Authored by Wolfgang Denk
1 parent 4dc37144f0
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board. 

Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005

Showing 12 changed files with 1643 additions and 1 deletions Side-by-side Diff

... ... @@ -2,6 +2,9 @@
2 2 Changes for U-Boot 1.1.4:
3 3 ======================================================================
4 4  
  5 +* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
  6 + Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
  7 +
5 8 * Check return value of malloc in 440gx_enet.c
6 9 Patch by Travis B. Sawyer, 18 Jul 2005
7 10  
... ... @@ -29,6 +29,7 @@
29 29 N: Pantelis Antoniou
30 30 E: panto@intracom.gr
31 31 D: NETVIA & NETPHONE board support, ARTOS support.
  32 +D: Support for Silicon Turnkey eXpress XTc
32 33  
33 34 N: Pierre Aubert
34 35 E: <p.aubert@staubli.com>
35 36  
... ... @@ -268,8 +269,9 @@
268 269 D: Support for DOS partitions
269 270  
270 271 N: Dan Malek
271   -E: dan@netx4.com
  272 +E: dan@embeddedalley.com
272 273 D: FADSROM, the grandfather of all of this
  274 +D: Support for Silicon Turnkey eXpress XTc
273 275  
274 276 N: Andrea "llandre" Marson
275 277 E: andrea.marson@dave-tech.it
... ... @@ -215,6 +215,7 @@
215 215 Dan Malek <dan@embeddededge.com>
216 216  
217 217 STxGP3 MPC85xx
  218 + STxXTc MPC8xx
218 219  
219 220 Eran Man <eran@nbase.co.il>
220 221  
... ... @@ -644,6 +644,9 @@
644 644 SPD823TS_config: unconfig
645 645 @./mkconfig $(@:_config=) ppc mpc8xx spd8xx
646 646  
  647 +stxxtc_config: unconfig
  648 + @./mkconfig $(@:_config=) ppc mpc8xx stxxtc
  649 +
647 650 svm_sc8xx_config: unconfig
648 651 @ >include/config.h
649 652 @./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx
board/stxxtc/Makefile
Diff comments   View file @ 6bdf430
  1 +#
  2 +# (C) Copyright 2000-2004
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o
  29 +
  30 +$(LIB): .depend $(OBJS)
  31 + $(AR) crv $@ $(OBJS)
  32 +
  33 +#########################################################################
  34 +
  35 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  36 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  37 +
  38 +sinclude .depend
  39 +
  40 +#########################################################################
board/stxxtc/config.mk
Diff comments   View file @ 6bdf430
  1 +#
  2 +# (C) Copyright 2000-2004
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +#
  25 +# STx XTc
  26 +#
  27 +
  28 +TEXT_BASE = 0x40F00000
board/stxxtc/stxxtc.c
Diff comments   View file @ 6bdf430
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  4 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5 + * (C) Copyright 2005
  6 + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +/*
  28 + * U-Boot port on STx XTc board
  29 + * Mostly copied from Netta
  30 + */
  31 +
  32 +#include <common.h>
  33 +#include <miiphy.h>
  34 +
  35 +#include "mpc8xx.h"
  36 +
  37 +#ifdef CONFIG_HW_WATCHDOG
  38 +#include <watchdog.h>
  39 +#endif
  40 +
  41 +/****************************************************************/
  42 +
  43 +/* some sane bit macros */
  44 +#define _BD(_b) (1U << (31-(_b)))
  45 +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
  46 +
  47 +#define _BW(_b) (1U << (15-(_b)))
  48 +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
  49 +
  50 +#define _BB(_b) (1U << (7-(_b)))
  51 +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
  52 +
  53 +#define _B(_b) _BD(_b)
  54 +#define _BR(_l, _h) _BDR(_l, _h)
  55 +
  56 +/****************************************************************/
  57 +
  58 +/*
  59 + * Check Board Identity:
  60 + *
  61 + * Return 1 always.
  62 + */
  63 +
  64 +int checkboard(void)
  65 +{
  66 + printf ("Silicon Turnkey eXpress XTc\n");
  67 + return (0);
  68 +}
  69 +
  70 +/****************************************************************/
  71 +
  72 +#define _NOT_USED_ 0xFFFFFFFF
  73 +
  74 +/****************************************************************/
  75 +
  76 +#define CS_0000 0x00000000
  77 +#define CS_0001 0x10000000
  78 +#define CS_0010 0x20000000
  79 +#define CS_0011 0x30000000
  80 +#define CS_0100 0x40000000
  81 +#define CS_0101 0x50000000
  82 +#define CS_0110 0x60000000
  83 +#define CS_0111 0x70000000
  84 +#define CS_1000 0x80000000
  85 +#define CS_1001 0x90000000
  86 +#define CS_1010 0xA0000000
  87 +#define CS_1011 0xB0000000
  88 +#define CS_1100 0xC0000000
  89 +#define CS_1101 0xD0000000
  90 +#define CS_1110 0xE0000000
  91 +#define CS_1111 0xF0000000
  92 +
  93 +#define BS_0000 0x00000000
  94 +#define BS_0001 0x01000000
  95 +#define BS_0010 0x02000000
  96 +#define BS_0011 0x03000000
  97 +#define BS_0100 0x04000000
  98 +#define BS_0101 0x05000000
  99 +#define BS_0110 0x06000000
  100 +#define BS_0111 0x07000000
  101 +#define BS_1000 0x08000000
  102 +#define BS_1001 0x09000000
  103 +#define BS_1010 0x0A000000
  104 +#define BS_1011 0x0B000000
  105 +#define BS_1100 0x0C000000
  106 +#define BS_1101 0x0D000000
  107 +#define BS_1110 0x0E000000
  108 +#define BS_1111 0x0F000000
  109 +
  110 +#define GPL0_AAAA 0x00000000
  111 +#define GPL0_AAA0 0x00200000
  112 +#define GPL0_AAA1 0x00300000
  113 +#define GPL0_000A 0x00800000
  114 +#define GPL0_0000 0x00A00000
  115 +#define GPL0_0001 0x00B00000
  116 +#define GPL0_111A 0x00C00000
  117 +#define GPL0_1110 0x00E00000
  118 +#define GPL0_1111 0x00F00000
  119 +
  120 +#define GPL1_0000 0x00000000
  121 +#define GPL1_0001 0x00040000
  122 +#define GPL1_1110 0x00080000
  123 +#define GPL1_1111 0x000C0000
  124 +
  125 +#define GPL2_0000 0x00000000
  126 +#define GPL2_0001 0x00010000
  127 +#define GPL2_1110 0x00020000
  128 +#define GPL2_1111 0x00030000
  129 +
  130 +#define GPL3_0000 0x00000000
  131 +#define GPL3_0001 0x00004000
  132 +#define GPL3_1110 0x00008000
  133 +#define GPL3_1111 0x0000C000
  134 +
  135 +#define GPL4_0000 0x00000000
  136 +#define GPL4_0001 0x00001000
  137 +#define GPL4_1110 0x00002000
  138 +#define GPL4_1111 0x00003000
  139 +
  140 +#define GPL5_0000 0x00000000
  141 +#define GPL5_0001 0x00000400
  142 +#define GPL5_1110 0x00000800
  143 +#define GPL5_1111 0x00000C00
  144 +#define LOOP 0x00000080
  145 +
  146 +#define EXEN 0x00000040
  147 +
  148 +#define AMX_COL 0x00000000
  149 +#define AMX_ROW 0x00000020
  150 +#define AMX_MAR 0x00000030
  151 +
  152 +#define NA 0x00000008
  153 +
  154 +#define UTA 0x00000004
  155 +
  156 +#define TODT 0x00000002
  157 +
  158 +#define LAST 0x00000001
  159 +
  160 +#define A10_AAAA GPL0_AAAA
  161 +#define A10_AAA0 GPL0_AAA0
  162 +#define A10_AAA1 GPL0_AAA1
  163 +#define A10_000A GPL0_000A
  164 +#define A10_0000 GPL0_0000
  165 +#define A10_0001 GPL0_0001
  166 +#define A10_111A GPL0_111A
  167 +#define A10_1110 GPL0_1110
  168 +#define A10_1111 GPL0_1111
  169 +
  170 +#define RAS_0000 GPL1_0000
  171 +#define RAS_0001 GPL1_0001
  172 +#define RAS_1110 GPL1_1110
  173 +#define RAS_1111 GPL1_1111
  174 +
  175 +#define CAS_0000 GPL2_0000
  176 +#define CAS_0001 GPL2_0001
  177 +#define CAS_1110 GPL2_1110
  178 +#define CAS_1111 GPL2_1111
  179 +
  180 +#define WE_0000 GPL3_0000
  181 +#define WE_0001 GPL3_0001
  182 +#define WE_1110 GPL3_1110
  183 +#define WE_1111 GPL3_1111
  184 +
  185 +/* #define CAS_LATENCY 3 */
  186 +#define CAS_LATENCY 2
  187 +
  188 +const uint sdram_table[0x40] = {
  189 +
  190 +#if CAS_LATENCY == 3
  191 + /* RSS */
  192 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  193 + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  194 + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
  195 + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
  196 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  197 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
  198 + _NOT_USED_, _NOT_USED_,
  199 +
  200 + /* RBS */
  201 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  202 + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  203 + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
  204 + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  205 + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  206 + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  207 + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
  208 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
  209 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  210 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  211 +
  212 + /* WSS */
  213 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  214 + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  215 + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
  216 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
  217 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
  218 + _NOT_USED_, _NOT_USED_, _NOT_USED_,
  219 +
  220 + /* WBS */
  221 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  222 + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  223 + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
  224 + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  225 + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  226 + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  227 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  228 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
  229 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
  230 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  231 + _NOT_USED_, _NOT_USED_, _NOT_USED_,
  232 +#endif
  233 +
  234 +#if CAS_LATENCY == 2
  235 + /* RSS */
  236 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  237 + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
  238 + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
  239 + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
  240 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
  241 + _NOT_USED_,
  242 + _NOT_USED_, _NOT_USED_,
  243 +
  244 + /* RBS */
  245 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  246 + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
  247 + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
  248 + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  249 + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  250 + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  251 + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
  252 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
  253 + _NOT_USED_,
  254 + _NOT_USED_, _NOT_USED_, _NOT_USED_,
  255 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  256 +
  257 + /* WSS */
  258 + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  259 + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
  260 + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
  261 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
  262 + _NOT_USED_,
  263 + _NOT_USED_, _NOT_USED_,
  264 + _NOT_USED_,
  265 +
  266 + /* WBS */
  267 + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
  268 + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
  269 + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
  270 + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  271 + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
  272 + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
  273 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
  274 + _NOT_USED_,
  275 + _NOT_USED_, _NOT_USED_, _NOT_USED_,
  276 + _NOT_USED_, _NOT_USED_, _NOT_USED_,
  277 + _NOT_USED_, _NOT_USED_,
  278 +
  279 +#endif
  280 +
  281 + /* UPT */
  282 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
  283 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  284 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  285 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
  286 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
  287 + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
  288 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  289 + _NOT_USED_, _NOT_USED_,
  290 +
  291 + /* EXC */
  292 + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
  293 + _NOT_USED_,
  294 +
  295 + /* REG */
  296 + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
  297 + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
  298 +};
  299 +
  300 +static const uint nandcs_table[0x40] = {
  301 + /* RSS */
  302 + CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
  303 + CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
  304 + CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
  305 + CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
  306 + CS_0000 | GPL4_0000 | GPL5_1111,
  307 + CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
  308 + CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
  309 + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
  310 +
  311 + /* RBS */
  312 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  313 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  314 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  315 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  316 +
  317 + /* WSS */
  318 + CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
  319 + CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
  320 + CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
  321 + CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
  322 + CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
  323 + CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
  324 + CS_0000 | GPL4_1111 | GPL5_1111,
  325 + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
  326 +
  327 + /* WBS */
  328 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  329 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  330 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  331 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  332 +
  333 + /* UPT */
  334 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  335 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  336 + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  337 +
  338 + /* EXC */
  339 + CS_0001 | LAST,
  340 + _NOT_USED_,
  341 +
  342 + /* REG */
  343 + CS_1110 ,
  344 + CS_0001 | LAST,
  345 +};
  346 +
  347 +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
  348 +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
  349 +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
  350 +
  351 +/* 9 */
  352 +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  353 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  354 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  355 +
  356 +void check_ram(unsigned int addr, unsigned int size)
  357 +{
  358 + unsigned int i, j, v, vv;
  359 + volatile unsigned int *p;
  360 + unsigned int pv;
  361 +
  362 + p = (unsigned int *)addr;
  363 + pv = (unsigned int)p;
  364 + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
  365 + *p++ = pv;
  366 +
  367 + p = (unsigned int *)addr;
  368 + for (i = 0; i < size / sizeof(unsigned int); i++) {
  369 + v = (unsigned int)p;
  370 + vv = *p;
  371 + if (vv != v) {
  372 + printf("%p: read %08x instead of %08x\n", p, vv, v);
  373 + hang();
  374 + }
  375 + p++;
  376 + }
  377 +
  378 + for (j = 0; j < 5; j++) {
  379 + switch (j) {
  380 + case 0: v = 0x00000000; break;
  381 + case 1: v = 0xffffffff; break;
  382 + case 2: v = 0x55555555; break;
  383 + case 3: v = 0xaaaaaaaa; break;
  384 + default:v = 0xdeadbeef; break;
  385 + }
  386 + p = (unsigned int *)addr;
  387 + for (i = 0; i < size / sizeof(unsigned int); i++) {
  388 + *p = v;
  389 + vv = *p;
  390 + if (vv != v) {
  391 + printf("%p: read %08x instead of %08x\n", p, vv, v);
  392 + hang();
  393 + }
  394 + *p = ~v;
  395 + p++;
  396 + }
  397 + }
  398 +}
  399 +
  400 +#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
  401 +
  402 +long int initdram(int board_type)
  403 +{
  404 + volatile immap_t *immap = (immap_t *) CFG_IMMR;
  405 + volatile memctl8xx_t *memctl = &immap->im_memctl;
  406 + long int size;
  407 + u32 d1, d2;
  408 +
  409 + upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
  410 +
  411 + /*
  412 + * Preliminary prescaler for refresh
  413 + */
  414 + memctl->memc_mptpr = MPTPR_PTP_DIV8;
  415 +
  416 + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
  417 +
  418 + /*
  419 + * Map controller bank 3 to the SDRAM bank at preliminary address.
  420 + */
  421 + memctl->memc_or4 = CFG_OR4_PRELIM;
  422 + memctl->memc_br4 = CFG_BR4_PRELIM;
  423 +
  424 + memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
  425 +
  426 + udelay(200);
  427 +
  428 + /* perform SDRAM initialisation sequence */
  429 + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
  430 + udelay(1);
  431 +
  432 + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
  433 + udelay(1);
  434 +
  435 + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
  436 + udelay(1);
  437 +
  438 + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  439 +
  440 + udelay(10000);
  441 +
  442 +
  443 + d1 = 0xAA55AA55;
  444 + *(volatile u32 *)0 = d1;
  445 + d2 = *(volatile u32 *)0;
  446 + if (d1 != d2) {
  447 + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
  448 + DO_LOOP;
  449 + }
  450 +
  451 + d1 = 0x55AA55AA;
  452 + *(volatile u32 *)0 = d1;
  453 + d2 = *(volatile u32 *)0;
  454 + if (d1 != d2) {
  455 + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
  456 + DO_LOOP;
  457 + }
  458 +
  459 + d1 = 0x12345678;
  460 + *(volatile u32 *)0 = d1;
  461 + d2 = *(volatile u32 *)0;
  462 + if (d1 != d2) {
  463 + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
  464 + DO_LOOP;
  465 + }
  466 +
  467 + size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
  468 +
  469 + return size;
  470 +}
  471 +
  472 +/* ------------------------------------------------------------------------- */
  473 +
  474 +void reset_phys(void)
  475 +{
  476 + int phyno;
  477 + unsigned short v;
  478 +
  479 + udelay(10000);
  480 + /* reset the damn phys */
  481 + mii_init();
  482 +
  483 + for (phyno = 0; phyno < 32; ++phyno) {
  484 + miiphy_read(phyno, PHY_PHYIDR1, &v);
  485 + if (v == 0xFFFF)
  486 + continue;
  487 + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
  488 + udelay(10000);
  489 + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
  490 + udelay(10000);
  491 + }
  492 +}
  493 +
  494 +/* ------------------------------------------------------------------------- */
  495 +
  496 +/* GP = general purpose, SP = special purpose (on chip peripheral) */
  497 +
  498 +/* bits that can have a special purpose or can be configured as inputs/outputs */
  499 +#define PA_GP_INMASK _BW(6)
  500 +#define PA_GP_OUTMASK (_BW(7))
  501 +#define PA_SP_MASK 0
  502 +#define PA_ODR_VAL 0
  503 +#define PA_GP_OUTVAL (_BW(7))
  504 +#define PA_SP_DIRVAL 0
  505 +
  506 +#define PB_GP_INMASK 0
  507 +#define PB_GP_OUTMASK (_B(23))
  508 +#define PB_SP_MASK 0
  509 +#define PB_ODR_VAL 0
  510 +#define PB_GP_OUTVAL (_B(23))
  511 +#define PB_SP_DIRVAL 0
  512 +
  513 +#define PC_GP_INMASK 0
  514 +#define PC_GP_OUTMASK (_BW(15))
  515 +
  516 +#define PC_SP_MASK 0
  517 +#define PC_SOVAL 0
  518 +#define PC_INTVAL 0
  519 +#define PC_GP_OUTVAL 0
  520 +#define PC_SP_DIRVAL 0
  521 +
  522 +#define PE_GP_INMASK 0
  523 +#define PE_GP_OUTMASK 0
  524 +#define PE_GP_OUTVAL 0
  525 +
  526 +#define PE_SP_MASK 0
  527 +#define PE_ODR_VAL 0
  528 +#define PE_SP_DIRVAL 0
  529 +
  530 +int board_early_init_f(void)
  531 +{
  532 + volatile immap_t *immap = (immap_t *) CFG_IMMR;
  533 + volatile iop8xx_t *ioport = &immap->im_ioport;
  534 + volatile cpm8xx_t *cpm = &immap->im_cpm;
  535 + volatile memctl8xx_t *memctl = &immap->im_memctl;
  536 +
  537 + (void)ioport;
  538 + (void)cpm;
  539 +#if 1
  540 + /* NAND chip select */
  541 + upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
  542 + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
  543 + memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
  544 + memctl->memc_mbmr = 0; /* all clear */
  545 +#endif
  546 +
  547 + memctl->memc_br5 &= ~BR_V;
  548 + memctl->memc_br6 &= ~BR_V;
  549 + memctl->memc_br7 &= ~BR_V;
  550 +
  551 +#if 1
  552 + ioport->iop_padat = PA_GP_OUTVAL;
  553 + ioport->iop_paodr = PA_ODR_VAL;
  554 + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
  555 + ioport->iop_papar = PA_SP_MASK;
  556 +
  557 + cpm->cp_pbdat = PB_GP_OUTVAL;
  558 + cpm->cp_pbodr = PB_ODR_VAL;
  559 + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
  560 + cpm->cp_pbpar = PB_SP_MASK;
  561 +
  562 + ioport->iop_pcdat = PC_GP_OUTVAL;
  563 + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
  564 + ioport->iop_pcso = PC_SOVAL;
  565 + ioport->iop_pcint = PC_INTVAL;
  566 + ioport->iop_pcpar = PC_SP_MASK;
  567 +
  568 + cpm->cp_pedat = PE_GP_OUTVAL;
  569 + cpm->cp_peodr = PE_ODR_VAL;
  570 + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
  571 + cpm->cp_pepar = PE_SP_MASK;
  572 +#endif
  573 +
  574 + return 0;
  575 +}
  576 +
  577 +#if (CONFIG_COMMANDS & CFG_CMD_NAND)
  578 +
  579 +#include <linux/mtd/nand.h>
  580 +
  581 +extern ulong nand_probe(ulong physadr);
  582 +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
  583 +
  584 +void nand_init(void)
  585 +{
  586 + unsigned long totlen;
  587 +
  588 + totlen = nand_probe(CFG_NAND_BASE);
  589 + printf ("%4lu MB\n", totlen >> 20);
  590 +}
  591 +#endif
  592 +
  593 +#ifdef CONFIG_HW_WATCHDOG
  594 +
  595 +void hw_watchdog_reset(void)
  596 +{
  597 + /* XXX add here the really funky stuff */
  598 +}
  599 +
  600 +#endif
  601 +
  602 +#ifdef CONFIG_SHOW_ACTIVITY
  603 +
  604 +/* called from timer interrupt every 1/CFG_HZ sec */
  605 +void board_show_activity(ulong timestamp)
  606 +{
  607 +}
  608 +
  609 +/* called when looping */
  610 +void show_activity(int arg)
  611 +{
  612 +}
  613 +
  614 +#endif
  615 +
  616 +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
  617 +int overwrite_console(void)
  618 +{
  619 + /* printf("overwrite_console called\n"); */
  620 + return 0;
  621 +}
  622 +#endif
  623 +
  624 +extern int drv_phone_init(void);
  625 +extern int drv_phone_use_me(void);
  626 +extern int drv_phone_is_idle(void);
  627 +
  628 +int misc_init_r(void)
  629 +{
  630 + return 0;
  631 +}
  632 +
  633 +int last_stage_init(void)
  634 +{
  635 + reset_phys();
  636 +
  637 + return 0;
  638 +}
board/stxxtc/u-boot.lds
Diff comments   View file @ 6bdf430
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_ARCH(powerpc)
  25 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  26 +/* Do we need any of these for elf?
  27 + __DYNAMIC = 0; */
  28 +SECTIONS
  29 +{
  30 + /* Read-only sections, merged into text segment: */
  31 + . = + SIZEOF_HEADERS;
  32 + .interp : { *(.interp) }
  33 + .hash : { *(.hash) }
  34 + .dynsym : { *(.dynsym) }
  35 + .dynstr : { *(.dynstr) }
  36 + .rel.text : { *(.rel.text) }
  37 + .rela.text : { *(.rela.text) }
  38 + .rel.data : { *(.rel.data) }
  39 + .rela.data : { *(.rela.data) }
  40 + .rel.rodata : { *(.rel.rodata) }
  41 + .rela.rodata : { *(.rela.rodata) }
  42 + .rel.got : { *(.rel.got) }
  43 + .rela.got : { *(.rela.got) }
  44 + .rel.ctors : { *(.rel.ctors) }
  45 + .rela.ctors : { *(.rela.ctors) }
  46 + .rel.dtors : { *(.rel.dtors) }
  47 + .rela.dtors : { *(.rela.dtors) }
  48 + .rel.bss : { *(.rel.bss) }
  49 + .rela.bss : { *(.rela.bss) }
  50 + .rel.plt : { *(.rel.plt) }
  51 + .rela.plt : { *(.rela.plt) }
  52 + .init : { *(.init) }
  53 + .plt : { *(.plt) }
  54 + .text :
  55 + {
  56 + cpu/mpc8xx/start.o (.text)
  57 + cpu/mpc8xx/traps.o (.text)
  58 + common/dlmalloc.o (.text)
  59 + lib_ppc/ppcstring.o (.text)
  60 + lib_generic/vsprintf.o (.text)
  61 + lib_generic/crc32.o (.text)
  62 + lib_generic/zlib.o (.text)
  63 + lib_ppc/cache.o (.text)
  64 + lib_ppc/time.o (.text)
  65 +
  66 + . = DEFINED(env_offset) ? env_offset : .;
  67 + common/environment.o (.text)
  68 +
  69 + *(.text)
  70 + *(.fixup)
  71 + *(.got1)
  72 + }
  73 + _etext = .;
  74 + PROVIDE (etext = .);
  75 + .rodata :
  76 + {
  77 + *(.rodata)
  78 + *(.rodata1)
  79 + *(.rodata.str1.4)
  80 + }
  81 + .fini : { *(.fini) } =0
  82 + .ctors : { *(.ctors) }
  83 + .dtors : { *(.dtors) }
  84 +
  85 + /* Read-write section, merged into data segment: */
  86 + . = (. + 0x00FF) & 0xFFFFFF00;
  87 + _erotext = .;
  88 + PROVIDE (erotext = .);
  89 + .reloc :
  90 + {
  91 + *(.got)
  92 + _GOT2_TABLE_ = .;
  93 + *(.got2)
  94 + _FIXUP_TABLE_ = .;
  95 + *(.fixup)
  96 + }
  97 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  98 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  99 +
  100 + .data :
  101 + {
  102 + *(.data)
  103 + *(.data1)
  104 + *(.sdata)
  105 + *(.sdata2)
  106 + *(.dynamic)
  107 + CONSTRUCTORS
  108 + }
  109 + _edata = .;
  110 + PROVIDE (edata = .);
  111 +
  112 + __u_boot_cmd_start = .;
  113 + .u_boot_cmd : { *(.u_boot_cmd) }
  114 + __u_boot_cmd_end = .;
  115 +
  116 +
  117 + __start___ex_table = .;
  118 + __ex_table : { *(__ex_table) }
  119 + __stop___ex_table = .;
  120 +
  121 + . = ALIGN(256);
  122 + __init_begin = .;
  123 + .text.init : { *(.text.init) }
  124 + .data.init : { *(.data.init) }
  125 + . = ALIGN(256);
  126 + __init_end = .;
  127 +
  128 + __bss_start = .;
  129 + .bss :
  130 + {
  131 + *(.sbss) *(.scommon)
  132 + *(.dynbss)
  133 + *(.bss)
  134 + *(COMMON)
  135 + }
  136 + _end = . ;
  137 + PROVIDE (end = .);
  138 +}
board/stxxtc/u-boot.lds.debug
Diff comments   View file @ 6bdf430
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_ARCH(powerpc)
  25 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  26 +/* Do we need any of these for elf?
  27 + __DYNAMIC = 0; */
  28 +SECTIONS
  29 +{
  30 + /* Read-only sections, merged into text segment: */
  31 + . = + SIZEOF_HEADERS;
  32 + .interp : { *(.interp) }
  33 + .hash : { *(.hash) }
  34 + .dynsym : { *(.dynsym) }
  35 + .dynstr : { *(.dynstr) }
  36 + .rel.text : { *(.rel.text) }
  37 + .rela.text : { *(.rela.text) }
  38 + .rel.data : { *(.rel.data) }
  39 + .rela.data : { *(.rela.data) }
  40 + .rel.rodata : { *(.rel.rodata) }
  41 + .rela.rodata : { *(.rela.rodata) }
  42 + .rel.got : { *(.rel.got) }
  43 + .rela.got : { *(.rela.got) }
  44 + .rel.ctors : { *(.rel.ctors) }
  45 + .rela.ctors : { *(.rela.ctors) }
  46 + .rel.dtors : { *(.rel.dtors) }
  47 + .rela.dtors : { *(.rela.dtors) }
  48 + .rel.bss : { *(.rel.bss) }
  49 + .rela.bss : { *(.rela.bss) }
  50 + .rel.plt : { *(.rel.plt) }
  51 + .rela.plt : { *(.rela.plt) }
  52 + .init : { *(.init) }
  53 + .plt : { *(.plt) }
  54 + .text :
  55 + {
  56 + /* WARNING - the following is hand-optimized to fit within */
  57 + /* the sector layout of our flash chips! XXX FIXME XXX */
  58 +
  59 + cpu/mpc8xx/start.o (.text)
  60 + common/dlmalloc.o (.text)
  61 + lib_generic/vsprintf.o (.text)
  62 + lib_generic/crc32.o (.text)
  63 +
  64 + . = env_offset;
  65 + common/environment.o(.text)
  66 +
  67 + *(.text)
  68 + *(.fixup)
  69 + *(.got1)
  70 + }
  71 + _etext = .;
  72 + PROVIDE (etext = .);
  73 + .rodata :
  74 + {
  75 + *(.rodata)
  76 + *(.rodata1)
  77 + }
  78 + .fini : { *(.fini) } =0
  79 + .ctors : { *(.ctors) }
  80 + .dtors : { *(.dtors) }
  81 +
  82 + /* Read-write section, merged into data segment: */
  83 + . = (. + 0x0FFF) & 0xFFFFF000;
  84 + _erotext = .;
  85 + PROVIDE (erotext = .);
  86 + .reloc :
  87 + {
  88 + *(.got)
  89 + _GOT2_TABLE_ = .;
  90 + *(.got2)
  91 + _FIXUP_TABLE_ = .;
  92 + *(.fixup)
  93 + }
  94 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  95 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  96 +
  97 + .data :
  98 + {
  99 + *(.data)
  100 + *(.data1)
  101 + *(.sdata)
  102 + *(.sdata2)
  103 + *(.dynamic)
  104 + CONSTRUCTORS
  105 + }
  106 + _edata = .;
  107 + PROVIDE (edata = .);
  108 +
  109 + __u_boot_cmd_start = .;
  110 + .u_boot_cmd : { *(.u_boot_cmd) }
  111 + __u_boot_cmd_end = .;
  112 +
  113 +
  114 + __start___ex_table = .;
  115 + __ex_table : { *(__ex_table) }
  116 + __stop___ex_table = .;
  117 +
  118 + . = ALIGN(4096);
  119 + __init_begin = .;
  120 + .text.init : { *(.text.init) }
  121 + .data.init : { *(.data.init) }
  122 + . = ALIGN(4096);
  123 + __init_end = .;
  124 +
  125 + __bss_start = .;
  126 + .bss :
  127 + {
  128 + *(.sbss) *(.scommon)
  129 + *(.dynbss)
  130 + *(.bss)
  131 + *(COMMON)
  132 + }
  133 + _end = . ;
  134 + PROVIDE (end = .);
  135 +}
  1 +
  2 +
  3 +First, some build notes on the Silicon Turnkey eXpress XTc.
  4 +
  5 +This board has both 87x/88x procesor options at various
  6 +frequencies. The configuration file has some macros for setting
  7 +the clock speed, not all have been tested. They all have
  8 +a 10MHz input clock. Please do not check in a configuration
  9 +file that selects a high speed not available on all processors.
  10 +We chose the 66MHz core and bus speed, which should be OK on
  11 +all boards. If you have a processor, lucky you! :-)
  12 +Just build a new configuration with that speed, check
  13 +the macro configuration to ensure it's correct. If the
  14 +macro is updated, please check that in, but keep default
  15 +processor speed.
  16 +
  17 +The board is likely to have more than 1Mbyte of NOR boot flash.
  18 +It was also configured with a high boot vector (Dan's fault)
  19 +so the standard 8xx mapping doesn't work well. We had to move
  20 +the addresses around a little bit so one copy would work. The
  21 +flash got fragmented, and we are working on a better solution.
  22 +There is an "xtc.cfg" floating around for the BDI2000, use
  23 +that for programming a new version of U-Boot. You can probably
  24 +find it on the Silicon Turnkey eXpress (www.silicontkx.com),
  25 +Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de)
  26 +servers.
  27 +
  28 +The board will also have various SDRAM sizes, but the code
  29 +should automatically determine the amount of memory.
  30 +
  31 +There are a couple of different board versions, visually
  32 +they use different BGA or surface mount memory parts. However,
  33 +they are logically the same board.
  34 +
  35 +Now, some operational notes.
  36 +
  37 +The board has the option of sporting two FEC Ethernet ports.
  38 +The second port isn't configured to be automatically available
  39 +because it would cause U-Boot to generate a board data structure
  40 +(the bd_t) with multiple MAC addresses and be incompatible with
  41 +standard 8xx kernel builds. You can use/test the second FEC
  42 +in U-Boot by assigning an 'eth1addr' and selecting the second
  43 +FEC as the port to use.
  44 +
  45 +Since this is just a development board and not a product, STx
  46 +does not assign unique MAC addresses. We just pilfer the
  47 +"default" ones used by Wolfgang on some other boards. Please
  48 +ensure you assign unique MAC addresses when using these boards.
  49 +
  50 +The serial port baud rate is 38400, because that's the way
  51 +I like it :-)
  52 +
  53 +Thanks to Pantelis for lots of the work on this board port.
  54 +
  55 +Have Fun!
  56 +
  57 + -- Dan
  58 +
  59 +15 August 2005
include/configs/stxxtc.h
Diff comments   View file @ 6bdf430
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
  26 + * U-Boot port on STx XTc 8xx board
  27 + * Mostly copied from Panto's NETTA2 board.
  28 + */
  29 +
  30 +#ifndef __CONFIG_H
  31 +#define __CONFIG_H
  32 +
  33 +/*
  34 + * High Level Configuration Options
  35 + * (easy to change)
  36 + */
  37 +
  38 +#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
  39 +#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
  40 +
  41 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  42 +#undef CONFIG_8xx_CONS_SMC2
  43 +#undef CONFIG_8xx_CONS_NONE
  44 +
  45 +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
  46 +
  47 +#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
  48 +
  49 +/* Select one of few clock rates defined later in this file.
  50 +*/
  51 +/* #define MPC8XX_HZ 50000000 */
  52 +#define MPC8XX_HZ 66666666
  53 +
  54 +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
  55 +
  56 +#if 0
  57 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  58 +#else
  59 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  60 +#endif
  61 +
  62 +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
  63 +
  64 +#undef CONFIG_BOOTARGS
  65 +#define CONFIG_BOOTCOMMAND \
  66 + "tftpboot; " \
  67 + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  68 + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  69 + "bootm"
  70 +
  71 +#define CONFIG_AUTOSCRIPT
  72 +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
  73 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  74 +
  75 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  76 +
  77 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  78 +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
  79 +
  80 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
  81 +
  82 +#undef CONFIG_MAC_PARTITION
  83 +#undef CONFIG_DOS_PARTITION
  84 +
  85 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
  86 +
  87 +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
  88 +#define FEC_ENET 1 /* eth.c needs it that way... */
  89 +#undef CFG_DISCOVER_PHY
  90 +#define CONFIG_MII 1
  91 +#undef CONFIG_RMII
  92 +
  93 +#define CONFIG_ETHER_ON_FEC1 1
  94 +#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
  95 +#undef CONFIG_FEC1_PHY_NORXERR
  96 +
  97 +#define CONFIG_ETHER_ON_FEC2 1
  98 +#define CONFIG_FEC2_PHY 3
  99 +#undef CONFIG_FEC2_PHY_NORXERR
  100 +
  101 +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
  102 +
  103 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  104 + CFG_CMD_NAND | \
  105 + CFG_CMD_DHCP | \
  106 + CFG_CMD_PING | \
  107 + CFG_CMD_MII | \
  108 + CFG_CMD_NFS)
  109 +
  110 +#define CONFIG_BOARD_EARLY_INIT_F 1
  111 +#define CONFIG_MISC_INIT_R
  112 +
  113 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  114 +#include <cmd_confdefs.h>
  115 +
  116 +/*
  117 + * Miscellaneous configurable options
  118 + */
  119 +#define CFG_LONGHELP /* undef to save memory */
  120 +#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */
  121 +
  122 +#define CFG_HUSH_PARSER 1
  123 +#define CFG_PROMPT_HUSH_PS2 "> "
  124 +
  125 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  126 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  127 +#else
  128 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  129 +#endif
  130 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  131 +#define CFG_MAXARGS 16 /* max number of command args */
  132 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  133 +
  134 +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
  135 +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
  136 +
  137 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  138 +
  139 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  140 +
  141 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  142 +
  143 +/*
  144 + * Low Level Configuration Settings
  145 + * (address mappings, register initial values, etc.)
  146 + * You should know what you are doing if you make changes here.
  147 + */
  148 +/*-----------------------------------------------------------------------
  149 + * Internal Memory Mapped Register
  150 + */
  151 +#define CFG_IMMR 0xFF000000
  152 +
  153 +/*-----------------------------------------------------------------------
  154 + * Definitions for initial stack pointer and data area (in DPRAM)
  155 + */
  156 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  157 +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
  158 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  159 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  160 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  161 +
  162 +/*-----------------------------------------------------------------------
  163 + * Start addresses for the final memory configuration
  164 + * (Set up by the startup code)
  165 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  166 + */
  167 +#define CFG_SDRAM_BASE 0x00000000
  168 +#define CFG_FLASH_BASE 0x40000000
  169 +#if defined(DEBUG)
  170 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  171 +#else
  172 +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
  173 +#endif
  174 +
  175 +/* yes this is weird, I know :) */
  176 +#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000)
  177 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  178 +
  179 +#define CFG_RESET_ADDRESS 0x80000000
  180 +
  181 +/*
  182 + * For booting Linux, the board info and command line data
  183 + * have to be in the first 8 MB of memory, since this is
  184 + * the maximum mapped by the Linux kernel during initialization.
  185 + */
  186 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  187 +
  188 +/*-----------------------------------------------------------------------
  189 + * FLASH organization
  190 + */
  191 +#define CFG_ENV_IS_IN_FLASH 1
  192 +#define CFG_ENV_SECT_SIZE 0x10000
  193 +
  194 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
  195 +#define CFG_ENV_OFFSET 0
  196 +#define CFG_ENV_SIZE 0x4000
  197 +
  198 +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000)
  199 +#define CFG_ENV_OFFSET_REDUND 0
  200 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
  201 +
  202 +#define CFG_FLASH_CFI 1
  203 +#define CFG_FLASH_CFI_DRIVER 1
  204 +#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
  205 +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  206 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  207 +
  208 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
  209 +
  210 +#define CFG_FLASH_PROTECTION
  211 +
  212 +/*-----------------------------------------------------------------------
  213 + * Cache Configuration
  214 + */
  215 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  216 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  217 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  218 +#endif
  219 +
  220 +/*-----------------------------------------------------------------------
  221 + * SYPCR - System Protection Control 11-9
  222 + * SYPCR can only be written once after reset!
  223 + *-----------------------------------------------------------------------
  224 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  225 + */
  226 +#if defined(CONFIG_WATCHDOG)
  227 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  228 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  229 +#else
  230 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  231 +#endif
  232 +
  233 +/*-----------------------------------------------------------------------
  234 + * SIUMCR - SIU Module Configuration 11-6
  235 + *-----------------------------------------------------------------------
  236 + * PCMCIA config., multi-function pin tri-state
  237 + */
  238 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
  239 +
  240 +/*-----------------------------------------------------------------------
  241 + * TBSCR - Time Base Status and Control 11-26
  242 + *-----------------------------------------------------------------------
  243 + * Clear Reference Interrupt Status, Timebase freezing enabled
  244 + */
  245 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  246 +
  247 +/*-----------------------------------------------------------------------
  248 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  249 + *-----------------------------------------------------------------------
  250 + */
  251 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  252 +
  253 +/*-----------------------------------------------------------------------
  254 + * PISCR - Periodic Interrupt Status and Control 11-31
  255 + *-----------------------------------------------------------------------
  256 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  257 + */
  258 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  259 +
  260 +/*-----------------------------------------------------------------------
  261 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  262 + *-----------------------------------------------------------------------
  263 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  264 + * interrupt status bit
  265 + *
  266 + */
  267 +
  268 +#if CONFIG_XIN == 10000000
  269 +
  270 +#if MPC8XX_HZ == 50000000
  271 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
  272 + (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
  273 + PLPRCR_TEXPS)
  274 +#elif MPC8XX_HZ == 66666666
  275 +#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
  276 + (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
  277 + PLPRCR_TEXPS)
  278 +#else
  279 +#error unsupported CPU freq for XIN = 10MHz
  280 +#endif
  281 +#else
  282 +#error unsupported freq for XIN (must be 10MHz)
  283 +#endif
  284 +
  285 +
  286 +/*
  287 + *-----------------------------------------------------------------------
  288 + * SCCR - System Clock and reset Control Register 15-27
  289 + *-----------------------------------------------------------------------
  290 + * Set clock output, timebase and RTC source and divider,
  291 + * power management and some other internal clocks
  292 + *
  293 + * Note: When TBS == 0 the timebase is independent of current cpu clock.
  294 + */
  295 +
  296 +#define SCCR_MASK SCCR_EBDF11
  297 +#if MPC8XX_HZ > 66666666
  298 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
  299 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  300 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  301 + SCCR_DFALCD00 | SCCR_EBDF01)
  302 +#else
  303 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
  304 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  305 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  306 + SCCR_DFALCD00)
  307 +#endif
  308 +
  309 +/*-----------------------------------------------------------------------
  310 + *
  311 + *-----------------------------------------------------------------------
  312 + *
  313 + */
  314 +/*#define CFG_DER 0x2002000F*/
  315 +#define CFG_DER 0
  316 +
  317 +/*
  318 + * Init Memory Controller:
  319 + *
  320 + * BR0/1 and OR0/1 (FLASH)
  321 + */
  322 +
  323 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  324 +#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
  325 +
  326 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  327 + * restrict access enough to keep SRAM working (if any)
  328 + * but not too much to meddle with FLASH accesses
  329 + */
  330 +
  331 +#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
  332 +
  333 +#define CFG_REMAP_OR_AM 0x80000000
  334 +#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
  335 +
  336 +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
  337 +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
  338 +
  339 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  340 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  341 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
  342 +
  343 +#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
  344 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
  345 +
  346 +/*
  347 + * BR4 and OR4 (SDRAM)
  348 + *
  349 + */
  350 +#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
  351 +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
  352 +
  353 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  354 +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
  355 +
  356 +#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
  357 +#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
  358 +
  359 +/*
  360 + * Memory Periodic Timer Prescaler
  361 + */
  362 +
  363 +/*
  364 + * Memory Periodic Timer Prescaler
  365 + *
  366 + * The Divider for PTA (refresh timer) configuration is based on an
  367 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  368 + * the number of chip selects (NCS) and the actually needed refresh
  369 + * rate is done by setting MPTPR.
  370 + *
  371 + * PTA is calculated from
  372 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  373 + *
  374 + * gclk CPU clock (not bus clock!)
  375 + * Trefresh Refresh cycle * 4 (four word bursts used)
  376 + *
  377 + * 4096 Rows from SDRAM example configuration
  378 + * 1000 factor s -> ms
  379 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  380 + * 4 Number of refresh cycles per period
  381 + * 64 Refresh cycle in ms per number of rows
  382 + * --------------------------------------------
  383 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  384 + *
  385 + * 50 MHz => 50.000.000 / Divider = 98
  386 + * 66 Mhz => 66.000.000 / Divider = 129
  387 + * 80 Mhz => 80.000.000 / Divider = 156
  388 + */
  389 +
  390 +#define CFG_MAMR_PTA 234
  391 +
  392 +/*
  393 + * For 16 MBit, refresh rates could be 31.3 us
  394 + * (= 64 ms / 2K = 125 / quad bursts).
  395 + * For a simpler initialization, 15.6 us is used instead.
  396 + *
  397 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  398 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  399 + */
  400 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  401 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  402 +
  403 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  404 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  405 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  406 +
  407 +/*
  408 + * MAMR settings for SDRAM
  409 + */
  410 +
  411 +/* 8 column SDRAM */
  412 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  413 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  414 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  415 +
  416 +/* 9 column SDRAM */
  417 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  418 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  419 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  420 +
  421 +/*
  422 + * Internal Definitions
  423 + *
  424 + * Boot Flags
  425 + */
  426 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  427 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  428 +
  429 +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
  430 +
  431 +/****************************************************************/
  432 +
  433 +#define NAND_SIZE 0x00010000 /* 64K */
  434 +#define NAND_BASE 0xF1000000
  435 +
  436 +/****************************************************************/
  437 +
  438 +/* NAND */
  439 +#define CFG_NAND_BASE NAND_BASE
  440 +#define CONFIG_MTD_NAND_ECC_JFFS2
  441 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  442 +#define CONFIG_MTD_NAND_UNSAFE
  443 +
  444 +#define CFG_MAX_NAND_DEVICE 1
  445 +#undef NAND_NO_RB
  446 +
  447 +#define SECTORSIZE 512
  448 +#define ADDR_COLUMN 1
  449 +#define ADDR_PAGE 2
  450 +#define ADDR_COLUMN_PAGE 3
  451 +#define NAND_ChipID_UNKNOWN 0x00
  452 +#define NAND_MAX_FLOORS 1
  453 +#define NAND_MAX_CHIPS 1
  454 +
  455 +/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
  456 +#define NAND_DISABLE_CE(nand) \
  457 + do { \
  458 + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
  459 + } while(0)
  460 +
  461 +#define NAND_ENABLE_CE(nand) \
  462 + do { \
  463 + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
  464 + } while(0)
  465 +
  466 +#define NAND_CTL_CLRALE(nandptr) \
  467 + do { \
  468 + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
  469 + } while(0)
  470 +
  471 +#define NAND_CTL_SETALE(nandptr) \
  472 + do { \
  473 + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
  474 + } while(0)
  475 +
  476 +#define NAND_CTL_CLRCLE(nandptr) \
  477 + do { \
  478 + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
  479 + } while(0)
  480 +
  481 +#define NAND_CTL_SETCLE(nandptr) \
  482 + do { \
  483 + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
  484 + } while(0)
  485 +
  486 +#ifndef NAND_NO_RB
  487 +#define NAND_WAIT_READY(nand) \
  488 + do { \
  489 + int _tries = 0; \
  490 + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
  491 + if (++_tries > 100000) \
  492 + break; \
  493 + } while (0)
  494 +#else
  495 +#define NAND_WAIT_READY(nand) udelay(12)
  496 +#endif
  497 +
  498 +#define WRITE_NAND_COMMAND(d, adr) \
  499 + do { \
  500 + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
  501 + } while(0)
  502 +
  503 +#define WRITE_NAND_ADDRESS(d, adr) \
  504 + do { \
  505 + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
  506 + } while(0)
  507 +
  508 +#define WRITE_NAND(d, adr) \
  509 + do { \
  510 + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
  511 + } while(0)
  512 +
  513 +#define READ_NAND(adr) \
  514 + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
  515 +
  516 +/*****************************************************************************/
  517 +
  518 +#define CFG_DIRECT_FLASH_TFTP
  519 +#define CFG_DIRECT_NAND_TFTP
  520 +
  521 +/*****************************************************************************/
  522 +
  523 +/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
  524 + * CxOE and CxRESET. We use the CxOE.
  525 + */
  526 +#define STATUS_LED_BIT 0x00000080 /* bit 24 */
  527 +
  528 +#define STATUS_LED_PERIOD (CFG_HZ / 2)
  529 +#define STATUS_LED_STATE STATUS_LED_BLINKING
  530 +
  531 +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
  532 +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
  533 +
  534 +#ifndef __ASSEMBLY__
  535 +
  536 +/* LEDs */
  537 +
  538 +/* led_id_t is unsigned int mask */
  539 +typedef unsigned int led_id_t;
  540 +
  541 +#define __led_toggle(_msk) \
  542 + do { \
  543 + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
  544 + } while(0)
  545 +
  546 +#define __led_set(_msk, _st) \
  547 + do { \
  548 + if ((_st)) \
  549 + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
  550 + else \
  551 + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
  552 + } while(0)
  553 +
  554 +#define __led_init(msk, st) __led_set(msk, st)
  555 +
  556 +#endif
  557 +
  558 +/******************************************************************************/
  559 +
  560 +#define CFG_CONSOLE_IS_IN_ENV 1
  561 +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
  562 +#define CFG_CONSOLE_ENV_OVERWRITE 1
  563 +
  564 +/******************************************************************************/
  565 +
  566 +/* use board specific hardware */
  567 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  568 +#define CONFIG_HW_WATCHDOG
  569 +#define CONFIG_SHOW_ACTIVITY
  570 +
  571 +/*****************************************************************************/
  572 +
  573 +#define CONFIG_AUTO_COMPLETE 1
  574 +#define CONFIG_CRC32_VERIFY 1
  575 +#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
  576 +
  577 +/* Note: change below for your network setting!!!
  578 + * This was done just to facilitate manufacturing test and configuration.
  579 + */
  580 +#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
  581 +
  582 +#define CONFIG_SERVERIP 192.168.08.1
  583 +#define CONFIG_IPADDR 192.168.08.85
  584 +#define CONFIG_GATEWAYIP 192.168.08.1
  585 +#define CONFIG_NETMASK 255.255.255.0
  586 +#define CONFIG_HOSTNAME stx_xtc
  587 +#define CONFIG_ROOTPATH /xtcroot
  588 +#define CONFIG_BOOTFILE uImage
  589 +#define CONFIG_LOADADDR 0x1000000
  590 +
  591 +
  592 +#endif /* __CONFIG_H */
include/status_led.h
Diff comments   View file @ 6bdf430
... ... @@ -336,6 +336,9 @@
336 336 /***** NetPhone ********************************************************/
337 337 #elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
338 338 /* XXX empty just to avoid the error */
  339 +/***** STx XTc ********************************************************/
  340 +#elif defined(CONFIG_STXXTC)
  341 +/* XXX empty just to avoid the error */
339 342 /***** sbc8240 ********************************************************/
340 343 #elif defined(CONFIG_WRSBC8240)
341 344 /* XXX empty just to avoid the error */