Patch by Mark Jonas, 01 Jul 2004:

Added support for Total5100 and Total5200 (Rev.1 and Rev.2) MGT5100 and MPC5200 based Freescale platforms.

Patch by Mark Jonas, 01 Jul 2004:
Added support for Total5100 and Total5200 (Rev.1 and Rev.2) MGT5100 and MPC5200 based Freescale platforms.
wdenk
1 parent bc54f309a1
Showing 17 changed files with 1158 additions and 1 deletions Side-by-side Diff
CHANGELOG
CREDITS
MAKEALL
Makefile
board/total5200/Makefile
board/total5200/config.mk
board/total5200/mt48lc16m16a2-75.h
board/total5200/mt48lc32m16a2-75.h
board/total5200/sdram.c
board/total5200/sdram.h
board/total5200/total5200.c
board/total5200/u-boot.lds
cpu/mpc5xxx/fec.c
cpu/mpc5xxx/ide.c
cpu/mpc5xxx/start.S
include/configs/Total5200.h
include/mpc5xxx.h
@@ -2,6 +2,10 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
  
+* Patch by Mark Jonas, 01 Jul 2004:
+  Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
+  MGT5100 and MPC5200 based Freescale platforms.
+
 * Patch by Philippe Robin, 01 Jul 2004:
   Add initialization for Integrator and versatile board files.
  
@@ -206,6 +206,11 @@
 E: yooth@ipone.co.kr
 D: Added port to the RPXlite board
  
+N: Mark Jonas
+E: mark.jonas@freescale.com
+D: Support for Freescale Total5200 platform
+W: http://www.mobilegt.com/
+
 N: Sam Song
 E: samsongshu@yahoo.com.cn
 D: Port to the RPXlite_DW board
@@ -26,7 +26,7 @@
  
 LIST_5xxx="	\
 	icecube_5100	icecube_5200	EVAL5200	PM520		\
-	TQM5200_AA							\
+	Total5100	Total5200	Total5200_Rev2	TQM5200_AA	\
 "
  
 #########################################################################
@@ -255,6 +255,34 @@
 	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
 	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
  
+Total5100_config		\
+Total5200_config		\
+Total5200_lowboot_config	\
+Total5200_Rev2_config		\
+Total5200_Rev2_lowboot_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring 5100,$@)" ] || \
+		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
+		  echo "... with MGT5100 processor" ; \
+		}
+	@[ -z "$(findstring 5200,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
+		  echo "... with MPC5200 processor" ; \
+		}
+	@[ -n "$(findstring Rev,$@)" ] || \
+		{ echo "#define CONFIG_TOTAL5200_REV 1"	>>include/config.h ; \
+		  echo "... revision 1 board" ; \
+		}
+	@[ -z "$(findstring Rev2_,$@)" ] || \
+		{ echo "#define CONFIG_TOTAL5200_REV 2"	>>include/config.h ; \
+		  echo "... revision 2 board" ; \
+		}
+	@[ -z "$(findstring lowboot_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \
+		  echo "... with lowboot configuration" ; \
+		}
+	@./mkconfig -a Total5200 ppc mpc5xxx total5200
+
 PM520_config \
 PM520_DDR_config \
 PM520_ROMBOOT_config \
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o sdram.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Total5200 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFE000000   boot low
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Micron MT48LC32M16A2-75 is compatible to:
+ *  - Infineon HYB39S512160AT-75
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x514F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#else
+#error CONFIG_MPC5200 is not defined
+#endif
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+#include "sdram.h"
+
+#ifndef CFG_RAMBOOT
+static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	if (sdram_conf->ddr) {
+		/* set mode register: extended mode */
+		*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
+		__asm__ volatile ("sync");
+
+		/* set mode register: reset DLL */
+		*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
+		__asm__ volatile ("sync");
+	}
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
+	__asm__ volatile ("sync");
+
+	if (sdram_conf->ddr) {
+		/* set tap delay */
+		*(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
+		__asm__ volatile ("sync");
+	}
+
+	/* find RAM size using SDRAM CS0 only */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct {
+	ulong ddr;
+	ulong mode;
+	ulong emode;
+	ulong control;
+	ulong config1;
+	ulong config2;
+#if defined(CONFIG_MPC5200)
+	ulong tapdelay;
+#endif
+#if defined(CONFIG_MGT5100)
+	ulong addrsel;
+#endif
+} sdram_conf_t;
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include "sdram.h"
+
+#if CONFIG_TOTAL5200_REV==2
+#include "mt48lc32m16a2-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+long int initdram (int board_type)
+{
+	sdram_conf_t sdram_conf;
+
+	sdram_conf.ddr = SDRAM_DDR;
+	sdram_conf.mode = SDRAM_MODE;
+	sdram_conf.emode = 0;
+	sdram_conf.control = SDRAM_CONTROL;
+	sdram_conf.config1 = SDRAM_CONFIG1;
+	sdram_conf.config2 = SDRAM_CONFIG2;
+#if defined(CONFIG_MPC5200)
+	sdram_conf.tapdelay = 0;
+#endif
+#if defined(CONFIG_MGT5100)
+	sdram_conf.addrsel = SDRAM_ADDRSEL;
+#endif
+	return mpc5xxx_sdram_init (&sdram_conf);
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+#if CONFIG_TOTAL5200_REV==2
+	puts ("Board: Total5200 Rev.2 ");
+#else
+	puts ("Board: Total5200 ");
+#endif
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: Total5100 ");
+#endif
+
+/*
+ * Retrieve FPGA Revision.
+ */
+printf ("(FPGA %08X)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400));
+
+/*
+ * Take all peripherals in power-up mode.
+ */
+#if CONFIG_TOTAL5200_REV==2
+	*(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70;
+#else
+	*(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70;
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_MGT5100)
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable CS0
+	 * because CS_BOOT cannot be written.
+	 */
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+
+	return 0;
+}
+#endif
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+/* IRDA_1 aka PSC6_3 (pin C13) */
+#define GPIO_IRDA_1	0x20000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
+	*(vu_long *) MPC5XXX_GPIO_DIR    |= GPIO_IRDA_1;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
+	} else {
+		*(vu_long *) MPC5XXX_GPIO_DATA_O |=  GPIO_IRDA_1;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
@@ -397,7 +397,13 @@
 	 */
 	if (fec->xcv_type == SEVENWIRE) {
 		/*  10MBit with 7-wire operation */
+#if defined(CONFIG_TOTAL5200)
+		/* 7-wire and USB2 on Ethernet */
+		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
+#else	/* !CONFIG_TOTAL5200 */
+		/* 7-wire only */
 		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
+#endif	/* CONFIG_TOTAL5200 */
 	} else {
 		/* 100MBit with MD operation */
 		*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
@@ -870,6 +876,8 @@
 # else
 	fec->xcv_type = MII10;
 # endif
+#elif defined(CONFIG_TOTAL5200)
+	fec->xcv_type = SEVENWIRE;
 #else
 #error fec->xcv_type not initialized.
 #endif
@@ -41,7 +41,13 @@
 	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
  
 	reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
+#if defined(CONFIG_TOTAL5200)
+	/* ATA cs0/1 on i2c2 clk/io */
+	reg = (reg & ~0x03000000ul) | 0x02000000ul;
+#else
+	/* ATA cs0/1 on Local Plus cs4/5 */
 	reg = (reg & ~0x03000000ul) | 0x01000000ul;
+#endif	/* CONFIG_TOTAL5200 */
 	*(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
  
 	/* All sample codes do that... */
@@ -110,6 +110,9 @@
 #if defined(CFG_RAMBOOT)
 #error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
 #endif /* CFG_RAMBOOT */
+#if defined(CFG_LOWBOOT)
+#error CFG_LOWBOOT is incompatible with MGT5100
+#endif /* CFG_LOWBOOT */
 	lis	r4, CFG_DEFAULT_MBAR@h
 	lis	r3,	START_REG(CFG_BOOTCS_START)@h
 	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Check valid setting of revision define.
+ * Total5100 and Total5200 Rev.1 are identical except for the processor.
+ */
+#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
+#error CONFIG_TOTAL5200_REV must be 1 or 2
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+#ifdef CONFIG_MPC5200	/* MGT5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+
+#else	/* MGT5100 */
+
+#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD             0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_IDE	| \
+				 ADD_PCI_CMD	| \
+				 ADD_USB_CMD)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFE000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#if CONFIG_TOTAL5200_REV==2
+#   define CFG_MAX_FLASH_BANKS	3	/* max num of flash banks */
+#   define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
+#else
+#   define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks  */
+#   define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#endif
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CFG_FLASH_BASE	0xFE000000
+#   define CFG_FLASH_SIZE	0x02000000
+#elif CONFIG_TOTAL5200_REV==2
+#   define CFG_FLASH_BASE	0xFA000000
+#   define CFG_FLASH_SIZE	0x06000000
+#endif /* CONFIG_TOTAL5200_REV */
+
+#if !defined(CFG_LOWBOOT)
+#   define CFG_ENV_ADDR		0xFE040000
+#else	/* CFG_LOWBOOT */
+#   define CFG_ENV_ADDR		0xFFF40000
+#endif	/* CFG_LOWBOOT */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_MBAR		0xF0000000	/*   64 kB */
+#define CFG_FPGA_BASE		0xF0010000	/*   64 kB */
+#define CFG_CPLD_BASE		0xF0020000	/*   64 kB */
+#define CFG_LCD_BASE		0xF0100000	/* 2048 kB */
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/* dummy, 7-wire FEC does not have phy address */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
+ * Reserved                                                      0
+ * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
+ * CS7:   Interrupt GPIO on PSC3_5                               0
+ * CS8:   Interrupt GPIO on PSC3_4                               0
+ * ATA:   reset default, changed in ATA driver                   00
+ * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
+ * IRDA:  reset default, changed in IrDA driver                  000
+ * ETHER: reset default, changed in Ethernet driver              0000
+ * PCI_DIS: reset default, changed in PCI driver                 0
+ * USB_SE: reset default, changed in USB driver                  0
+ * USB:   reset default, changed in USB driver                   00
+ * PSC3:  SPI and UART functionality without CD                  1100
+ * Reserved                                                      0
+ * PSC2:  CAN1/2                                                 001
+ * Reserved                                                      0
+ * PSC1:  reset default, changed in AC'97 driver                 000
+ *
+ */
+#define CFG_GPS_PORT_CONFIG	0x00000C10
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#if defined (CONFIG_MGT5100)
+#   define CONFIG_BOARD_EARLY_INIT_R	/* switch from CS_BOOT to CS0 */
+#endif
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CFG_BOOTCS_START	CFG_FLASH_BASE
+#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CFG_CS0_START	CFG_FLASH_BASE
+#   define CFG_CS0_SIZE		0x02000000	/* 32 MB */
+#else
+#   define CFG_BOOTCS_START	(CFG_CS4_START + CFG_CS4_SIZE)
+#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CFG_CS4_START	(CFG_CS5_START + CFG_CS5_SIZE)
+#   define CFG_CS4_SIZE		0x02000000	/* 32 MB */
+#   define CFG_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CFG_CS5_START	CFG_FLASH_BASE
+#   define CFG_CS5_SIZE		0x02000000	/* 32 MB */
+#   define CFG_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#endif
+
+#define CFG_CS1_START		CFG_FPGA_BASE
+#define CFG_CS1_SIZE		0x00010000	/* 64 kB */
+#define CFG_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
+
+#define CFG_CS2_START		CFG_LCD_BASE
+#define CFG_CS2_SIZE		0x00200000	/* 2048 kB */
+#define CFG_CS2_CFG		0x0019FD00	/* 25WS, MX, AL, AA, CE, AS_25, DS_16 */
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CFG_CS3_START	CFG_CPLD_BASE
+#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CFG_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
+#else
+#   define CFG_CS3_START	CFG_CPLD_BASE
+#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CFG_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
+#endif
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
@@ -165,6 +165,23 @@
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
  
+/* Standard GPIO registers (simple, output only and simple interrupt */
+#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)
+#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)
+#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)
+#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)
+#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)
+#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)
+#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)
+#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)
+#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)
+#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)
+
 /* WakeUp GPIO registers */
 #define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
 #define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
...	...	@@ -2,6 +2,10 @@
2	2	Changes since U-Boot 1.1.1:
3	3	======================================================================
4	4
	5	+* Patch by Mark Jonas, 01 Jul 2004:
	6	+ Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
	7	+ MGT5100 and MPC5200 based Freescale platforms.
	8	+
5	9	* Patch by Philippe Robin, 01 Jul 2004:
6	10	Add initialization for Integrator and versatile board files.
7	11
...	...	@@ -206,6 +206,11 @@
206	206	E: yooth@ipone.co.kr
207	207	D: Added port to the RPXlite board
208	208
	209	+N: Mark Jonas
	210	+E: mark.jonas@freescale.com
	211	+D: Support for Freescale Total5200 platform
	212	+W: http://www.mobilegt.com/
	213	+
209	214	N: Sam Song
210	215	E: samsongshu@yahoo.com.cn
211	216	D: Port to the RPXlite_DW board
...	...	@@ -26,7 +26,7 @@
26	26
27	27	LIST_5xxx=" \
28	28	icecube_5100 icecube_5200 EVAL5200 PM520 \
29		- TQM5200_AA \
	29	+ Total5100 Total5200 Total5200_Rev2 TQM5200_AA \
30	30	"
31	31
32	32	#########################################################################
...	...	@@ -255,6 +255,34 @@
255	255	@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
256	256	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
257	257
	258	+Total5100_config \
	259	+Total5200_config \
	260	+Total5200_lowboot_config \
	261	+Total5200_Rev2_config \
	262	+Total5200_Rev2_lowboot_config: unconfig
	263	+ @ >include/config.h
	264	+ @[ -z "$(findstring 5100,$@)" ] \|\| \
	265	+ { echo "#define CONFIG_MGT5100" >>include/config.h ; \
	266	+ echo "... with MGT5100 processor" ; \
	267	+ }
	268	+ @[ -z "$(findstring 5200,$@)" ] \|\| \
	269	+ { echo "#define CONFIG_MPC5200" >>include/config.h ; \
	270	+ echo "... with MPC5200 processor" ; \
	271	+ }
	272	+ @[ -n "$(findstring Rev,$@)" ] \|\| \
	273	+ { echo "#define CONFIG_TOTAL5200_REV 1" >>include/config.h ; \
	274	+ echo "... revision 1 board" ; \
	275	+ }
	276	+ @[ -z "$(findstring Rev2_,$@)" ] \|\| \
	277	+ { echo "#define CONFIG_TOTAL5200_REV 2" >>include/config.h ; \
	278	+ echo "... revision 2 board" ; \
	279	+ }
	280	+ @[ -z "$(findstring lowboot_,$@)" ] \|\| \
	281	+ { echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \
	282	+ echo "... with lowboot configuration" ; \
	283	+ }
	284	+ @./mkconfig -a Total5200 ppc mpc5xxx total5200
	285	+
258	286	PM520_config \
259	287	PM520_DDR_config \
260	288	PM520_ROMBOOT_config \
	1	+#
	2	+# (C) Copyright 2003-2004
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = lib$(BOARD).a
	27	+
	28	+OBJS := $(BOARD).o sdram.o
	29	+
	30	+$(LIB): $(OBJS) $(SOBJS)
	31	+ $(AR) crv $@ $(OBJS)
	32	+
	33	+clean:
	34	+ rm -f $(SOBJS) $(OBJS)
	35	+
	36	+distclean: clean
	37	+ rm -f $(LIB) core *.bak .depend
	38	+
	39	+#########################################################################
	40	+
	41	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	42	+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	43	+
	44	+-include .depend
	45	+
	46	+#########################################################################
	1	+/*
	2	+ * (C) Copyright 2004
	3	+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#define SDRAM_DDR 0 /* is SDR */
	25	+
	26	+#if defined(CONFIG_MPC5200)
	27	+/* Settings for XLB = 132 MHz */
	28	+#define SDRAM_MODE 0x00CD0000
	29	+#define SDRAM_CONTROL 0x504F0000
	30	+#define SDRAM_CONFIG1 0xD2322800
	31	+#define SDRAM_CONFIG2 0x8AD70000
	32	+
	33	+#elif defined(CONFIG_MGT5100)
	34	+/* Settings for XLB = 66 MHz */
	35	+#define SDRAM_MODE 0x008D0000
	36	+#define SDRAM_CONTROL 0x504F0000
	37	+#define SDRAM_CONFIG1 0xC2222600
	38	+#define SDRAM_CONFIG2 0x88B70004
	39	+#define SDRAM_ADDRSEL 0x02000000
	40	+
	41	+#else
	42	+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
	43	+#endif
	1	+/*
	2	+ * (C) Copyright 2003-2004
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * (C) Copyright 2004
	6	+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+#include <common.h>
	28	+#include <mpc5xxx.h>
	29	+
	30	+#include "sdram.h"
	31	+
	32	+#ifndef CFG_RAMBOOT
	33	+static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
	34	+{
	35	+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	36	+
	37	+ /* unlock mode register */
	38	+ (vu_long )MPC5XXX_SDRAM_CTRL = sdram_conf->control \| 0x80000000 \| hi_addr_bit;
	39	+ __asm__ volatile ("sync");
	40	+
	41	+ /* precharge all banks */
	42	+ (vu_long )MPC5XXX_SDRAM_CTRL = sdram_conf->control \| 0x80000002 \| hi_addr_bit;
	43	+ __asm__ volatile ("sync");
	44	+
	45	+ if (sdram_conf->ddr) {
	46	+ /* set mode register: extended mode */
	47	+ (vu_long )MPC5XXX_SDRAM_MODE = sdram_conf->emode;
	48	+ __asm__ volatile ("sync");
	49	+
	50	+ /* set mode register: reset DLL */
	51	+ (vu_long )MPC5XXX_SDRAM_MODE = sdram_conf->mode \| 0x04000000;
	52	+ __asm__ volatile ("sync");
	53	+ }
	54	+
	55	+ /* precharge all banks */
	56	+ (vu_long )MPC5XXX_SDRAM_CTRL = sdram_conf->control \| 0x80000002 \| hi_addr_bit;
	57	+ __asm__ volatile ("sync");
	58	+
	59	+ /* auto refresh */
	60	+ (vu_long )MPC5XXX_SDRAM_CTRL = sdram_conf->control \| 0x80000004 \| hi_addr_bit;
	61	+ __asm__ volatile ("sync");
	62	+
	63	+ /* set mode register */
	64	+ (vu_long )MPC5XXX_SDRAM_MODE = sdram_conf->mode;
	65	+ __asm__ volatile ("sync");
	66	+
	67	+ /* normal operation */
	68	+ (vu_long )MPC5XXX_SDRAM_CTRL = sdram_conf->control \| hi_addr_bit;
	69	+ __asm__ volatile ("sync");
	70	+}
	71	+#endif
	72	+
	73	+/*
	74	+ * ATTENTION: Although partially referenced initdram does NOT make real use
	75	+ * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
	76	+ * is something else than 0x00000000.
	77	+ */
	78	+
	79	+#if defined(CONFIG_MPC5200)
	80	+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
	81	+{
	82	+ ulong dramsize = 0;
	83	+ ulong dramsize2 = 0;
	84	+#ifndef CFG_RAMBOOT
	85	+ ulong test1, test2;
	86	+
	87	+ /* setup SDRAM chip selects */
	88	+ (vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	89	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	90	+ __asm__ volatile ("sync");
	91	+
	92	+ /* setup config registers */
	93	+ (vu_long )MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
	94	+ (vu_long )MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
	95	+ __asm__ volatile ("sync");
	96	+
	97	+ if (sdram_conf->ddr) {
	98	+ /* set tap delay */
	99	+ (vu_long )MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
	100	+ __asm__ volatile ("sync");
	101	+ }
	102	+
	103	+ /* find RAM size using SDRAM CS0 only */
	104	+ mpc5xxx_sdram_start(sdram_conf, 0);
	105	+ test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
	106	+ mpc5xxx_sdram_start(sdram_conf, 1);
	107	+ test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
	108	+ if (test1 > test2) {
	109	+ mpc5xxx_sdram_start(sdram_conf, 0);
	110	+ dramsize = test1;
	111	+ } else {
	112	+ dramsize = test2;
	113	+ }
	114	+
	115	+ /* memory smaller than 1MB is impossible */
	116	+ if (dramsize < (1 << 20)) {
	117	+ dramsize = 0;
	118	+ }
	119	+
	120	+ /* set SDRAM CS0 size according to the amount of RAM found */
	121	+ if (dramsize > 0) {
	122	+ (vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	123	+ } else {
	124	+ (vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	125	+ }
	126	+
	127	+ /* let SDRAM CS1 start right after CS0 */
	128	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	129	+
	130	+ /* find RAM size using SDRAM CS1 only */
	131	+ mpc5xxx_sdram_start(sdram_conf, 0);
	132	+ test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
	133	+ mpc5xxx_sdram_start(sdram_conf, 1);
	134	+ test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
	135	+ if (test1 > test2) {
	136	+ mpc5xxx_sdram_start(sdram_conf, 0);
	137	+ dramsize2 = test1;
	138	+ } else {
	139	+ dramsize2 = test2;
	140	+ }
	141	+
	142	+ /* memory smaller than 1MB is impossible */
	143	+ if (dramsize2 < (1 << 20)) {
	144	+ dramsize2 = 0;
	145	+ }
	146	+
	147	+ /* set SDRAM CS1 size according to the amount of RAM found */
	148	+ if (dramsize2 > 0) {
	149	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	150	+ \| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	151	+ } else {
	152	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	153	+ }
	154	+
	155	+#else /* CFG_RAMBOOT */
	156	+
	157	+ /* retrieve size of memory connected to SDRAM CS0 */
	158	+ dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	159	+ if (dramsize >= 0x13) {
	160	+ dramsize = (1 << (dramsize - 0x13)) << 20;
	161	+ } else {
	162	+ dramsize = 0;
	163	+ }
	164	+
	165	+ /* retrieve size of memory connected to SDRAM CS1 */
	166	+ dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	167	+ if (dramsize2 >= 0x13) {
	168	+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	169	+ } else {
	170	+ dramsize2 = 0;
	171	+ }
	172	+
	173	+#endif /* CFG_RAMBOOT */
	174	+
	175	+ return dramsize + dramsize2;
	176	+}
	177	+
	178	+#elif defined(CONFIG_MGT5100)
	179	+
	180	+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
	181	+{
	182	+ ulong dramsize = 0;
	183	+#ifndef CFG_RAMBOOT
	184	+ ulong test1, test2;
	185	+
	186	+ /* setup and enable SDRAM chip selects */
	187	+ (vu_long )MPC5XXX_SDRAM_START = 0x00000000;
	188	+ (vu_long )MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	189	+ (vu_long )MPC5XXX_ADDECR \|= (1 << 22); /* Enable SDRAM */
	190	+ __asm__ volatile ("sync");
	191	+
	192	+ /* setup config registers */
	193	+ (vu_long )MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
	194	+ (vu_long )MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
	195	+
	196	+ /* address select register */
	197	+ (vu_long )MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
	198	+ __asm__ volatile ("sync");
	199	+
	200	+ /* find RAM size */
	201	+ mpc5xxx_sdram_start(sdram_conf, 0);
	202	+ test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
	203	+ mpc5xxx_sdram_start(sdram_conf, 1);
	204	+ test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
	205	+ if (test1 > test2) {
	206	+ mpc5xxx_sdram_start(sdram_conf, 0);
	207	+ dramsize = test1;
	208	+ } else {
	209	+ dramsize = test2;
	210	+ }
	211	+
	212	+ /* set SDRAM end address according to size */
	213	+ (vu_long )MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
	214	+
	215	+#else /* CFG_RAMBOOT */
	216	+
	217	+ /* Retrieve amount of SDRAM available */
	218	+ dramsize = (((vu_long )MPC5XXX_SDRAM_STOP + 1) << 15);
	219	+
	220	+#endif /* CFG_RAMBOOT */
	221	+
	222	+ return dramsize;
	223	+}
	224	+
	225	+#else
	226	+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
	227	+#endif
...	...	@@ -397,7 +397,13 @@
397	397	*/
398	398	if (fec->xcv_type == SEVENWIRE) {
399	399	/* 10MBit with 7-wire operation */
	400	+#if defined(CONFIG_TOTAL5200)
	401	+ /* 7-wire and USB2 on Ethernet */
	402	+ (vu_long )MPC5XXX_GPS_PORT_CONFIG \|= 0x00030000;
	403	+#else /* !CONFIG_TOTAL5200 */
	404	+ /* 7-wire only */
400	405	(vu_long )MPC5XXX_GPS_PORT_CONFIG \|= 0x00020000;
	406	+#endif /* CONFIG_TOTAL5200 */
401	407	} else {
402	408	/* 100MBit with MD operation */
403	409	(vu_long )MPC5XXX_GPS_PORT_CONFIG \|= 0x00050000;
...	...	@@ -870,6 +876,8 @@
870	876	# else
871	877	fec->xcv_type = MII10;
872	878	# endif
	879	+#elif defined(CONFIG_TOTAL5200)
	880	+ fec->xcv_type = SEVENWIRE;
873	881	#else
874	882	#error fec->xcv_type not initialized.
875	883	#endif
...	...	@@ -41,7 +41,13 @@
41	41	struct mpc5xxx_sdma psdma = (struct mpc5xxx_sdma ) MPC5XXX_SDMA;
42	42
43	43	reg = (vu_long ) MPC5XXX_GPS_PORT_CONFIG;
	44	+#if defined(CONFIG_TOTAL5200)
	45	+ /* ATA cs0/1 on i2c2 clk/io */
	46	+ reg = (reg & ~0x03000000ul) \| 0x02000000ul;
	47	+#else
	48	+ /* ATA cs0/1 on Local Plus cs4/5 */
44	49	reg = (reg & ~0x03000000ul) \| 0x01000000ul;
	50	+#endif /* CONFIG_TOTAL5200 */
45	51	(vu_long ) MPC5XXX_GPS_PORT_CONFIG = reg;
46	52
47	53	/* All sample codes do that... */
...	...	@@ -110,6 +110,9 @@
110	110	#if defined(CFG_RAMBOOT)
111	111	#error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
112	112	#endif /* CFG_RAMBOOT */
	113	+#if defined(CFG_LOWBOOT)
	114	+#error CFG_LOWBOOT is incompatible with MGT5100
	115	+#endif /* CFG_LOWBOOT */
113	116	lis r4, CFG_DEFAULT_MBAR@h
114	117	lis r3, START_REG(CFG_BOOTCS_START)@h
115	118	ori r3, r3, START_REG(CFG_BOOTCS_START)@l