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Commit 6cc2120646a3230bcf4b57cb3cb937f4a1cfe150

Authored by Masahiro Yamada
1 parent afed8c1b6a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: UniPhier: consolidate MEMCONF setting code 

This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.

The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 6 changed files with 116 additions and 141 deletions Side-by-side Diff

arch/arm/mach-uniphier/Makefile
Diff comments   View file @ 6cc2120
... ... @@ -7,6 +7,7 @@
7 7 obj-y += lowlevel_init.o
8 8 obj-y += init_page_table.o
9 9 obj-y += spl.o
  10 +obj-y += memconf.o
10 11 obj-y += ddrphy_training.o
11 12  
12 13 else
arch/arm/mach-uniphier/include/mach/sg-regs.h
Diff comments   View file @ 6cc2120
1 1 /*
2 2 * UniPhier SG (SoC Glue) block registers
3 3 *
4   - * Copyright (C) 2011-2014 Panasonic Corporation
  4 + * Copyright (C) 2011-2015 Panasonic Corporation
5 5 *
6 6 * SPDX-License-Identifier: GPL-2.0+
7 7 */
... ... @@ -108,7 +108,6 @@
108 108 #else
109 109  
110 110 #include <linux/types.h>
111   -#include <linux/sizes.h>
112 111 #include <asm/io.h>
113 112  
114 113 static inline void sg_set_pinsel(int n, int value)
... ... @@ -117,122 +116,6 @@
117 116 | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
118 117 }
119 118  
120   -static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
121   -{
122   - int size_mb = size / num;
123   - u32 ret;
124   -
125   - switch (size_mb) {
126   - case SZ_64M:
127   - ret = SG_MEMCONF_CH0_SZ_64M;
128   - break;
129   - case SZ_128M:
130   - ret = SG_MEMCONF_CH0_SZ_128M;
131   - break;
132   - case SZ_256M:
133   - ret = SG_MEMCONF_CH0_SZ_256M;
134   - break;
135   - case SZ_512M:
136   - ret = SG_MEMCONF_CH0_SZ_512M;
137   - break;
138   - case SZ_1G:
139   - ret = SG_MEMCONF_CH0_SZ_1G;
140   - break;
141   - default:
142   - BUG();
143   - break;
144   - }
145   -
146   - switch (num) {
147   - case 1:
148   - ret |= SG_MEMCONF_CH0_NUM_1;
149   - break;
150   - case 2:
151   - ret |= SG_MEMCONF_CH0_NUM_2;
152   - break;
153   - default:
154   - BUG();
155   - break;
156   - }
157   - return ret;
158   -}
159   -
160   -static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
161   -{
162   - int size_mb = size / num;
163   - u32 ret;
164   -
165   - switch (size_mb) {
166   - case SZ_64M:
167   - ret = SG_MEMCONF_CH1_SZ_64M;
168   - break;
169   - case SZ_128M:
170   - ret = SG_MEMCONF_CH1_SZ_128M;
171   - break;
172   - case SZ_256M:
173   - ret = SG_MEMCONF_CH1_SZ_256M;
174   - break;
175   - case SZ_512M:
176   - ret = SG_MEMCONF_CH1_SZ_512M;
177   - break;
178   - case SZ_1G:
179   - ret = SG_MEMCONF_CH1_SZ_1G;
180   - break;
181   - default:
182   - BUG();
183   - break;
184   - }
185   -
186   - switch (num) {
187   - case 1:
188   - ret |= SG_MEMCONF_CH1_NUM_1;
189   - break;
190   - case 2:
191   - ret |= SG_MEMCONF_CH1_NUM_2;
192   - break;
193   - default:
194   - BUG();
195   - break;
196   - }
197   - return ret;
198   -}
199   -
200   -static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
201   -{
202   - int size_mb = size / num;
203   - u32 ret;
204   -
205   - switch (size_mb) {
206   - case SZ_64M:
207   - ret = SG_MEMCONF_CH2_SZ_64M;
208   - break;
209   - case SZ_128M:
210   - ret = SG_MEMCONF_CH2_SZ_128M;
211   - break;
212   - case SZ_256M:
213   - ret = SG_MEMCONF_CH2_SZ_256M;
214   - break;
215   - case SZ_512M:
216   - ret = SG_MEMCONF_CH2_SZ_512M;
217   - break;
218   - default:
219   - BUG();
220   - break;
221   - }
222   -
223   - switch (num) {
224   - case 1:
225   - ret |= SG_MEMCONF_CH2_NUM_1;
226   - break;
227   - case 2:
228   - ret |= SG_MEMCONF_CH2_NUM_2;
229   - break;
230   - default:
231   - BUG();
232   - break;
233   - }
234   - return ret;
235   -}
236 119 #endif /* __ASSEMBLY__ */
237 120  
238 121 #endif /* ARCH_SG_REGS_H */
arch/arm/mach-uniphier/memconf.c
Diff comments   View file @ 6cc2120
  1 +/*
  2 + * Copyright (C) 2011-2015 Panasonic Corporation
  3 + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <linux/sizes.h>
  10 +#include <asm/io.h>
  11 +#include <mach/sg-regs.h>
  12 +
  13 +static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
  14 +{
  15 + int size_mb = size / num;
  16 + u32 ret;
  17 +
  18 + switch (size_mb) {
  19 + case SZ_64M:
  20 + ret = SG_MEMCONF_CH0_SZ_64M;
  21 + break;
  22 + case SZ_128M:
  23 + ret = SG_MEMCONF_CH0_SZ_128M;
  24 + break;
  25 + case SZ_256M:
  26 + ret = SG_MEMCONF_CH0_SZ_256M;
  27 + break;
  28 + case SZ_512M:
  29 + ret = SG_MEMCONF_CH0_SZ_512M;
  30 + break;
  31 + case SZ_1G:
  32 + ret = SG_MEMCONF_CH0_SZ_1G;
  33 + break;
  34 + default:
  35 + BUG();
  36 + break;
  37 + }
  38 +
  39 + switch (num) {
  40 + case 1:
  41 + ret |= SG_MEMCONF_CH0_NUM_1;
  42 + break;
  43 + case 2:
  44 + ret |= SG_MEMCONF_CH0_NUM_2;
  45 + break;
  46 + default:
  47 + BUG();
  48 + break;
  49 + }
  50 + return ret;
  51 +}
  52 +
  53 +static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
  54 +{
  55 + int size_mb = size / num;
  56 + u32 ret;
  57 +
  58 + switch (size_mb) {
  59 + case SZ_64M:
  60 + ret = SG_MEMCONF_CH1_SZ_64M;
  61 + break;
  62 + case SZ_128M:
  63 + ret = SG_MEMCONF_CH1_SZ_128M;
  64 + break;
  65 + case SZ_256M:
  66 + ret = SG_MEMCONF_CH1_SZ_256M;
  67 + break;
  68 + case SZ_512M:
  69 + ret = SG_MEMCONF_CH1_SZ_512M;
  70 + break;
  71 + case SZ_1G:
  72 + ret = SG_MEMCONF_CH1_SZ_1G;
  73 + break;
  74 + default:
  75 + BUG();
  76 + break;
  77 + }
  78 +
  79 + switch (num) {
  80 + case 1:
  81 + ret |= SG_MEMCONF_CH1_NUM_1;
  82 + break;
  83 + case 2:
  84 + ret |= SG_MEMCONF_CH1_NUM_2;
  85 + break;
  86 + default:
  87 + BUG();
  88 + break;
  89 + }
  90 + return ret;
  91 +}
  92 +
  93 +void memconf_init(void)
  94 +{
  95 + u32 tmp;
  96 +
  97 + /* Set DDR size */
  98 + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
  99 + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
  100 +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
  101 + tmp |= SG_MEMCONF_SPARSEMEM;
  102 +#endif
  103 + writel(tmp, SG_MEMCONF);
  104 +}
arch/arm/mach-uniphier/ph1-ld4/sg_init.c
Diff comments   View file @ 6cc2120
1 1 /*
2   - * Copyright (C) 2011-2014 Panasonic Corporation
  2 + * Copyright (C) 2011-2015 Panasonic Corporation
3 3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
6 6 */
7 7  
8   -#include <common.h>
9 8 #include <asm/io.h>
10 9 #include <mach/sg-regs.h>
11 10  
12 11 void sg_init(void)
13 12 {
14 13 u32 tmp;
15   -
16   - /* Set DDR size */
17   - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
18   - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
19   -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
20   - tmp |= SG_MEMCONF_SPARSEMEM;
21   -#endif
22   - writel(tmp, SG_MEMCONF);
23 14  
24 15 /* Input ports must be enabled before deasserting reset of cores */
25 16 tmp = readl(SG_IECTRL);
arch/arm/mach-uniphier/ph1-pro4/sg_init.c
Diff comments   View file @ 6cc2120
1 1 /*
2   - * Copyright (C) 2011-2014 Panasonic Corporation
  2 + * Copyright (C) 2011-2015 Panasonic Corporation
3 3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
6 6 */
7 7  
8   -#include <common.h>
9 8 #include <asm/io.h>
10 9 #include <mach/sg-regs.h>
11 10  
12 11 void sg_init(void)
13 12 {
14 13 u32 tmp;
15   -
16   - /* Set DDR size */
17   - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
18   - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
19   -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
20   - tmp |= SG_MEMCONF_SPARSEMEM;
21   -#endif
22   - writel(tmp, SG_MEMCONF);
23 14  
24 15 /* Input ports must be enabled before deasserting reset of cores */
25 16 tmp = readl(SG_IECTRL);
arch/arm/mach-uniphier/spl.c
Diff comments   View file @ 6cc2120
... ... @@ -18,6 +18,7 @@
18 18 void sg_init(void);
19 19 void pll_init(void);
20 20 void pin_init(void);
  21 +void memconf_init(void);
21 22 void early_clkrst_init(void);
22 23 int umc_init(void);
23 24 void enable_dpll_ssc(void);
24 25  
... ... @@ -38,10 +39,14 @@
38 39  
39 40 led_write(L, 0, , );
40 41  
41   - early_clkrst_init();
  42 + memconf_init();
42 43  
43 44 led_write(L, 1, , );
44 45  
  46 + early_clkrst_init();
  47 +
  48 + led_write(L, 2, , );
  49 +
45 50 {
46 51 int res;
47 52  
48 53  
... ... @@ -51,10 +56,10 @@
51 56 ;
52 57 }
53 58 }
54   - led_write(L, 2, , );
  59 + led_write(L, 3, , );
55 60  
56 61 enable_dpll_ssc();
57 62  
58   - led_write(L, 3, , );
  63 + led_write(L, 4, , );
59 64 }