Eric Lee / smarc-uboot

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Commit 6d204089cf767cd6fb23ea2655f621f689351413

Authored by Ye Li
1 parent 00b6fcdbf9
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-24062-5 DTS: imx8qm: Remove unused nodes from DTS 

Current iMX8QM DTSi is a version with full nodes, but this introduces
overhead in u-boot initf_dm phase because the initf_dm will search all
subnodes of the root. This is does not like SPL which has slimmed the
DTB.

During initf_dm the dcache is not enabled, so the overhead is large
if we have many unused nodes in the DTS. This patch removed iMX8QM
nodes those we won't ever used in SPL/u-boot, like VPU/GPU, Audio,
camera, M4 i2c, flexcan, pwm, etc.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 6c69c8f2918f254ff5a3e68a70709d87a35cbc59)

Showing 2 changed files with 15 additions and 2139 deletions Side-by-side Diff

arch/arm/dts/fsl-imx8qm-device.dtsi
Diff comments   View file @ 6d20408
Changes suppressed. Click to show
... ... @@ -189,51 +189,6 @@
189 189 #address-cells = <1>;
190 190 #size-cells = <0>;
191 191  
192   - pd_lsio_pwm0: PD_LSIO_PWM_0 {
193   - reg = <SC_R_PWM_0>;
194   - #power-domain-cells = <0>;
195   - power-domains = <&pd_lsio>;
196   - };
197   - pd_lsio_pwm1: PD_LSIO_PWM_1 {
198   - reg = <SC_R_PWM_1>;
199   - #power-domain-cells = <0>;
200   - power-domains = <&pd_lsio>;
201   - };
202   - pd_lsio_pwm2: PD_LSIO_PWM_2 {
203   - reg = <SC_R_PWM_2>;
204   - #power-domain-cells = <0>;
205   - power-domains = <&pd_lsio>;
206   - };
207   - pd_lsio_pwm3: PD_LSIO_PWM_3 {
208   - reg = <SC_R_PWM_3>;
209   - #power-domain-cells = <0>;
210   - power-domains = <&pd_lsio>;
211   - };
212   - pd_lsio_pwm4: PD_LSIO_PWM_4 {
213   - reg = <SC_R_PWM_4>;
214   - #power-domain-cells = <0>;
215   - power-domains = <&pd_lsio>;
216   - };
217   - pd_lsio_pwm5: PD_LSIO_PWM_5 {
218   - reg = <SC_R_PWM_5>;
219   - #power-domain-cells = <0>;
220   - power-domains = <&pd_lsio>;
221   - };
222   - pd_lsio_pwm6: PD_LSIO_PWM_6 {
223   - reg = <SC_R_PWM_6>;
224   - #power-domain-cells = <0>;
225   - power-domains = <&pd_lsio>;
226   - };
227   - pd_lsio_pwm7: PD_LSIO_PWM_7 {
228   - reg = <SC_R_PWM_7>;
229   - #power-domain-cells = <0>;
230   - power-domains = <&pd_lsio>;
231   - };
232   - pd_lsio_kpp: PD_LSIO_KPP {
233   - reg = <SC_R_KPP>;
234   - #power-domain-cells = <0>;
235   - power-domains = <&pd_lsio>;
236   - };
237 192 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
238 193 reg = <SC_R_GPIO_0>;
239 194 #power-domain-cells = <0>;
... ... @@ -274,31 +229,6 @@
274 229 #power-domain-cells = <0>;
275 230 power-domains = <&pd_lsio>;
276 231 };
277   - pd_lsio_gpt0: PD_LSIO_GPT_0 {
278   - reg = <SC_R_GPT_0>;
279   - #power-domain-cells = <0>;
280   - power-domains = <&pd_lsio>;
281   - };
282   - pd_lsio_gpt1: PD_LSIO_GPT_1 {
283   - reg = <SC_R_GPT_1>;
284   - #power-domain-cells = <0>;
285   - power-domains = <&pd_lsio>;
286   - };
287   - pd_lsio_gpt2: PD_LSIO_GPT_2 {
288   - reg = <SC_R_GPT_2>;
289   - #power-domain-cells = <0>;
290   - power-domains = <&pd_lsio>;
291   - };
292   - pd_lsio_gpt3: PD_LSIO_GPT_3 {
293   - reg = <SC_R_GPT_3>;
294   - #power-domain-cells = <0>;
295   - power-domains = <&pd_lsio>;
296   - };
297   - pd_lsio_gpt4: PD_LSIO_GPT_4 {
298   - reg = <SC_R_GPT_4>;
299   - #power-domain-cells = <0>;
300   - power-domains = <&pd_lsio>;
301   - };
302 232 pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
303 233 reg = <SC_R_FSPI_0>;
304 234 #power-domain-cells = <0>;
... ... @@ -492,457 +422,6 @@
492 422 };
493 423 };
494 424  
495   - pd_audio: PD_AUDIO {
496   - compatible = "nxp,imx8-pd";
497   - reg = <SC_R_NONE>;
498   - #power-domain-cells = <0>;
499   - #address-cells = <1>;
500   - #size-cells = <0>;
501   -
502   - pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
503   - reg = <SC_R_AUDIO_PLL_0>;
504   - power-domains =<&pd_audio>;
505   - #power-domain-cells = <0>;
506   - #address-cells = <1>;
507   - #size-cells = <0>;
508   -
509   - pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
510   - reg = <SC_R_AUDIO_PLL_1>;
511   - power-domains =<&pd_audio_pll0>;
512   - #power-domain-cells = <0>;
513   - #address-cells = <1>;
514   - #size-cells = <0>;
515   -
516   - pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
517   - reg = <SC_R_AUDIO_CLK_0>;
518   - power-domains =<&pd_audio_pll1>;
519   - #power-domain-cells = <0>;
520   - #address-cells = <1>;
521   - #size-cells = <0>;
522   -
523   - pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
524   - reg = <SC_R_AUDIO_CLK_1>;
525   - power-domains =<&pd_audio_clk0>;
526   - #power-domain-cells = <0>;
527   - #address-cells = <1>;
528   - #size-cells = <0>;
529   -
530   - pd_dma2_chan0: PD_ASRC_0_RXA {
531   - reg = <SC_R_DMA_2_CH0>;
532   - power-domains =<&pd_audio_clk1>;
533   - #power-domain-cells = <0>;
534   - #address-cells = <1>;
535   - #size-cells = <0>;
536   -
537   - pd_dma2_chan1: PD_ASRC_0_RXB {
538   - reg = <SC_R_DMA_2_CH1>;
539   - power-domains =<&pd_dma2_chan0>;
540   - #power-domain-cells = <0>;
541   - #address-cells = <1>;
542   - #size-cells = <0>;
543   -
544   - pd_dma2_chan2: PD_ASRC_0_RXC {
545   - reg = <SC_R_DMA_2_CH2>;
546   - power-domains =<&pd_dma2_chan1>;
547   - #power-domain-cells = <0>;
548   - #address-cells = <1>;
549   - #size-cells = <0>;
550   -
551   - pd_dma2_chan3: PD_ASRC_0_TXA {
552   - reg = <SC_R_DMA_2_CH3>;
553   - power-domains =<&pd_dma2_chan2>;
554   - #power-domain-cells = <0>;
555   - #address-cells = <1>;
556   - #size-cells = <0>;
557   -
558   - pd_dma2_chan4: PD_ASRC_0_TXB {
559   - reg = <SC_R_DMA_2_CH4>;
560   - power-domains =<&pd_dma2_chan3>;
561   - #power-domain-cells = <0>;
562   - #address-cells = <1>;
563   - #size-cells = <0>;
564   -
565   - pd_dma2_chan5: PD_ASRC_0_TXC {
566   - reg = <SC_R_DMA_2_CH5>;
567   - power-domains =<&pd_dma2_chan4>;
568   - #power-domain-cells = <0>;
569   - #address-cells = <1>;
570   - #size-cells = <0>;
571   -
572   - pd_asrc0:PD_AUD_ASRC_0 {
573   - reg = <SC_R_ASRC_0>;
574   - #power-domain-cells = <0>;
575   - power-domains =<&pd_dma2_chan5>;
576   - };
577   - };
578   - };
579   - };
580   - };
581   - };
582   - };
583   -
584   - pd_dma3_chan0: PD_ASRC_1_RXA {
585   - reg = <SC_R_DMA_3_CH0>;
586   - power-domains =<&pd_audio_clk1>;
587   - #power-domain-cells = <0>;
588   - #address-cells = <1>;
589   - #size-cells = <0>;
590   -
591   - pd_dma3_chan1: PD_ASRC_1_RXB {
592   - reg = <SC_R_DMA_3_CH1>;
593   - power-domains =<&pd_dma3_chan0>;
594   - #power-domain-cells = <0>;
595   - #address-cells = <1>;
596   - #size-cells = <0>;
597   -
598   - pd_dma3_chan2: PD_ASRC_1_RXC {
599   - reg = <SC_R_DMA_3_CH2>;
600   - power-domains =<&pd_dma3_chan1>;
601   - #power-domain-cells = <0>;
602   - #address-cells = <1>;
603   - #size-cells = <0>;
604   -
605   - pd_dma3_chan3: PD_ASRC_1_TXA {
606   - reg = <SC_R_DMA_3_CH3>;
607   - power-domains =<&pd_dma3_chan2>;
608   - #power-domain-cells = <0>;
609   - #address-cells = <1>;
610   - #size-cells = <0>;
611   -
612   - pd_dma3_chan4: PD_ASRC_1_TXB {
613   - reg = <SC_R_DMA_3_CH4>;
614   - power-domains =<&pd_dma3_chan3>;
615   - #power-domain-cells = <0>;
616   - #address-cells = <1>;
617   - #size-cells = <0>;
618   -
619   - pd_dma3_chan5: PD_ASRC_1_TXC {
620   - reg = <SC_R_DMA_3_CH5>;
621   - power-domains =<&pd_dma3_chan4>;
622   - #power-domain-cells = <0>;
623   - #address-cells = <1>;
624   - #size-cells = <0>;
625   -
626   - pd_asrc1: PD_AUD_ASRC_1 {
627   - reg = <SC_R_ASRC_1>;
628   - #power-domain-cells = <0>;
629   - power-domains =<&pd_dma3_chan5>;
630   -
631   - };
632   - };
633   - };
634   - };
635   - };
636   - };
637   - };
638   - pd_dma2_chan6: PD_ESAI_0_RX {
639   - reg = <SC_R_DMA_2_CH6>;
640   - power-domains =<&pd_audio_clk1>;
641   - #power-domain-cells = <0>;
642   - #address-cells = <1>;
643   - #size-cells = <0>;
644   -
645   - pd_dma2_chan7: PD_ESAI_0_TX {
646   - reg = <SC_R_DMA_2_CH7>;
647   - power-domains =<&pd_dma2_chan6>;
648   - #power-domain-cells = <0>;
649   - #address-cells = <1>;
650   - #size-cells = <0>;
651   -
652   - pd_esai0: PD_AUD_ESAI_0 {
653   - reg = <SC_R_ESAI_0>;
654   - #power-domain-cells = <0>;
655   - power-domains =<&pd_dma2_chan7>;
656   - };
657   - };
658   - };
659   -
660   - pd_dma3_chan6: PD_ESAI_1_RX {
661   - reg = <SC_R_DMA_3_CH6>;
662   - power-domains =<&pd_audio_clk1>;
663   - #power-domain-cells = <0>;
664   - #address-cells = <1>;
665   - #size-cells = <0>;
666   -
667   - pd_dma3_chan7: PD_ESAI_1_TX {
668   - reg = <SC_R_DMA_3_CH7>;
669   - power-domains =<&pd_dma3_chan6>;
670   - #power-domain-cells = <0>;
671   - #address-cells = <1>;
672   - #size-cells = <0>;
673   -
674   - pd_esai1: PD_AUD_ESAI_1 {
675   - reg = <SC_R_ESAI_1>;
676   - #power-domain-cells = <0>;
677   - power-domains =<&pd_dma3_chan7>;
678   - };
679   - };
680   - };
681   - pd_dma2_chan8: PD_SPDIF_0_RX {
682   - reg = <SC_R_DMA_2_CH8>;
683   - power-domains =<&pd_audio_clk1>;
684   - #power-domain-cells = <0>;
685   - #address-cells = <1>;
686   - #size-cells = <0>;
687   -
688   - pd_dma2_chan9: PD_SPDIF_0_TX {
689   - reg = <SC_R_DMA_2_CH9>;
690   - power-domains =<&pd_dma2_chan8>;
691   - #power-domain-cells = <0>;
692   - #address-cells = <1>;
693   - #size-cells = <0>;
694   -
695   - pd_spdif0: PD_AUD_SPDIF_0 {
696   - reg = <SC_R_SPDIF_0>;
697   - #power-domain-cells = <0>;
698   - power-domains =<&pd_dma2_chan9>;
699   -
700   - };
701   - };
702   - };
703   - pd_dma2_chan10: PD_SPDIF_1_RX {
704   - reg = <SC_R_DMA_2_CH10>;
705   - power-domains =<&pd_audio_clk1>;
706   - #power-domain-cells = <0>;
707   - #address-cells = <1>;
708   - #size-cells = <0>;
709   -
710   - pd_dma2_chan11: PD_SPDIF_1_TX {
711   - reg = <SC_R_DMA_2_CH11>;
712   - power-domains =<&pd_dma2_chan10>;
713   - #power-domain-cells = <0>;
714   - #address-cells = <1>;
715   - #size-cells = <0>;
716   -
717   - pd_spdif1: PD_AUD_SPDIF_1 {
718   - reg = <SC_R_SPDIF_1>;
719   - #power-domain-cells = <0>;
720   - power-domains =<&pd_dma2_chan11>;
721   -
722   - };
723   - };
724   - };
725   - pd_dma2_chan12: PD_SAI_0_RX {
726   - reg = <SC_R_DMA_2_CH12>;
727   - power-domains =<&pd_audio_clk1>;
728   - #power-domain-cells = <0>;
729   - #address-cells = <1>;
730   - #size-cells = <0>;
731   -
732   - pd_dma2_chan13: PD_SAI_0_TX {
733   - reg = <SC_R_DMA_2_CH13>;
734   - power-domains =<&pd_dma2_chan12>;
735   - #power-domain-cells = <0>;
736   - #address-cells = <1>;
737   - #size-cells = <0>;
738   -
739   - pd_sai0:PD_AUD_SAI_0 {
740   - reg = <SC_R_SAI_0>;
741   - #power-domain-cells = <0>;
742   - power-domains =<&pd_dma2_chan13>;
743   - };
744   - };
745   -
746   - };
747   - pd_dma2_chan14: PD_SAI_1_RX {
748   - reg = <SC_R_DMA_2_CH14>;
749   - power-domains =<&pd_audio_clk1>;
750   - #power-domain-cells = <0>;
751   - #address-cells = <1>;
752   - #size-cells = <0>;
753   -
754   - pd_dma2_chan15: PD_SAI_1_TX {
755   - reg = <SC_R_DMA_2_CH15>;
756   - power-domains =<&pd_dma2_chan14>;
757   - #power-domain-cells = <0>;
758   - #address-cells = <1>;
759   - #size-cells = <0>;
760   -
761   - pd_sai1: PD_AUD_SAI_1 {
762   - reg = <SC_R_SAI_1>;
763   - #power-domain-cells = <0>;
764   - power-domains =<&pd_dma2_chan15>;
765   - };
766   - };
767   - };
768   - pd_dma2_chan16: PD_SAI_2_RX {
769   - reg = <SC_R_DMA_2_CH16>;
770   - power-domains =<&pd_audio_clk1>;
771   - #power-domain-cells = <0>;
772   - #address-cells = <1>;
773   - #size-cells = <0>;
774   - pd_sai2: PD_AUD_SAI_2 {
775   - reg = <SC_R_SAI_2>;
776   - #power-domain-cells = <0>;
777   - power-domains =<&pd_dma2_chan16>;
778   - };
779   - };
780   - pd_dma2_chan17: PD_SAI_3_RX {
781   - reg = <SC_R_DMA_2_CH17>;
782   - power-domains =<&pd_audio_clk1>;
783   - #power-domain-cells = <0>;
784   - #address-cells = <1>;
785   - #size-cells = <0>;
786   -
787   - pd_sai3: PD_AUD_SAI_3 {
788   - reg = <SC_R_SAI_3>;
789   - #power-domain-cells = <0>;
790   - power-domains =<&pd_dma2_chan17>;
791   - };
792   - };
793   - pd_dma2_chan18: PD_SAI_4_RX {
794   - reg = <SC_R_DMA_2_CH18>;
795   - power-domains =<&pd_audio_clk1>;
796   - #power-domain-cells = <0>;
797   - #address-cells = <1>;
798   - #size-cells = <0>;
799   -
800   - pd_sai4: PD_AUD_SAI_4 {
801   - reg = <SC_R_SAI_4>;
802   - #power-domain-cells = <0>;
803   - power-domains =<&pd_dma2_chan18>;
804   - };
805   - };
806   - pd_dma2_chan19: PD_SAI_5_RX {
807   - reg = <SC_R_DMA_2_CH19>;
808   - power-domains =<&pd_audio_clk1>;
809   - #power-domain-cells = <0>;
810   - #address-cells = <1>;
811   - #size-cells = <0>;
812   -
813   - pd_sai5: PD_AUD_SAI_5 {
814   - reg = <SC_R_SAI_5>;
815   - #power-domain-cells = <0>;
816   - power-domains =<&pd_dma2_chan19>;
817   - };
818   - };
819   - pd_dma3_chan8: PD_SAI_6_RX {
820   - reg = <SC_R_DMA_3_CH8>;
821   - power-domains =<&pd_audio_clk1>;
822   - #power-domain-cells = <0>;
823   - #address-cells = <1>;
824   - #size-cells = <0>;
825   -
826   - pd_dma3_chan9: PD_SAI_6_TX {
827   - reg = <SC_R_DMA_3_CH9>;
828   - power-domains =<&pd_dma3_chan8>;
829   - #power-domain-cells = <0>;
830   - #address-cells = <1>;
831   - #size-cells = <0>;
832   -
833   - pd_sai6: PD_AUD_SAI_6 {
834   - reg = <SC_R_SAI_6>;
835   - #power-domain-cells = <0>;
836   - power-domains =<&pd_dma3_chan9>;
837   -
838   - };
839   - };
840   - };
841   - pd_dma3_chan10: PD_SAI_7_TX {
842   - reg = <SC_R_DMA_3_CH10>;
843   - power-domains =<&pd_audio_clk1>;
844   - #power-domain-cells = <0>;
845   - #address-cells = <1>;
846   - #size-cells = <0>;
847   - pd_sai7: PD_AUD_SAI_7 {
848   - reg = <SC_R_SAI_7>;
849   - #power-domain-cells = <0>;
850   - power-domains =<&pd_dma3_chan10>;
851   - };
852   - };
853   - pd_gpt5: PD_AUD_GPT_5 {
854   - reg = <SC_R_GPT_5>;
855   - #power-domain-cells = <0>;
856   - power-domains =<&pd_audio_clk1>;
857   - };
858   - pd_gpt6: PD_AUD_GPT_6 {
859   - reg = <SC_R_GPT_6>;
860   - #power-domain-cells = <0>;
861   - power-domains =<&pd_audio_clk1>;
862   - };
863   - pd_gpt7: PD_AUD_GPT_7 {
864   - reg = <SC_R_GPT_7>;
865   - #power-domain-cells = <0>;
866   - power-domains =<&pd_audio_clk1>;
867   - };
868   - pd_gpt8: PD_AUD_GPT_8 {
869   - reg = <SC_R_GPT_8>;
870   - #power-domain-cells = <0>;
871   - power-domains =<&pd_audio_clk1>;
872   - };
873   - pd_gpt9: PD_AUD_GPT_9 {
874   - reg = <SC_R_GPT_9>;
875   - #power-domain-cells = <0>;
876   - power-domains =<&pd_audio_clk1>;
877   - };
878   - pd_gpt10: PD_AUD_GPT_10 {
879   - reg = <SC_R_GPT_10>;
880   - #power-domain-cells = <0>;
881   - power-domains =<&pd_audio_clk1>;
882   - };
883   - pd_amix: PD_AUD_AMIX {
884   - reg = <SC_R_AMIX>;
885   - #power-domain-cells = <0>;
886   - power-domains =<&pd_audio_clk1>;
887   - };
888   - pd_mqs0: PD_AUD_MQS_0 {
889   - reg = <SC_R_MQS_0>;
890   - #power-domain-cells = <0>;
891   - power-domains =<&pd_audio_clk1>;
892   - };
893   - pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
894   - reg = <SC_R_MCLK_OUT_0>;
895   - #power-domain-cells = <0>;
896   - power-domains =<&pd_audio_clk1>;
897   - };
898   - pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
899   - reg = <SC_R_MCLK_OUT_1>;
900   - #power-domain-cells = <0>;
901   - power-domains =<&pd_audio_clk1>;
902   - };
903   - };
904   - };
905   - };
906   - };
907   -
908   - pd_dsp_irqsteer: PD_DSP_MU_A {
909   - reg = <SC_R_IRQSTR_DSP>;
910   - #power-domain-cells = <0>;
911   - power-domains =<&pd_audio>;
912   - #address-cells = <1>;
913   - #size-cells = <0>;
914   -
915   - pd_dsp_mu_A: PD_DSP_MU_A {
916   - reg = <SC_R_MU_13A>;
917   - #power-domain-cells = <0>;
918   - power-domains =<&pd_dsp_irqsteer>;
919   - #address-cells = <1>;
920   - #size-cells = <0>;
921   -
922   - pd_dsp_mu_B: PD_DSP_MU_B {
923   - reg = <SC_R_MU_13B>;
924   - #power-domain-cells = <0>;
925   - power-domains =<&pd_dsp_mu_A>;
926   - #address-cells = <1>;
927   - #size-cells = <0>;
928   -
929   - pd_dsp_ram: PD_AUD_OCRAM {
930   - reg = <SC_R_DSP_RAM>;
931   - #power-domain-cells = <0>;
932   - power-domains =<&pd_dsp_mu_B>;
933   - #address-cells = <1>;
934   - #size-cells = <0>;
935   - pd_dsp: PD_AUD_DSP {
936   - reg = <SC_R_DSP>;
937   - #power-domain-cells = <0>;
938   - power-domains =<&pd_dsp_ram>;
939   - };
940   - };
941   - };
942   - };
943   - };
944   - };
945   -
946 425 pd_dma: PD_DMA {
947 426 compatible = "nxp,imx8-pd";
948 427 reg = <SC_R_NONE>;
... ... @@ -950,44 +429,6 @@
950 429 #address-cells = <1>;
951 430 #size-cells = <0>;
952 431  
953   - pd_dma_flexcan0: PD_DMA_CAN_0 {
954   - reg = <SC_R_CAN_0>;
955   - #power-domain-cells = <0>;
956   - power-domains = <&pd_dma>;
957   - wakeup-irq = <235>;
958   - };
959   - pd_dma_flexcan1: PD_DMA_CAN_1 {
960   - reg = <SC_R_CAN_1>;
961   - #power-domain-cells = <0>;
962   - power-domains = <&pd_dma>;
963   - wakeup-irq = <236>;
964   - };
965   - pd_dma_flexcan2: PD_DMA_CAN_2 {
966   - reg = <SC_R_CAN_2>;
967   - #power-domain-cells = <0>;
968   - power-domains = <&pd_dma>;
969   - wakeup-irq = <237>;
970   - };
971   - pd_dma_ftm0: PD_DMA_FTM_0 {
972   - reg = <SC_R_FTM_0>;
973   - #power-domain-cells = <0>;
974   - power-domains = <&pd_dma>;
975   - };
976   - pd_dma_ftm1: PD_DMA_FTM_1 {
977   - reg = <SC_R_FTM_1>;
978   - #power-domain-cells = <0>;
979   - power-domains = <&pd_dma>;
980   - };
981   - pd_dma_adc0: PD_DMA_ADC_0 {
982   - reg = <SC_R_ADC_0>;
983   - #power-domain-cells = <0>;
984   - power-domains = <&pd_dma>;
985   - };
986   - pd_dma_adc1: PD_DMA_ADC_1 {
987   - reg = <SC_R_ADC_1>;
988   - #power-domain-cells = <0>;
989   - power-domains = <&pd_dma>;
990   - };
991 432 pd_dma_lpi2c0: PD_DMA_I2C_0 {
992 433 reg = <SC_R_I2C_0>;
993 434 #power-domain-cells = <0>;
994 435  
995 436  
... ... @@ -1190,78 +631,8 @@
1190 631 power-domains = <&pd_dma>;
1191 632 };
1192 633 };
1193   - pd_gpu: PD_GPU {
1194   - compatible = "nxp,imx8-pd";
1195   - reg = <SC_R_NONE>;
1196   - #power-domain-cells = <0>;
1197   - #address-cells = <1>;
1198   - #size-cells = <0>;
1199 634  
1200   - pd_gpu0: PD_GPU0 {
1201   - reg = <SC_R_GPU_0_PID0>;
1202   - #power-domain-cells = <0>;
1203   - power-domains =<&pd_gpu>;
1204   - };
1205   - pd_gpu1: PD_GPU1 {
1206   - reg = <SC_R_GPU_1_PID0>;
1207   - #power-domain-cells = <0>;
1208   - power-domains =<&pd_gpu>;
1209   - };
1210   - };
1211 635  
1212   - pd_vpu: vpu-power-domain {
1213   - compatible = "nxp,imx8-pd";
1214   - reg = <SC_R_VPU>;
1215   - #power-domain-cells = <0>;
1216   - #address-cells = <1>;
1217   - #size-cells = <0>;
1218   -
1219   - pd_vpu_mu1_enc: VPU_ENC_MU1 {
1220   - reg = <SC_R_VPU_MU_2>;
1221   - #power-domain-cells = <0>;
1222   - power-domains =<&pd_vpu>;
1223   - #address-cells = <1>;
1224   - #size-cells = <0>;
1225   -
1226   - pd_vpu_enc1: VPU_ENC1 {
1227   - reg = <SC_R_VPU_ENC_1>;
1228   - #power-domain-cells = <0>;
1229   - power-domains =<&pd_vpu_mu1_enc>;
1230   - #address-cells = <1>;
1231   - #size-cells = <0>;
1232   -
1233   - pd_vpu_mu_enc: VPU_ENC_MU {
1234   - reg = <SC_R_VPU_MU_1>;
1235   - #power-domain-cells = <0>;
1236   - power-domains =<&pd_vpu_enc1>;
1237   - #address-cells = <1>;
1238   - #size-cells = <0>;
1239   -
1240   - pd_vpu_enc: VPU_ENC {
1241   - reg = <SC_R_VPU_ENC_0>;
1242   - #power-domain-cells = <0>;
1243   - power-domains =<&pd_vpu_mu_enc>;
1244   - };
1245   - };
1246   - };
1247   - };
1248   -
1249   - pd_vpu_mu_dec: VPU_DEC_MU {
1250   - reg = <SC_R_VPU_MU_0>;
1251   - #power-domain-cells = <0>;
1252   - power-domains =<&pd_vpu>;
1253   - #address-cells = <1>;
1254   - #size-cells = <0>;
1255   -
1256   - pd_vpu_dec: VPU_DEC {
1257   - reg = <SC_R_VPU_DEC_0>;
1258   - #power-domain-cells = <0>;
1259   - power-domains =<&pd_vpu_mu_dec>;
1260   - };
1261   - };
1262   - };
1263   -
1264   -
1265 636 pd_isi_ch0: PD_IMAGING {
1266 637 compatible = "nxp,imx8-pd";
1267 638 reg = <SC_R_ISI_CH0>;
... ... @@ -1269,46 +640,6 @@
1269 640 #address-cells = <1>;
1270 641 #size-cells = <0>;
1271 642  
1272   - pd_csi0: PD_MIPI_CSI0 {
1273   - reg = <SC_R_CSI_0>;
1274   - #power-domain-cells = <0>;
1275   - power-domains =<&pd_isi_ch0>;
1276   - #address-cells = <1>;
1277   - #size-cells = <0>;
1278   -
1279   - pd_csi0_i2c0: PD_MIPI_CSI0_I2C0 {
1280   - reg = <SC_R_CSI_0_I2C_0>;
1281   - #power-domain-cells = <0>;
1282   - power-domains =<&pd_csi0>;
1283   - };
1284   -
1285   - pd_csi0_pwm: PD_MIPI_CSI0_PWM {
1286   - reg = <SC_R_CSI_0_PWM_0>;
1287   - #power-domain-cells = <0>;
1288   - power-domains =<&pd_csi0>;
1289   - };
1290   - };
1291   -
1292   - pd_csi1: PD_MIPI_CSI1 {
1293   - reg = <SC_R_CSI_1>;
1294   - #power-domain-cells = <0>;
1295   - power-domains =<&pd_isi_ch0>;
1296   - #address-cells = <1>;
1297   - #size-cells = <0>;
1298   -
1299   - pd_csi1_i2c0: PD_MIPI_CSI1_I2C0 {
1300   - reg = <SC_R_CSI_1_I2C_0>;
1301   - #power-domain-cells = <0>;
1302   - power-domains =<&pd_csi1>;
1303   - };
1304   -
1305   - pd_csi1_pwm: PD_MIPI_CSI1_PWM {
1306   - reg = <SC_R_CSI_1_PWM_0>;
1307   - #power-domain-cells = <0>;
1308   - power-domains =<&pd_csi1>;
1309   - };
1310   - };
1311   -
1312 643 pd_hdmi_rx: PD_HDMI_RX {
1313 644 reg = <SC_R_HDMI_RX>;
1314 645 #power-domain-cells = <0>;
1315 646  
... ... @@ -1337,120 +668,8 @@
1337 668 };
1338 669 };
1339 670  
1340   - pd_isi_ch1: PD_IMAGING_PDMA1 {
1341   - reg = <SC_R_ISI_CH1>;
1342   - #power-domain-cells = <0>;
1343   - power-domains =<&pd_isi_ch0>;
1344   - };
1345   -
1346   - pd_isi_ch2: PD_IMAGING_PDMA2 {
1347   - reg = <SC_R_ISI_CH2>;
1348   - #power-domain-cells = <0>;
1349   - power-domains =<&pd_isi_ch0>;
1350   - };
1351   -
1352   - pd_isi_ch3: PD_IMAGING_PDMA3 {
1353   - reg = <SC_R_ISI_CH3>;
1354   - #power-domain-cells = <0>;
1355   - power-domains =<&pd_isi_ch0>;
1356   - };
1357   -
1358   - pd_isi_ch4: PD_IMAGING_PDMA4 {
1359   - reg = <SC_R_ISI_CH4>;
1360   - #power-domain-cells = <0>;
1361   - power-domains =<&pd_isi_ch0>;
1362   - };
1363   -
1364   - pd_isi_ch5: PD_IMAGING_PDMA5 {
1365   - reg = <SC_R_ISI_CH5>;
1366   - #power-domain-cells = <0>;
1367   - power-domains =<&pd_isi_ch0>;
1368   - };
1369   -
1370   - pd_isi_ch6: PD_IMAGING_PDMA6 {
1371   - reg = <SC_R_ISI_CH6>;
1372   - #power-domain-cells = <0>;
1373   - power-domains =<&pd_isi_ch0>;
1374   - };
1375   -
1376   - pd_isi_ch7: PD_IMAGING_PDMA7 {
1377   - reg = <SC_R_ISI_CH7>;
1378   - #power-domain-cells = <0>;
1379   - power-domains =<&pd_isi_ch0>;
1380   - };
1381   -
1382   - pd_jpeg_dec_mp: PD_JPEG_DEC_MP {
1383   - reg = <SC_R_MJPEG_DEC_MP>;
1384   - #power-domain-cells = <0>;
1385   - power-domains =<&pd_isi_ch0>;
1386   - #address-cells = <1>;
1387   - #size-cells = <0>;
1388   -
1389   - pd_jpgdec: PD_IMAGING_JPEG_DEC {
1390   - reg = <SC_R_MJPEG_DEC_S0>;
1391   - #power-domain-cells = <0>;
1392   - power-domains =<&pd_jpeg_dec_mp>;
1393   - };
1394   - };
1395   -
1396   - pd_jpeg_enc_mp: PD_JPEG_ENC_MP {
1397   - reg = <SC_R_MJPEG_ENC_MP>;
1398   - #power-domain-cells = <0>;
1399   - power-domains =<&pd_isi_ch0>;
1400   - #address-cells = <1>;
1401   - #size-cells = <0>;
1402   -
1403   - pd_jpgenc: PD_IMAGING_JPEG_ENC {
1404   - reg = <SC_R_MJPEG_ENC_S0>;
1405   - #power-domain-cells = <0>;
1406   - power-domains =<&pd_jpeg_enc_mp>;
1407   - };
1408   - };
1409 671 };
1410 672  
1411   - pd_cm40: PD_CM40 {
1412   - compatible = "nxp,imx8-pd";
1413   - reg = <SC_R_NONE>;
1414   - #power-domain-cells = <0>;
1415   - #address-cells = <1>;
1416   - #size-cells = <0>;
1417   -
1418   - pd_cm40_i2c: PD_CM40_I2C {
1419   - reg = <SC_R_M4_0_I2C>;
1420   - #power-domain-cells = <0>;
1421   - power-domains =<&pd_cm40>;
1422   - };
1423   -
1424   - pd_cm40_intmux: PD_CM40_INTMUX {
1425   - reg = <SC_R_M4_0_INTMUX>;
1426   - #power-domain-cells = <0>;
1427   - power-domains =<&pd_cm40>;
1428   - };
1429   - };
1430   -
1431   - pd_cm41: PD_CM41 {
1432   - compatible = "nxp,imx8-pd";
1433   - reg = <SC_R_NONE>;
1434   - #power-domain-cells = <0>;
1435   - #address-cells = <1>;
1436   - #size-cells = <0>;
1437   -
1438   - pd_cm41_intmux: PD_CM41_INTMUX {
1439   - reg = <SC_R_M4_1_INTMUX>;
1440   - #power-domain-cells = <0>;
1441   - power-domains =<&pd_cm41>;
1442   - #address-cells = <1>;
1443   - #size-cells = <0>;
1444   - early_power_on;
1445   -
1446   - pd_cm41_i2c: PD_CM41_I2C {
1447   - reg = <SC_R_M4_1_I2C>;
1448   - #power-domain-cells = <0>;
1449   - power-domains =<&pd_cm41_intmux>;
1450   - };
1451   - };
1452   - };
1453   -
1454 673 pd_caam: PD_CAAM {
1455 674 compatible = "nxp,imx8-pd";
1456 675 reg = <SC_R_NONE>;
... ... @@ -1601,181 +820,6 @@
1601 820 reg = <0x0 0x56000000 0x0 0x10000>;
1602 821 };
1603 822  
1604   - pixel_combiner1: pixel-combiner@56020000 {
1605   - compatible = "fsl,imx8qm-pixel-combiner";
1606   - reg = <0x0 0x56020000 0x0 0x10000>;
1607   - power-domains = <&pd_dc0>;
1608   - status = "disabled";
1609   - };
1610   -
1611   - prg1: prg@56040000 {
1612   - compatible = "fsl,imx8qm-prg";
1613   - reg = <0x0 0x56040000 0x0 0x10000>;
1614   - clocks = <&clk IMX8QM_DC0_PRG0_APB_CLK>,
1615   - <&clk IMX8QM_DC0_PRG0_RTRAM_CLK>;
1616   - clock-names = "apb", "rtram";
1617   - power-domains = <&pd_dc0>;
1618   - status = "disabled";
1619   - };
1620   -
1621   - prg2: prg@56050000 {
1622   - compatible = "fsl,imx8qm-prg";
1623   - reg = <0x0 0x56050000 0x0 0x10000>;
1624   - clocks = <&clk IMX8QM_DC0_PRG1_APB_CLK>,
1625   - <&clk IMX8QM_DC0_PRG1_RTRAM_CLK>;
1626   - clock-names = "apb", "rtram";
1627   - power-domains = <&pd_dc0>;
1628   - status = "disabled";
1629   - };
1630   -
1631   - prg3: prg@56060000 {
1632   - compatible = "fsl,imx8qm-prg";
1633   - reg = <0x0 0x56060000 0x0 0x10000>;
1634   - clocks = <&clk IMX8QM_DC0_PRG2_APB_CLK>,
1635   - <&clk IMX8QM_DC0_PRG2_RTRAM_CLK>;
1636   - clock-names = "apb", "rtram";
1637   - power-domains = <&pd_dc0>;
1638   - status = "disabled";
1639   - };
1640   -
1641   - prg4: prg@56070000 {
1642   - compatible = "fsl,imx8qm-prg";
1643   - reg = <0x0 0x56070000 0x0 0x10000>;
1644   - clocks = <&clk IMX8QM_DC0_PRG3_APB_CLK>,
1645   - <&clk IMX8QM_DC0_PRG3_RTRAM_CLK>;
1646   - clock-names = "apb", "rtram";
1647   - power-domains = <&pd_dc0>;
1648   - status = "disabled";
1649   - };
1650   -
1651   - prg5: prg@56080000 {
1652   - compatible = "fsl,imx8qm-prg";
1653   - reg = <0x0 0x56080000 0x0 0x10000>;
1654   - clocks = <&clk IMX8QM_DC0_PRG4_APB_CLK>,
1655   - <&clk IMX8QM_DC0_PRG4_RTRAM_CLK>;
1656   - clock-names = "apb", "rtram";
1657   - power-domains = <&pd_dc0>;
1658   - status = "disabled";
1659   - };
1660   -
1661   - prg6: prg@56090000 {
1662   - compatible = "fsl,imx8qm-prg";
1663   - reg = <0x0 0x56090000 0x0 0x10000>;
1664   - clocks = <&clk IMX8QM_DC0_PRG5_APB_CLK>,
1665   - <&clk IMX8QM_DC0_PRG5_RTRAM_CLK>;
1666   - clock-names = "apb", "rtram";
1667   - power-domains = <&pd_dc0>;
1668   - status = "disabled";
1669   - };
1670   -
1671   - prg7: prg@560a0000 {
1672   - compatible = "fsl,imx8qm-prg";
1673   - reg = <0x0 0x560a0000 0x0 0x10000>;
1674   - clocks = <&clk IMX8QM_DC0_PRG6_APB_CLK>,
1675   - <&clk IMX8QM_DC0_PRG6_RTRAM_CLK>;
1676   - clock-names = "apb", "rtram";
1677   - power-domains = <&pd_dc0>;
1678   - status = "disabled";
1679   - };
1680   -
1681   - prg8: prg@560b0000 {
1682   - compatible = "fsl,imx8qm-prg";
1683   - reg = <0x0 0x560b0000 0x0 0x10000>;
1684   - clocks = <&clk IMX8QM_DC0_PRG7_APB_CLK>,
1685   - <&clk IMX8QM_DC0_PRG7_RTRAM_CLK>;
1686   - clock-names = "apb", "rtram";
1687   - power-domains = <&pd_dc0>;
1688   - status = "disabled";
1689   - };
1690   -
1691   - prg9: prg@560c0000 {
1692   - compatible = "fsl,imx8qm-prg";
1693   - reg = <0x0 0x560c0000 0x0 0x10000>;
1694   - clocks = <&clk IMX8QM_DC0_PRG8_APB_CLK>,
1695   - <&clk IMX8QM_DC0_PRG8_RTRAM_CLK>;
1696   - clock-names = "apb", "rtram";
1697   - power-domains = <&pd_dc0>;
1698   - status = "disabled";
1699   - };
1700   -
1701   - dpr1_channel1: dpr-channel@560d0000 {
1702   - compatible = "fsl,imx8qm-dpr-channel";
1703   - reg = <0x0 0x560d0000 0x0 0x10000>;
1704   - fsl,sc-resource = <SC_R_DC_0_BLIT0>;
1705   - fsl,prgs = <&prg1>;
1706   - clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>,
1707   - <&clk IMX8QM_DC0_DPR0_B_CLK>,
1708   - <&clk IMX8QM_DC0_RTRAM0_CLK>;
1709   - clock-names = "apb", "b", "rtram";
1710   - power-domains = <&pd_dc0>;
1711   - status = "disabled";
1712   - };
1713   -
1714   - dpr1_channel2: dpr-channel@560e0000 {
1715   - compatible = "fsl,imx8qm-dpr-channel";
1716   - reg = <0x0 0x560e0000 0x0 0x10000>;
1717   - fsl,sc-resource = <SC_R_DC_0_BLIT1>;
1718   - fsl,prgs = <&prg2>, <&prg1>;
1719   - clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>,
1720   - <&clk IMX8QM_DC0_DPR0_B_CLK>,
1721   - <&clk IMX8QM_DC0_RTRAM0_CLK>;
1722   - clock-names = "apb", "b", "rtram";
1723   - power-domains = <&pd_dc0>;
1724   - status = "disabled";
1725   - };
1726   -
1727   - dpr1_channel3: dpr-channel@560f0000 {
1728   - compatible = "fsl,imx8qm-dpr-channel";
1729   - reg = <0x0 0x560f0000 0x0 0x10000>;
1730   - fsl,sc-resource = <SC_R_DC_0_FRAC0>;
1731   - fsl,prgs = <&prg3>;
1732   - clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>,
1733   - <&clk IMX8QM_DC0_DPR0_B_CLK>,
1734   - <&clk IMX8QM_DC0_RTRAM0_CLK>;
1735   - clock-names = "apb", "b", "rtram";
1736   - power-domains = <&pd_dc0>;
1737   - status = "disabled";
1738   - };
1739   -
1740   - dpr2_channel1: dpr-channel@56100000 {
1741   - compatible = "fsl,imx8qm-dpr-channel";
1742   - reg = <0x0 0x56100000 0x0 0x10000>;
1743   - fsl,sc-resource = <SC_R_DC_0_VIDEO0>;
1744   - fsl,prgs = <&prg4>, <&prg5>;
1745   - clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
1746   - <&clk IMX8QM_DC0_DPR1_B_CLK>,
1747   - <&clk IMX8QM_DC0_RTRAM1_CLK>;
1748   - clock-names = "apb", "b", "rtram";
1749   - power-domains = <&pd_dc0>;
1750   - status = "disabled";
1751   - };
1752   -
1753   - dpr2_channel2: dpr-channel@56110000 {
1754   - compatible = "fsl,imx8qm-dpr-channel";
1755   - reg = <0x0 0x56110000 0x0 0x10000>;
1756   - fsl,sc-resource = <SC_R_DC_0_VIDEO1>;
1757   - fsl,prgs = <&prg6>, <&prg7>;
1758   - clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
1759   - <&clk IMX8QM_DC0_DPR1_B_CLK>,
1760   - <&clk IMX8QM_DC0_RTRAM1_CLK>;
1761   - clock-names = "apb", "b", "rtram";
1762   - power-domains = <&pd_dc0>;
1763   - status = "disabled";
1764   - };
1765   -
1766   - dpr2_channel3: dpr-channel@56120000 {
1767   - compatible = "fsl,imx8qm-dpr-channel";
1768   - reg = <0x0 0x56120000 0x0 0x10000>;
1769   - fsl,sc-resource = <SC_R_DC_0_WARP>;
1770   - fsl,prgs = <&prg8>, <&prg9>;
1771   - clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
1772   - <&clk IMX8QM_DC0_DPR1_B_CLK>,
1773   - <&clk IMX8QM_DC0_RTRAM1_CLK>;
1774   - clock-names = "apb", "b", "rtram";
1775   - power-domains = <&pd_dc0>;
1776   - status = "disabled";
1777   - };
1778   -
1779 823 dpu1: dpu@56180000 {
1780 824 #address-cells = <1>;
1781 825 #size-cells = <0>;
... ... @@ -1812,10 +856,6 @@
1812 856 clock-names = "pll0", "pll1", "bypass0",
1813 857 "disp0_sel", "disp1_sel", "disp0", "disp1";
1814 858 power-domains = <&pd_dc0_pll1>;
1815   - fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>,
1816   - <&dpr1_channel3>, <&dpr2_channel1>,
1817   - <&dpr2_channel2>, <&dpr2_channel3>;
1818   - fsl,pixel-combiner = <&pixel_combiner1>;
1819 859 status = "disabled";
1820 860  
1821 861 dpu1_disp0: port@0 {
... ... @@ -2075,181 +1115,6 @@
2075 1115 reg = <0x0 0x57000000 0x0 0x10000>;
2076 1116 };
2077 1117  
2078   - pixel_combiner2: pixel-combiner@57020000 {
2079   - compatible = "fsl,imx8qm-pixel-combiner";
2080   - reg = <0x0 0x57020000 0x0 0x10000>;
2081   - power-domains = <&pd_dc1>;
2082   - status = "disabled";
2083   - };
2084   -
2085   - prg10: prg@57040000 {
2086   - compatible = "fsl,imx8qm-prg";
2087   - reg = <0x0 0x57040000 0x0 0x10000>;
2088   - clocks = <&clk IMX8QM_DC1_PRG0_APB_CLK>,
2089   - <&clk IMX8QM_DC1_PRG0_RTRAM_CLK>;
2090   - clock-names = "apb", "rtram";
2091   - power-domains = <&pd_dc1>;
2092   - status = "disabled";
2093   - };
2094   -
2095   - prg11: prg@57050000 {
2096   - compatible = "fsl,imx8qm-prg";
2097   - reg = <0x0 0x57050000 0x0 0x10000>;
2098   - clocks = <&clk IMX8QM_DC1_PRG1_APB_CLK>,
2099   - <&clk IMX8QM_DC1_PRG1_RTRAM_CLK>;
2100   - clock-names = "apb", "rtram";
2101   - power-domains = <&pd_dc1>;
2102   - status = "disabled";
2103   - };
2104   -
2105   - prg12: prg@57060000 {
2106   - compatible = "fsl,imx8qm-prg";
2107   - reg = <0x0 0x57060000 0x0 0x10000>;
2108   - clocks = <&clk IMX8QM_DC1_PRG2_APB_CLK>,
2109   - <&clk IMX8QM_DC1_PRG2_RTRAM_CLK>;
2110   - clock-names = "apb", "rtram";
2111   - power-domains = <&pd_dc1>;
2112   - status = "disabled";
2113   - };
2114   -
2115   - prg13: prg@57070000 {
2116   - compatible = "fsl,imx8qm-prg";
2117   - reg = <0x0 0x57070000 0x0 0x10000>;
2118   - clocks = <&clk IMX8QM_DC1_PRG3_APB_CLK>,
2119   - <&clk IMX8QM_DC1_PRG3_RTRAM_CLK>;
2120   - clock-names = "apb", "rtram";
2121   - power-domains = <&pd_dc1>;
2122   - status = "disabled";
2123   - };
2124   -
2125   - prg14: prg@57080000 {
2126   - compatible = "fsl,imx8qm-prg";
2127   - reg = <0x0 0x57080000 0x0 0x10000>;
2128   - clocks = <&clk IMX8QM_DC1_PRG4_APB_CLK>,
2129   - <&clk IMX8QM_DC1_PRG4_RTRAM_CLK>;
2130   - clock-names = "apb", "rtram";
2131   - power-domains = <&pd_dc1>;
2132   - status = "disabled";
2133   - };
2134   -
2135   - prg15: prg@57090000 {
2136   - compatible = "fsl,imx8qm-prg";
2137   - reg = <0x0 0x57090000 0x0 0x10000>;
2138   - clocks = <&clk IMX8QM_DC1_PRG5_APB_CLK>,
2139   - <&clk IMX8QM_DC1_PRG5_RTRAM_CLK>;
2140   - clock-names = "apb", "rtram";
2141   - power-domains = <&pd_dc1>;
2142   - status = "disabled";
2143   - };
2144   -
2145   - prg16: prg@570a0000 {
2146   - compatible = "fsl,imx8qm-prg";
2147   - reg = <0x0 0x570a0000 0x0 0x10000>;
2148   - clocks = <&clk IMX8QM_DC1_PRG6_APB_CLK>,
2149   - <&clk IMX8QM_DC1_PRG6_RTRAM_CLK>;
2150   - clock-names = "apb", "rtram";
2151   - power-domains = <&pd_dc1>;
2152   - status = "disabled";
2153   - };
2154   -
2155   - prg17: prg@570b0000 {
2156   - compatible = "fsl,imx8qm-prg";
2157   - reg = <0x0 0x570b0000 0x0 0x10000>;
2158   - clocks = <&clk IMX8QM_DC1_PRG7_APB_CLK>,
2159   - <&clk IMX8QM_DC1_PRG7_RTRAM_CLK>;
2160   - clock-names = "apb", "rtram";
2161   - power-domains = <&pd_dc1>;
2162   - status = "disabled";
2163   - };
2164   -
2165   - prg18: prg@570c0000 {
2166   - compatible = "fsl,imx8qm-prg";
2167   - reg = <0x0 0x570c0000 0x0 0x10000>;
2168   - clocks = <&clk IMX8QM_DC1_PRG8_APB_CLK>,
2169   - <&clk IMX8QM_DC1_PRG8_RTRAM_CLK>;
2170   - clock-names = "apb", "rtram";
2171   - power-domains = <&pd_dc1>;
2172   - status = "disabled";
2173   - };
2174   -
2175   - dpr3_channel1: dpr-channel@570d0000 {
2176   - compatible = "fsl,imx8qm-dpr-channel";
2177   - reg = <0x0 0x570d0000 0x0 0x10000>;
2178   - fsl,sc-resource = <SC_R_DC_1_BLIT0>;
2179   - fsl,prgs = <&prg10>;
2180   - clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>,
2181   - <&clk IMX8QM_DC1_DPR0_B_CLK>,
2182   - <&clk IMX8QM_DC1_RTRAM0_CLK>;
2183   - clock-names = "apb", "b", "rtram";
2184   - power-domains = <&pd_dc1>;
2185   - status = "disabled";
2186   - };
2187   -
2188   - dpr3_channel2: dpr-channel@570e0000 {
2189   - compatible = "fsl,imx8qm-dpr-channel";
2190   - reg = <0x0 0x570e0000 0x0 0x10000>;
2191   - fsl,sc-resource = <SC_R_DC_1_BLIT1>;
2192   - fsl,prgs = <&prg11>, <&prg10>;
2193   - clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>,
2194   - <&clk IMX8QM_DC1_DPR0_B_CLK>,
2195   - <&clk IMX8QM_DC1_RTRAM0_CLK>;
2196   - clock-names = "apb", "b", "rtram";
2197   - power-domains = <&pd_dc1>;
2198   - status = "disabled";
2199   - };
2200   -
2201   - dpr3_channel3: dpr-channel@570f0000 {
2202   - compatible = "fsl,imx8qm-dpr-channel";
2203   - reg = <0x0 0x570f0000 0x0 0x10000>;
2204   - fsl,sc-resource = <SC_R_DC_1_FRAC0>;
2205   - fsl,prgs = <&prg12>;
2206   - clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>,
2207   - <&clk IMX8QM_DC1_DPR0_B_CLK>,
2208   - <&clk IMX8QM_DC1_RTRAM0_CLK>;
2209   - clock-names = "apb", "b", "rtram";
2210   - power-domains = <&pd_dc1>;
2211   - status = "disabled";
2212   - };
2213   -
2214   - dpr4_channel1: dpr-channel@57100000 {
2215   - compatible = "fsl,imx8qm-dpr-channel";
2216   - reg = <0x0 0x57100000 0x0 0x10000>;
2217   - fsl,sc-resource = <SC_R_DC_1_VIDEO0>;
2218   - fsl,prgs = <&prg13>, <&prg14>;
2219   - clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>,
2220   - <&clk IMX8QM_DC1_DPR1_B_CLK>,
2221   - <&clk IMX8QM_DC1_RTRAM1_CLK>;
2222   - clock-names = "apb", "b", "rtram";
2223   - power-domains = <&pd_dc1>;
2224   - status = "disabled";
2225   - };
2226   -
2227   - dpr4_channel2: dpr-channel@57110000 {
2228   - compatible = "fsl,imx8qm-dpr-channel";
2229   - reg = <0x0 0x57110000 0x0 0x10000>;
2230   - fsl,sc-resource = <SC_R_DC_1_VIDEO1>;
2231   - fsl,prgs = <&prg15>, <&prg16>;
2232   - clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>,
2233   - <&clk IMX8QM_DC1_DPR1_B_CLK>,
2234   - <&clk IMX8QM_DC1_RTRAM1_CLK>;
2235   - clock-names = "apb", "b", "rtram";
2236   - power-domains = <&pd_dc1>;
2237   - status = "disabled";
2238   - };
2239   -
2240   - dpr4_channel3: dpr-channel@56712000 {
2241   - compatible = "fsl,imx8qm-dpr-channel";
2242   - reg = <0x0 0x57120000 0x0 0x10000>;
2243   - fsl,sc-resource = <SC_R_DC_1_WARP>;
2244   - fsl,prgs = <&prg17>, <&prg18>;
2245   - clocks = <&clk IMX8QM_DC1_DPR1_APB_CLK>,
2246   - <&clk IMX8QM_DC1_DPR1_B_CLK>,
2247   - <&clk IMX8QM_DC1_RTRAM1_CLK>;
2248   - clock-names = "apb", "b", "rtram";
2249   - power-domains = <&pd_dc1>;
2250   - status = "disabled";
2251   - };
2252   -
2253 1118 dpu2: dpu@57180000 {
2254 1119 #address-cells = <1>;
2255 1120 #size-cells = <0>;
... ... @@ -2286,10 +1151,6 @@
2286 1151 clock-names = "pll0", "pll1", "bypass0",
2287 1152 "disp0_sel", "disp1_sel", "disp0", "disp1";
2288 1153 power-domains = <&pd_dc1_pll1>;
2289   - fsl,dpr-channels = <&dpr3_channel1>, <&dpr3_channel2>,
2290   - <&dpr3_channel3>, <&dpr4_channel1>,
2291   - <&dpr4_channel2>, <&dpr4_channel3>;
2292   - fsl,pixel-combiner = <&pixel_combiner2>;
2293 1154 status = "disabled";
2294 1155  
2295 1156 dpu2_disp0: port@0 {
... ... @@ -2515,133 +1376,6 @@
2515 1376 status = "disabled";
2516 1377 };
2517 1378  
2518   - isi_1: isi@58110000 {
2519   - compatible = "fsl,imx8-isi";
2520   - reg = <0x0 0x58110000 0x0 0x10000>;
2521   - interrupts = <0 298 0>;
2522   - interface = <2 1 2>;
2523   - clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>;
2524   - clock-names = "per";
2525   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>;
2526   - assigned-clock-rates = <600000000>;
2527   - power-domains =<&pd_isi_ch1>;
2528   - status = "disabled";
2529   - };
2530   -
2531   - isi_2: isi@58120000 {
2532   - compatible = "fsl,imx8-isi";
2533   - reg = <0x0 0x58120000 0x0 0x10000>;
2534   - interrupts = <0 299 0>;
2535   - interface = <2 2 2>;
2536   - clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>;
2537   - clock-names = "per";
2538   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>;
2539   - assigned-clock-rates = <600000000>;
2540   - power-domains =<&pd_isi_ch2>;
2541   - status = "disabled";
2542   - };
2543   -
2544   - isi_3: isi@58130000 {
2545   - compatible = "fsl,imx8-isi";
2546   - reg = <0x0 0x58130000 0x0 0x10000>;
2547   - interrupts = <0 300 0>;
2548   - interface = <2 3 2>;
2549   - clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>;
2550   - clock-names = "per";
2551   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>;
2552   - assigned-clock-rates = <600000000>;
2553   - power-domains =<&pd_isi_ch3>;
2554   - status = "disabled";
2555   - };
2556   -
2557   - isi_4: isi@58140000 {
2558   - compatible = "fsl,imx8-isi";
2559   - reg = <0x0 0x58140000 0x0 0x10000>;
2560   - interrupts = <0 301 0>;
2561   - interface = <3 0 2>;
2562   - clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>;
2563   - clock-names = "per";
2564   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>;
2565   - assigned-clock-rates = <600000000>;
2566   - power-domains =<&pd_isi_ch4>;
2567   - status = "disabled";
2568   - };
2569   -
2570   - isi_5: isi@58150000 {
2571   - compatible = "fsl,imx8-isi";
2572   - reg = <0x0 0x58150000 0x0 0x10000>;
2573   - interrupts = <0 302 0>;
2574   - interface = <3 1 2>;
2575   - clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>;
2576   - clock-names = "per";
2577   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>;
2578   - assigned-clock-rates = <600000000>;
2579   - power-domains =<&pd_isi_ch5>;
2580   - status = "disabled";
2581   - };
2582   -
2583   - isi_6: isi@58160000 {
2584   - compatible = "fsl,imx8-isi";
2585   - reg = <0x0 0x58160000 0x0 0x10000>;
2586   - interrupts = <0 303 0>;
2587   - interface = <3 2 2>;
2588   - clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>;
2589   - clock-names = "per";
2590   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>;
2591   - assigned-clock-rates = <600000000>;
2592   - power-domains =<&pd_isi_ch6>;
2593   - status = "disabled";
2594   - };
2595   -
2596   - isi_7: isi@58170000 {
2597   - compatible = "fsl,imx8-isi";
2598   - reg = <0x0 0x58170000 0x0 0x10000>;
2599   - interrupts = <0 304 0>;
2600   - interface = <3 3 2>;
2601   - clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>;
2602   - clock-names = "per";
2603   - assigned-clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>;
2604   - assigned-clock-rates = <600000000>;
2605   - power-domains =<&pd_isi_ch7>;
2606   - status = "disabled";
2607   - };
2608   -
2609   - mipi_csi_0: csi@58227000 {
2610   - compatible = "fsl,mxc-mipi-csi2";
2611   - reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */
2612   - <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */
2613   - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
2614   - interrupt-parent = <&irqsteer_csi0>;
2615   - clocks = <&clk IMX8QM_CLK_DUMMY>,
2616   - <&clk IMX8QM_CSI0_CORE_CLK>,
2617   - <&clk IMX8QM_CSI0_ESC_CLK>,
2618   - <&clk IMX8QM_IMG_PXL_LINK_CSI0_CLK>;
2619   - clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
2620   - assigned-clocks = <&clk IMX8QM_CSI0_CORE_CLK>,
2621   - <&clk IMX8QM_CSI0_ESC_CLK>;
2622   - assigned-clock-rates = <360000000>, <72000000>;
2623   - power-domains = <&pd_csi0>;
2624   - status = "disabled";
2625   - };
2626   -
2627   - mipi_csi_1: csi@58247000 {
2628   - compatible = "fsl,mxc-mipi-csi2";
2629   - reg = <0x0 0x58247000 0x0 0x1000>, /* CSI1 Controler base addr */
2630   - <0x0 0x58241000 0x0 0x1000>; /* CSI1 Subsystem CSR base addr */
2631   - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
2632   - interrupt-parent = <&irqsteer_csi1>;
2633   - clocks = <&clk IMX8QM_CLK_DUMMY>,
2634   - <&clk IMX8QM_CSI1_CORE_CLK>,
2635   - <&clk IMX8QM_CSI1_ESC_CLK>,
2636   - <&clk IMX8QM_IMG_PXL_LINK_CSI1_CLK>;
2637   - clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
2638   - assigned-clocks = <&clk IMX8QM_CSI1_CORE_CLK>,
2639   - <&clk IMX8QM_CSI1_ESC_CLK>;
2640   - assigned-clock-rates = <360000000>, <72000000>;
2641   - power-domains = <&pd_csi1>;
2642   - status = "disabled";
2643   - };
2644   -
2645 1379 hdmi_rx: hdmi_rx@58268000 {
2646 1380 compatible = "fsl,imx-hdmi-rx";
2647 1381 reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */
2648 1382  
... ... @@ -2667,62 +1401,8 @@
2667 1401 power-domains = <&pd_hdmi_rx_bypass>;
2668 1402 status = "disabled";
2669 1403 };
2670   -
2671   - jpegdec: jpegdec@58400000 {
2672   - compatible = "fsl,imx8-jpgdec";
2673   - reg = <0x0 0x58400000 0x0 0x00040020 >;
2674   - interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2675   - clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >,
2676   - <&clk IMX8QM_IMG_JPEG_DEC_CLK >;
2677   - clock-names = "ipg", "per";
2678   - assigned-clocks = <&clk IMX8QM_IMG_JPEG_DEC_IPG_CLK >,
2679   - <&clk IMX8QM_IMG_JPEG_DEC_CLK >;
2680   - assigned-clock-rates = <200000000>;
2681   - power-domains =<&pd_jpgdec>;
2682   - };
2683   -
2684   - jpegenc: jpegenc@58450000 {
2685   - compatible = "fsl,imx8-jpgenc";
2686   - reg = <0x0 0x58450000 0x0 0x00240020 >;
2687   - interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2688   - clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >,
2689   - <&clk IMX8QM_IMG_JPEG_ENC_CLK >;
2690   - clock-names = "ipg", "per";
2691   - assigned-clocks = <&clk IMX8QM_IMG_JPEG_ENC_IPG_CLK >,
2692   - <&clk IMX8QM_IMG_JPEG_ENC_CLK >;
2693   - assigned-clock-rates = <200000000>;
2694   - power-domains =<&pd_jpgenc>;
2695   - };
2696 1404 };
2697 1405  
2698   - adc0: adc@5a880000 {
2699   - compatible = "fsl,imx8qxp-adc";
2700   - reg = <0x0 0x5a880000 0x0 0x10000>;
2701   - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
2702   - interrupt-parent = <&gic>;
2703   - clocks = <&clk IMX8QM_ADC0_CLK>,
2704   - <&clk IMX8QM_ADC0_IPG_CLK>;
2705   - clock-names = "per", "ipg";
2706   - assigned-clocks = <&clk IMX8QM_ADC0_CLK>;
2707   - assigned-clock-rates = <24000000>;
2708   - power-domains = <&pd_dma_adc0>;
2709   - status = "disabled";
2710   - };
2711   -
2712   - adc1: adc@5a890000 {
2713   - compatible = "fsl,imx8qxp-adc";
2714   - reg = <0x0 0x5a890000 0x0 0x10000>;
2715   - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
2716   - interrupt-parent = <&gic>;
2717   - clocks = <&clk IMX8QM_ADC1_CLK>,
2718   - <&clk IMX8QM_ADC1_IPG_CLK>;
2719   - clock-names = "per", "ipg";
2720   - assigned-clocks = <&clk IMX8QM_ADC1_CLK>;
2721   - assigned-clock-rates = <24000000>;
2722   - power-domains = <&pd_dma_adc1>;
2723   - status = "disabled";
2724   - };
2725   -
2726 1406 i2c0: i2c@5a800000 {
2727 1407 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
2728 1408 reg = <0x0 0x5a800000 0x0 0x4000>;
... ... @@ -2793,34 +1473,6 @@
2793 1473 status = "disabled";
2794 1474 };
2795 1475  
2796   - i2c0_cm40: i2c@37230000 {
2797   - compatible = "fsl,imx8qm-lpi2c";
2798   - reg = <0x0 0x37230000 0x0 0x1000>;
2799   - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
2800   - interrupt-parent = <&intmux_cm40>;
2801   - clocks = <&clk IMX8QM_CM40_I2C_CLK>,
2802   - <&clk IMX8QM_CM40_I2C_IPG_CLK>;
2803   - clock-names = "per", "ipg";
2804   - assigned-clocks = <&clk IMX8QM_CM40_I2C_CLK>;
2805   - assigned-clock-rates = <24000000>;
2806   - power-domains = <&pd_cm40_i2c>;
2807   - status = "disabled";
2808   - };
2809   -
2810   - i2c0_cm41: i2c@3b230000 {
2811   - compatible = "fsl,imx8qm-lpi2c";
2812   - reg = <0x0 0x3b230000 0x0 0x1000>;
2813   - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
2814   - interrupt-parent = <&intmux_cm41>;
2815   - clocks = <&clk IMX8QM_CM41_I2C_CLK>,
2816   - <&clk IMX8QM_CM41_I2C_IPG_CLK>;
2817   - clock-names = "per", "ipg";
2818   - assigned-clocks = <&clk IMX8QM_CM41_I2C_CLK>;
2819   - assigned-clock-rates = <24000000>;
2820   - power-domains = <&pd_cm41_i2c>;
2821   - status = "disabled";
2822   - };
2823   -
2824 1476 irqsteer_hdmi: irqsteer@56260000 {
2825 1477 compatible = "nxp,imx-irqsteer";
2826 1478 reg = <0x0 0x56260000 0x0 0x1000>;
2827 1479  
... ... @@ -2875,48 +1527,7 @@
2875 1527 power-domains = <&pd_lvds0>;
2876 1528 };
2877 1529  
2878   - flexcan1: can@5a8d0000 {
2879   - compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
2880   - reg = <0x0 0x5a8d0000 0x0 0x10000>;
2881   - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
2882   - interrupt-parent = <&wu>;
2883   - clocks = <&clk IMX8QM_CAN0_IPG_CLK>,
2884   - <&clk IMX8QM_CAN0_CLK>;
2885   - clock-names = "ipg", "per";
2886   - assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
2887   - assigned-clock-rates = <40000000>;
2888   - power-domains = <&pd_dma_flexcan0>;
2889   - status = "disabled";
2890   - };
2891 1530  
2892   - flexcan2: can@5a8e0000 {
2893   - compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
2894   - reg = <0x0 0x5a8e0000 0x0 0x10000>;
2895   - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
2896   - interrupt-parent = <&wu>;
2897   - clocks = <&clk IMX8QM_CAN1_IPG_CLK>,
2898   - <&clk IMX8QM_CAN1_CLK>;
2899   - clock-names = "ipg", "per";
2900   - assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
2901   - assigned-clock-rates = <40000000>;
2902   - power-domains = <&pd_dma_flexcan1>;
2903   - status = "disabled";
2904   - };
2905   -
2906   - flexcan3: can@5a8f0000 {
2907   - compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
2908   - reg = <0x0 0x5a8f0000 0x0 0x10000>;
2909   - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
2910   - interrupt-parent = <&wu>;
2911   - clocks = <&clk IMX8QM_CAN2_IPG_CLK>,
2912   - <&clk IMX8QM_CAN2_CLK>;
2913   - clock-names = "ipg", "per";
2914   - assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
2915   - assigned-clock-rates = <40000000>;
2916   - power-domains = <&pd_dma_flexcan2>;
2917   - status = "disabled";
2918   - };
2919   -
2920 1531 i2c1_lvds0: i2c@56247000 {
2921 1532 compatible = "fsl,imx8qm-lpi2c";
2922 1533 reg = <0x0 0x56247000 0x0 0x1000>;
... ... @@ -2957,58 +1568,6 @@
2957 1568 status = "disabled";
2958 1569 };
2959 1570  
2960   - irqsteer_csi0: irqsteer@58220000 {
2961   - compatible = "nxp,imx-irqsteer";
2962   - reg = <0x0 0x58220000 0x0 0x1000>;
2963   - interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
2964   - interrupt-controller;
2965   - interrupt-parent = <&gic>;
2966   - #interrupt-cells = <2>;
2967   - clocks = <&clk IMX8QM_CLK_DUMMY>;
2968   - clock-names = "ipg";
2969   - power-domains = <&pd_csi0>;
2970   - };
2971   -
2972   - i2c0_mipi_csi0: i2c@58226000 {
2973   - compatible = "fsl,imx8qm-lpi2c";
2974   - reg = <0x0 0x58226000 0x0 0x1000>;
2975   - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
2976   - interrupt-parent = <&irqsteer_csi0>;
2977   - clocks = <&clk IMX8QM_CSI0_I2C0_CLK>,
2978   - <&clk IMX8QM_CSI0_I2C0_IPG_CLK>;
2979   - clock-names = "per", "ipg";
2980   - assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>;
2981   - assigned-clock-rates = <24000000>;
2982   - power-domains = <&pd_csi0_i2c0>;
2983   - status = "disabled";
2984   - };
2985   -
2986   - irqsteer_csi1: irqsteer@582400000 {
2987   - compatible = "nxp,imx-irqsteer";
2988   - reg = <0x0 0x58240000 0x0 0x1000>;
2989   - interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2990   - interrupt-controller;
2991   - interrupt-parent = <&gic>;
2992   - #interrupt-cells = <2>;
2993   - clocks = <&clk IMX8QM_CLK_DUMMY>;
2994   - clock-names = "ipg";
2995   - power-domains = <&pd_csi1>;
2996   - };
2997   -
2998   - i2c0_mipi_csi1: i2c@58246000 {
2999   - compatible = "fsl,imx8qm-lpi2c";
3000   - reg = <0x0 0x58246000 0x0 0x1000>;
3001   - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
3002   - interrupt-parent = <&irqsteer_csi1>;
3003   - clocks = <&clk IMX8QM_CSI1_I2C0_CLK>,
3004   - <&clk IMX8QM_CSI1_I2C0_IPG_CLK>;
3005   - clock-names = "per", "ipg";
3006   - assigned-clocks = <&clk IMX8QM_CSI1_I2C0_CLK>;
3007   - assigned-clock-rates = <24000000>;
3008   - power-domains = <&pd_csi1_i2c0>;
3009   - status = "disabled";
3010   - };
3011   -
3012 1571 lpspi0: lpspi@5a000000 {
3013 1572 compatible = "fsl,imx7ulp-spi";
3014 1573 reg = <0x0 0x5a000000 0x0 0x10000>;
... ... @@ -3123,53 +1682,6 @@
3123 1682 status = "disabled";
3124 1683 };
3125 1684  
3126   - ftmpwm0: ftmpwm@0x05a8a0000 {
3127   - compatible = "fsl,vf610-ftm-pwm";
3128   - reg = <0 0x5A8A0000 0 0x1000>;
3129   - #pwm-cells = <3>;
3130   - clock-names = "ftm_sys", "ftm_ext",
3131   - "ftm_fix", "ftm_cnt_clk_en", "ipg";
3132   - clocks = <&clk IMX8QM_FTM0_CLK>,
3133   - <&clk IMX8QM_CLK_DUMMY>,
3134   - <&clk IMX8QM_FTM0_CLK>,
3135   - <&clk IMX8QM_CLK_DUMMY>,
3136   - <&clk IMX8QM_FTM0_IPG_CLK>;
3137   - assigned-clocks = <&clk IMX8QM_FTM0_CLK>;
3138   - assigned-clock-rates = <8000000>;
3139   - power-domains = <&pd_dma_ftm0>;
3140   - ftm-has-pwmen-bits;
3141   - status = "disabled";
3142   - };
3143   -
3144   - ftmpwm1: ftmpwm@0x05a8b0000 {
3145   - compatible = "fsl,vf610-ftm-pwm";
3146   - reg = <0 0x5A8B0000 0 0x1000>;
3147   - #pwm-cells = <3>;
3148   - clock-names = "ftm_sys", "ftm_ext",
3149   - "ftm_fix", "ftm_cnt_clk_en", "ipg";
3150   - clocks = <&clk IMX8QM_FTM1_CLK>,
3151   - <&clk IMX8QM_CLK_DUMMY>,
3152   - <&clk IMX8QM_FTM1_CLK>,
3153   - <&clk IMX8QM_CLK_DUMMY>,
3154   - <&clk IMX8QM_FTM0_IPG_CLK>;
3155   - assigned-clocks = <&clk IMX8QM_FTM1_CLK>;
3156   - assigned-clock-rates = <8000000>;
3157   - power-domains = <&pd_dma_ftm1>;
3158   - ftm-has-pwmen-bits;
3159   - status = "disabled";
3160   - };
3161   -
3162   - emvsim0: sim0@5a0d0000 {
3163   - compatible = "fsl,imx8-emvsim";
3164   - reg = <0x0 0x5a0d0000 0x0 0x10000>;
3165   - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
3166   - clocks = <&clk IMX8QM_EMVSIM0_CLK>,
3167   - <&clk IMX8QM_EMVSIM0_IPG_CLK>;
3168   - clock-names = "sim", "ipg";
3169   - power-domains = <&pd_ldo1_sim>;
3170   - status = "disabled";
3171   - };
3172   -
3173 1685 edma0: dma-controller@5a1f0000 {
3174 1686 compatible = "fsl,imx8qm-edma";
3175 1687 reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
... ... @@ -3391,174 +1903,6 @@
3391 1903 #interrupt-cells = <2>;
3392 1904 };
3393 1905  
3394   - gpio0_mipi_csi0: gpio@58222000 {
3395   - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
3396   - reg = <0x0 0x58222000 0x0 0x1000>;
3397   - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3398   - interrupt-parent = <&irqsteer_csi0>;
3399   - gpio-controller;
3400   - #gpio-cells = <2>;
3401   - interrupt-controller;
3402   - #interrupt-cells = <2>;
3403   - power-domains = <&pd_csi0>;
3404   - status = "disabled";
3405   - };
3406   -
3407   - gpio0_mipi_csi1: gpio@58242000 {
3408   - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
3409   - reg = <0x0 0x58242000 0x0 0x1000>;
3410   - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3411   - interrupt-parent = <&irqsteer_csi1>;
3412   - gpio-controller;
3413   - #gpio-cells = <2>;
3414   - interrupt-controller;
3415   - #interrupt-cells = <2>;
3416   - power-domains = <&pd_csi1>;
3417   - status = "disabled";
3418   - };
3419   -
3420   - gpt0: gpt0@5d140000 {
3421   - compatible = "fsl,imx8qm-gpt";
3422   - reg = <0x0 0x5d140000 0x0 0x4000>;
3423   - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
3424   - clocks = <&clk IMX8QM_GPT0_CLK>, <&clk IMX8QM_GPT_3M>;
3425   - clock-names = "ipg", "per";
3426   - power-domains = <&pd_lsio_gpt0>;
3427   - };
3428   -
3429   - pwm0: pwm@5d000000 {
3430   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3431   - reg = <0x0 0x5d000000 0 0x10000>;
3432   - clocks = <&clk IMX8QM_PWM0_HF_CLK>,
3433   - <&clk IMX8QM_PWM0_HF_CLK>;
3434   - clock-names = "ipg", "per";
3435   - assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>;
3436   - assigned-clock-rates = <24000000>;
3437   - #pwm-cells = <2>;
3438   - status = "disabled";
3439   - };
3440   -
3441   -
3442   - pwm1: pwm@5d010000 {
3443   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3444   - reg = <0x0 0x5d010000 0 0x10000>;
3445   - clocks = <&clk IMX8QM_PWM1_HF_CLK>,
3446   - <&clk IMX8QM_PWM1_HF_CLK>;
3447   - clock-names = "ipg", "per";
3448   - assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>;
3449   - assigned-clock-rates = <24000000>;
3450   - #pwm-cells = <2>;
3451   - status = "disabled";
3452   - };
3453   -
3454   - pwm2: pwm@5d020000 {
3455   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3456   - reg = <0x0 0x5d020000 0 0x10000>;
3457   - clocks = <&clk IMX8QM_PWM2_HF_CLK>,
3458   - <&clk IMX8QM_PWM2_HF_CLK>;
3459   - clock-names = "ipg", "per";
3460   - assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>;
3461   - assigned-clock-rates = <24000000>;
3462   - #pwm-cells = <2>;
3463   - status = "disabled";
3464   - };
3465   -
3466   - pwm3: pwm@5d030000 {
3467   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3468   - reg = <0x0 0x5d030000 0 0x10000>;
3469   - clocks = <&clk IMX8QM_PWM3_HF_CLK>,
3470   - <&clk IMX8QM_PWM3_HF_CLK>;
3471   - clock-names = "ipg", "per";
3472   - assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>;
3473   - assigned-clock-rates = <24000000>;
3474   - #pwm-cells = <2>;
3475   - status = "disabled";
3476   - };
3477   -
3478   - pwm4: pwm@5d040000 {
3479   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3480   - reg = <0x0 0x5d040000 0 0x10000>;
3481   - clocks = <&clk IMX8QM_PWM4_HF_CLK>,
3482   - <&clk IMX8QM_PWM4_HF_CLK>;
3483   - clock-names = "ipg", "per";
3484   - assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>;
3485   - assigned-clock-rates = <24000000>;
3486   - #pwm-cells = <2>;
3487   - status = "disabled";
3488   - };
3489   -
3490   - pwm5: pwm@5d050000 {
3491   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3492   - reg = <0x0 0x5d050000 0 0x10000>;
3493   - clocks = <&clk IMX8QM_PWM5_HF_CLK>,
3494   - <&clk IMX8QM_PWM5_HF_CLK>;
3495   - clock-names = "ipg", "per";
3496   - assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>;
3497   - assigned-clock-rates = <24000000>;
3498   - #pwm-cells = <2>;
3499   - status = "disabled";
3500   - };
3501   -
3502   - pwm6: pwm@5d060000 {
3503   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3504   - reg = <0x0 0x5d060000 0 0x10000>;
3505   - clocks = <&clk IMX8QM_PWM6_HF_CLK>,
3506   - <&clk IMX8QM_PWM6_HF_CLK>;
3507   - clock-names = "ipg", "per";
3508   - assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>;
3509   - assigned-clock-rates = <24000000>;
3510   - #pwm-cells = <2>;
3511   - status = "disabled";
3512   - };
3513   -
3514   - pwm7: pwm@5d070000 {
3515   - compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
3516   - reg = <0x0 0x5d070000 0 0x10000>;
3517   - clocks = <&clk IMX8QM_PWM7_HF_CLK>,
3518   - <&clk IMX8QM_PWM7_HF_CLK>;
3519   - clock-names = "ipg", "per";
3520   - assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>;
3521   - assigned-clock-rates = <24000000>;
3522   - #pwm-cells = <2>;
3523   - status = "disabled";
3524   - };
3525   -
3526   -
3527   - gpu_3d0: gpu@53100000 {
3528   - compatible = "fsl,imx8-gpu";
3529   - reg = <0x0 0x53100000 0 0x40000>;
3530   - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
3531   - clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>;
3532   - clock-names = "core", "shader";
3533   - assigned-clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>;
3534   - assigned-clock-rates = <800000000>, <1000000000>;
3535   - fsl,sc_gpu_pid = <SC_R_GPU_0_PID0>;
3536   - power-domains = <&pd_gpu0>;
3537   - status = "disabled";
3538   - };
3539   -
3540   - gpu_3d1: gpu@54100000 {
3541   - compatible = "fsl,imx8-gpu";
3542   - reg = <0x0 0x54100000 0x0 0x40000>;
3543   - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
3544   - clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>;
3545   - clock-names = "core", "shader";
3546   - assigned-clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>;
3547   - assigned-clock-rates = <800000000>, <1000000000>;
3548   - fsl,sc_gpu_pid = <SC_R_GPU_1_PID0>;
3549   - power-domains = <&pd_gpu1>;
3550   - status = "disabled";
3551   - };
3552   -
3553   - imx8_gpu_ss: imx8_gpu_ss {
3554   - compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss";
3555   - cores = <&gpu_3d0>, <&gpu_3d1>;
3556   - reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>;
3557   - reg-names = "phys_baseaddr", "contiguous_mem";
3558   - depth-compression = <0>;
3559   - status = "disabled";
3560   - };
3561   -
3562 1906 mlb: mlb@5B060000 {
3563 1907 compatible = "fsl,imx6q-mlb150";
3564 1908 reg = <0x0 0x5B060000 0x0 0x10000>;
... ... @@ -3780,359 +2124,6 @@
3780 2124 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3781 2125 };
3782 2126  
3783   - vpu: vpu@2c000000 {
3784   - compatible = "nxp,imx8qm-vpu", "nxp,imx8x-vpu";
3785   - reg = <0x0 0x2c000000 0x0 0x1000000>;
3786   - reg-names = "iobase_vpu";
3787   - interrupts = <0 464 0x4>;
3788   - interrupt-names = "irq_vpu";
3789   - clocks = <&clk IMX8QM_VPU_DDR_CLK>,
3790   - <&clk IMX8QM_VPU_SYS_CLK>,
3791   - <&clk IMX8QM_VPU_XUVI_CLK>,
3792   - <&clk IMX8QM_VPU_UART_CLK>;
3793   - clock-names = "clk_vpu_ddr", "clk_vpu_sys",
3794   - "clk_vpu_xuvi", "clk_vpu_uart";
3795   - assigned-clocks = <&clk IMX8QM_VPU_DDR_CLK>,
3796   - <&clk IMX8QM_VPU_SYS_CLK>,
3797   - <&clk IMX8QM_VPU_XUVI_CLK>,
3798   - <&clk IMX8QM_VPU_UART_CLK>;
3799   - assigned-clock-rates = <800000000>, <600000000>,
3800   - <600000000>, <80000000>;
3801   - power-domains = <&pd_vpu_dec>;
3802   - status = "disabled";
3803   - };
3804   -
3805   - acm: acm@59e00000 {
3806   - compatible = "nxp,imx8qm-acm";
3807   - reg = <0x0 0x59e00000 0x0 0x1D0000>;
3808   - status = "disabled";
3809   - };
3810   -
3811   - dsp: dsp@556e8000 {
3812   - compatible = "fsl,imx8qm-dsp";
3813   - reserved-region = <&dsp_reserved>;
3814   - reg = <0x0 0x556e8000 0x0 0x88000>;
3815   - clocks = <&clk IMX8QM_AUD_DSP_IPG>,
3816   - <&clk IMX8QM_AUD_OCRAM_IPG>,
3817   - <&clk IMX8QM_AUD_DSP_CORE_CLK>;
3818   - clock-names = "ipg", "ocram", "core";
3819   - fsl,dsp-firmware = "imx/dsp/hifi4.bin";
3820   - fixup-offset = <0x4000000>;
3821   - power-domains = <&pd_dsp>;
3822   - };
3823   -
3824   - esai0: esai@59010000 {
3825   - compatible = "fsl,imx8qm-esai";
3826   - reg = <0x0 0x59010000 0x0 0x10000>;
3827   - interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
3828   - clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>,
3829   - <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>,
3830   - <&clk IMX8QM_AUD_ESAI_0_IPG>,
3831   - <&clk IMX8QM_CLK_DUMMY>;
3832   - clock-names = "core", "extal", "fsys", "spba";
3833   - dmas = <&edma2 6 0 1>, <&edma2 7 0 0>;
3834   - dma-names = "rx", "tx";
3835   - power-domains = <&pd_esai0>;
3836   - status = "disabled";
3837   - };
3838   -
3839   - spdif0: spdif@59020000 {
3840   - compatible = "fsl,imx8qm-spdif";
3841   - reg = <0x0 0x59020000 0x0 0x10000>;
3842   - interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
3843   - <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
3844   - clocks = <&clk IMX8QM_AUD_SPDIF_0_GCLKW>, /* core */
3845   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */
3846   - <&clk IMX8QM_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
3847   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */
3848   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */
3849   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */
3850   - <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */
3851   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */
3852   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */
3853   - <&clk IMX8QM_CLK_DUMMY>; /* spba */
3854   - clock-names = "core", "rxtx0",
3855   - "rxtx1", "rxtx2",
3856   - "rxtx3", "rxtx4",
3857   - "rxtx5", "rxtx6",
3858   - "rxtx7", "spba";
3859   - dmas = <&edma2 8 0 5>, <&edma2 9 0 4>;
3860   - dma-names = "rx", "tx";
3861   - power-domains = <&pd_spdif0>;
3862   - status = "disabled";
3863   - };
3864   -
3865   - spdif1: spdif@59030000 {
3866   - compatible = "fsl,imx8qm-spdif";
3867   - reg = <0x0 0x59030000 0x0 0x10000>;
3868   - interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
3869   - <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
3870   - clocks = <&clk IMX8QM_AUD_SPDIF_1_GCLKW>, /* core */
3871   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */
3872   - <&clk IMX8QM_AUD_SPDIF_1_TX_CLK>, /* rxtx1 */
3873   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */
3874   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */
3875   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */
3876   - <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */
3877   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */
3878   - <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */
3879   - <&clk IMX8QM_CLK_DUMMY>; /* spba */
3880   - clock-names = "core", "rxtx0",
3881   - "rxtx1", "rxtx2",
3882   - "rxtx3", "rxtx4",
3883   - "rxtx5", "rxtx6",
3884   - "rxtx7", "spba";
3885   - dmas = <&edma2 10 0 5>, <&edma2 11 0 4>;
3886   - dma-names = "rx", "tx";
3887   - power-domains = <&pd_spdif1>;
3888   - status = "disabled";
3889   - };
3890   -
3891   - sai1: sai@59050000 {
3892   - compatible = "fsl,imx8qm-sai";
3893   - reg = <0x0 0x59050000 0x0 0x10000>;
3894   - interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
3895   - clocks = <&clk IMX8QM_AUD_SAI_1_IPG>,
3896   - <&clk IMX8QM_CLK_DUMMY>,
3897   - <&clk IMX8QM_AUD_SAI_1_MCLK>,
3898   - <&clk IMX8QM_CLK_DUMMY>,
3899   - <&clk IMX8QM_CLK_DUMMY>;
3900   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3901   - dma-names = "rx", "tx";
3902   - dmas = <&edma2 14 0 1>, <&edma2 15 0 0>;
3903   - status = "disabled";
3904   - power-domains = <&pd_sai1>;
3905   - };
3906   -
3907   -
3908   - sai0: sai@59040000 {
3909   - compatible = "fsl,imx8qm-sai";
3910   - reg = <0x0 0x59040000 0x0 0x10000>;
3911   - interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
3912   - clocks = <&clk IMX8QM_AUD_SAI_0_IPG>,
3913   - <&clk IMX8QM_CLK_DUMMY>,
3914   - <&clk IMX8QM_AUD_SAI_0_MCLK>,
3915   - <&clk IMX8QM_CLK_DUMMY>,
3916   - <&clk IMX8QM_CLK_DUMMY>;
3917   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3918   - dma-names = "rx", "tx";
3919   - dmas = <&edma2 12 0 1>, <&edma2 13 0 0>;
3920   - status = "disabled";
3921   - power-domains = <&pd_sai0>;
3922   - };
3923   -
3924   - sai2: sai@59060000 {
3925   - compatible = "fsl,imx8qm-sai";
3926   - reg = <0x0 0x59060000 0x0 0x10000>;
3927   - interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
3928   - clocks = <&clk IMX8QM_AUD_SAI_2_IPG>,
3929   - <&clk IMX8QM_CLK_DUMMY>,
3930   - <&clk IMX8QM_AUD_SAI_2_MCLK>,
3931   - <&clk IMX8QM_CLK_DUMMY>,
3932   - <&clk IMX8QM_CLK_DUMMY>;
3933   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3934   - dma-names = "rx";
3935   - dmas = <&edma2 16 0 1>;
3936   - status = "disabled";
3937   - power-domains = <&pd_sai2>;
3938   - };
3939   -
3940   - sai3: sai@59070000 {
3941   - compatible = "fsl,imx8qm-sai";
3942   - reg = <0x0 0x59070000 0x0 0x10000>;
3943   - interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
3944   - clocks = <&clk IMX8QM_AUD_SAI_3_IPG>,
3945   - <&clk IMX8QM_CLK_DUMMY>,
3946   - <&clk IMX8QM_AUD_SAI_3_MCLK>,
3947   - <&clk IMX8QM_CLK_DUMMY>,
3948   - <&clk IMX8QM_CLK_DUMMY>;
3949   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3950   - dma-names = "rx";
3951   - dmas = <&edma2 17 0 1>;
3952   - status = "disabled";
3953   - power-domains = <&pd_sai3>;
3954   - };
3955   -
3956   - sai_hdmi_rx: sai@59080000 {
3957   - compatible = "fsl,imx8qm-sai";
3958   - reg = <0x0 0x59080000 0x0 0x10000>;
3959   - interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
3960   - clocks = <&clk IMX8QM_AUD_SAI_HDMIRX0_IPG>,
3961   - <&clk IMX8QM_CLK_DUMMY>,
3962   - <&clk IMX8QM_AUD_SAI_HDMIRX0_MCLK>,
3963   - <&clk IMX8QM_CLK_DUMMY>,
3964   - <&clk IMX8QM_CLK_DUMMY>;
3965   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3966   - dma-names = "rx";
3967   - dmas = <&edma2 18 0 1>;
3968   - fsl,dataline = <0 0xf 0x0>;
3969   - status = "disabled";
3970   - power-domains = <&pd_sai4>;
3971   - };
3972   -
3973   - sai_hdmi_tx: sai@59090000 {
3974   - compatible = "fsl,imx8qm-sai";
3975   - reg = <0x0 0x59090000 0x0 0x10000>;
3976   - interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
3977   - clocks = <&clk IMX8QM_AUD_SAI_HDMITX0_IPG>,
3978   - <&clk IMX8QM_CLK_DUMMY>,
3979   - <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>,
3980   - <&clk IMX8QM_CLK_DUMMY>,
3981   - <&clk IMX8QM_CLK_DUMMY>;
3982   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3983   - dma-names = "tx";
3984   - dmas = <&edma2 19 0 0>;
3985   - fsl,dataline = <0 0x0 0xf>;
3986   - status = "disabled";
3987   - power-domains = <&pd_sai5>;
3988   - };
3989   -
3990   - esai1: esai@59810000 {
3991   - compatible = "fsl,imx8qm-esai";
3992   - reg = <0x0 0x59810000 0x0 0x10000>;
3993   - interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
3994   - clocks = <&clk IMX8QM_AUD_ESAI_1_IPG>,
3995   - <&clk IMX8QM_AUD_ESAI_1_EXTAL_IPG>,
3996   - <&clk IMX8QM_AUD_ESAI_1_IPG>,
3997   - <&clk IMX8QM_CLK_DUMMY>;
3998   - clock-names = "core", "extal", "fsys", "spba";
3999   - dmas = <&edma3 6 0 1>, <&edma3 7 0 0>;
4000   - dma-names = "rx", "tx";
4001   - status = "disabled";
4002   - power-domains = <&pd_esai1>;
4003   - };
4004   -
4005   - sai6: sai@59820000 {
4006   - compatible = "fsl,imx8qm-sai";
4007   - reg = <0x0 0x59820000 0x0 0x10000>;
4008   - interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
4009   - clocks = <&clk IMX8QM_AUD_SAI_6_IPG>,
4010   - <&clk IMX8QM_CLK_DUMMY>,
4011   - <&clk IMX8QM_AUD_SAI_6_MCLK>,
4012   - <&clk IMX8QM_CLK_DUMMY>,
4013   - <&clk IMX8QM_CLK_DUMMY>;
4014   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
4015   - dma-names = "rx", "tx";
4016   - dmas = <&edma3 8 0 1>, <&edma3 9 0 0>;
4017   - status = "disabled";
4018   - power-domains = <&pd_sai6>;
4019   - };
4020   -
4021   - sai7: sai@59830000 {
4022   - compatible = "fsl,imx8qm-sai";
4023   - reg = <0x0 0x59830000 0x0 0x10000>;
4024   - interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
4025   - clocks = <&clk IMX8QM_AUD_SAI_7_IPG>,
4026   - <&clk IMX8QM_CLK_DUMMY>,
4027   - <&clk IMX8QM_AUD_SAI_7_MCLK>,
4028   - <&clk IMX8QM_CLK_DUMMY>,
4029   - <&clk IMX8QM_CLK_DUMMY>;
4030   - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
4031   - dma-names = "tx";
4032   - dmas = <&edma3 10 0 0>;
4033   - status = "disabled";
4034   - power-domains = <&pd_sai7>;
4035   - };
4036   -
4037   - amix: amix@59840000 {
4038   - compatible = "fsl,imx8qm-amix";
4039   - reg = <0x0 0x59840000 0x0 0x10000>;
4040   - clocks = <&clk IMX8QM_AUD_AMIX_IPG>;
4041   - clock-names = "ipg";
4042   - power-domains = <&pd_amix>;
4043   - status = "disabled";
4044   - };
4045   -
4046   - asrc0: asrc@59000000 {
4047   - compatible = "fsl,imx8qm-asrc0";
4048   - reg = <0x0 0x59000000 0x0 0x10000>;
4049   - interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4050   - <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
4051   - clocks = <&clk IMX8QM_AUD_ASRC_0_IPG>,
4052   - <&clk IMX8QM_AUD_ASRC_0_MEM>,
4053   - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
4054   - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
4055   - <&clk IMX8QM_ACM_AUD_CLK0_SEL>,
4056   - <&clk IMX8QM_ACM_AUD_CLK1_SEL>,
4057   - <&clk IMX8QM_CLK_DUMMY>,
4058   - <&clk IMX8QM_CLK_DUMMY>,
4059   - <&clk IMX8QM_CLK_DUMMY>,
4060   - <&clk IMX8QM_CLK_DUMMY>,
4061   - <&clk IMX8QM_CLK_DUMMY>,
4062   - <&clk IMX8QM_CLK_DUMMY>,
4063   - <&clk IMX8QM_CLK_DUMMY>,
4064   - <&clk IMX8QM_CLK_DUMMY>,
4065   - <&clk IMX8QM_CLK_DUMMY>,
4066   - <&clk IMX8QM_CLK_DUMMY>,
4067   - <&clk IMX8QM_CLK_DUMMY>,
4068   - <&clk IMX8QM_CLK_DUMMY>,
4069   - <&clk IMX8QM_CLK_DUMMY>;
4070   - clock-names = "ipg", "mem",
4071   - "asrck_0", "asrck_1", "asrck_2", "asrck_3",
4072   - "asrck_4", "asrck_5", "asrck_6", "asrck_7",
4073   - "asrck_8", "asrck_9", "asrck_a", "asrck_b",
4074   - "asrck_c", "asrck_d", "asrck_e", "asrck_f",
4075   - "spba";
4076   - dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>,
4077   - <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>;
4078   - dma-names = "rxa", "rxb", "rxc",
4079   - "txa", "txb", "txc";
4080   - fsl,asrc-rate = <8000>;
4081   - fsl,asrc-width = <16>;
4082   - power-domains = <&pd_asrc0>;
4083   - status = "disabled";
4084   - };
4085   -
4086   - asrc1: asrc@59800000 {
4087   - compatible = "fsl,imx8qm-asrc1";
4088   - reg = <0x0 0x59800000 0x0 0x10000>;
4089   - interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
4090   - <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
4091   - clocks = <&clk IMX8QM_AUD_ASRC_1_IPG>,
4092   - <&clk IMX8QM_AUD_ASRC_1_MEM>,
4093   - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
4094   - <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
4095   - <&clk IMX8QM_ACM_AUD_CLK0_SEL>,
4096   - <&clk IMX8QM_ACM_AUD_CLK1_SEL>,
4097   - <&clk IMX8QM_CLK_DUMMY>,
4098   - <&clk IMX8QM_CLK_DUMMY>,
4099   - <&clk IMX8QM_CLK_DUMMY>,
4100   - <&clk IMX8QM_CLK_DUMMY>,
4101   - <&clk IMX8QM_CLK_DUMMY>,
4102   - <&clk IMX8QM_CLK_DUMMY>,
4103   - <&clk IMX8QM_CLK_DUMMY>,
4104   - <&clk IMX8QM_CLK_DUMMY>,
4105   - <&clk IMX8QM_CLK_DUMMY>,
4106   - <&clk IMX8QM_CLK_DUMMY>,
4107   - <&clk IMX8QM_CLK_DUMMY>,
4108   - <&clk IMX8QM_CLK_DUMMY>,
4109   - <&clk IMX8QM_CLK_DUMMY>;
4110   - clock-names = "ipg", "mem",
4111   - "asrck_0", "asrck_1", "asrck_2", "asrck_3",
4112   - "asrck_4", "asrck_5", "asrck_6", "asrck_7",
4113   - "asrck_8", "asrck_9", "asrck_a", "asrck_b",
4114   - "asrck_c", "asrck_d", "asrck_e", "asrck_f",
4115   - "spba";
4116   - dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>,
4117   - <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>;
4118   - dma-names = "rxa", "rxb", "rxc",
4119   - "txa", "txb", "txc";
4120   - fsl,asrc-rate = <8000>;
4121   - fsl,asrc-width = <16>;
4122   - power-domains = <&pd_asrc1>;
4123   - status = "disabled";
4124   - };
4125   -
4126   - mqs: mqs@59850000 {
4127   - compatible = "fsl,imx8qm-mqs";
4128   - reg = <0x0 0x59850000 0x0 0x10000>;
4129   - clocks = <&clk IMX8QM_AUD_MQS_IPG>,
4130   - <&clk IMX8QM_AUD_MQS_HMCLK>;
4131   - clock-names = "core", "mclk";
4132   - power-domains = <&pd_mqs0>;
4133   - status = "disabled";
4134   - };
4135   -
4136 2127 flexspi0: flexspi@05d120000 {
4137 2128 #address-cells = <1>;
4138 2129 #size-cells = <0>;
... ... @@ -4275,46 +2266,6 @@
4275 2266 hsio = <&hsio>;
4276 2267 power-domains = <&pd_sata0>;
4277 2268 iommus = <&smmu 0x13 0x7f80>;
4278   - status = "disabled";
4279   - };
4280   -
4281   - intmux_cm40: intmux@37400000 {
4282   - compatible = "nxp,imx-intmux";
4283   - reg = <0x0 0x37400000 0x0 0x1000>;
4284   - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
4285   - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
4286   - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
4287   - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
4288   - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
4289   - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
4290   - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
4291   - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
4292   - interrupt-controller;
4293   - interrupt-parent = <&gic>;
4294   - #interrupt-cells = <2>;
4295   - clocks = <&clk IMX8QM_CM40_IPG_CLK>;
4296   - clock-names = "ipg";
4297   - power-domains = <&pd_cm40_intmux>;
4298   - status = "disabled";
4299   - };
4300   -
4301   - intmux_cm41: intmux@3b400000 {
4302   - compatible = "nxp,imx-intmux";
4303   - reg = <0x0 0x3b400000 0x0 0x1000>;
4304   - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
4305   - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
4306   - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
4307   - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
4308   - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
4309   - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
4310   - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4311   - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
4312   - interrupt-controller;
4313   - interrupt-parent = <&gic>;
4314   - #interrupt-cells = <2>;
4315   - clocks = <&clk IMX8QM_CM41_IPG_CLK>;
4316   - clock-names = "ipg";
4317   - power-domains = <&pd_cm41_intmux>;
4318 2269 status = "disabled";
4319 2270 };
4320 2271  
arch/arm/dts/fsl-imx8qm.dtsi
Diff comments   View file @ 6d20408
... ... @@ -22,22 +22,12 @@
22 22 #size-cells = <2>;
23 23  
24 24 aliases {
25   - csi0 = &mipi_csi_0;
26   - csi1 = &mipi_csi_1;
27 25 ethernet0 = &fec1;
28 26 ethernet1 = &fec2;
29 27 dsiphy0 = &mipi_dsi_phy1;
30 28 dsiphy1 = &mipi_dsi_phy2;
31 29 mipidsi0 = &mipi_dsi1;
32 30 mipidsi1 = &mipi_dsi2;
33   - isi0 = &isi_0;
34   - isi1 = &isi_1;
35   - isi2 = &isi_2;
36   - isi3 = &isi_3;
37   - isi4 = &isi_4;
38   - isi5 = &isi_5;
39   - isi6 = &isi_6;
40   - isi7 = &isi_7;
41 31 serial0 = &lpuart0;
42 32 serial1 = &lpuart1;
43 33 serial2 = &lpuart2;
... ... @@ -57,9 +47,6 @@
57 47 usb0 = &usbotg1;
58 48 usbphy0 = &usbphy1;
59 49 usb1 = &usbotg3;
60   - can0 = &flexcan1;
61   - can1 = &flexcan2;
62   - can2 = &flexcan3;
63 50 i2c0 = &i2c0;
64 51 i2c1 = &i2c1;
65 52 i2c2 = &i2c2;
... ... @@ -219,57 +206,6 @@
219 206 status = "okay";
220 207 };
221 208  
222   - vpu_decoder: vpu_decoder@2c000000 {
223   - compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
224   - boot-region = <&decoder_boot>;
225   - rpc-region = <&decoder_rpc>;
226   - reg = <0x0 0x2c000000 0x0 0x1000000>;
227   - reg-names = "vpu_regs";
228   - reg-csr = <0x2d080000>;
229   - power-domains = <&pd_vpu_dec>;
230   - status = "disabled";
231   - };
232   -
233   - vpu_encoder: vpu_encoder@2d000000 {
234   - compatible = "nxp,imx8qm-b0-vpuenc";
235   - #address-cells = <1>;
236   - #size-cells = <1>;
237   -
238   - boot-region = <&encoder_boot>;
239   - rpc-region = <&encoder_rpc>;
240   - reserved-region = <&encoder_reserved>;
241   - reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/
242   - <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
243   - reg-names = "vpu_regs";
244   - power-domains = <&pd_vpu_enc>;
245   - reg-rpc-system = <0x40000000>;
246   -
247   - resolution-max = <1920 1080>;
248   - fps-max = <120>;
249   - status = "disabled";
250   -
251   - core0@1020000 {
252   - compatible = "fsl,imx8-mu1-vpu-m0";
253   - reg = <0x1020000 0x20000>;
254   - reg-csr = <0x1090000 0x10000>;
255   - interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
256   - fsl,vpu_ap_mu_id = <17>;
257   - fw-buf-size = <0x200000>;
258   - rpc-buf-size = <0x80000>;
259   - print-buf-size = <0x80000>;
260   - };
261   - core1@1040000 {
262   - compatible = "fsl,imx8-mu2-vpu-m0";
263   - reg = <0x1040000 0x20000>;
264   - reg-csr = <0x10a0000 0x10000>;
265   - interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
266   - fsl,vpu_ap_mu_id = <18>;
267   - fw-buf-size = <0x200000>;
268   - rpc-buf-size = <0x80000>;
269   - print-buf-size = <0x80000>;
270   - };
271   - };
272   -
273 209 timer {
274 210 compatible = "arm,armv8-timer";
275 211 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
... ... @@ -349,17 +285,6 @@
349 285 clock-latency = <61036>;
350 286 #cooling-cells = <2>;
351 287 /delete-property/ cpu-idle-states;
352   -};
353   -
354   -
355   -&imx8_gpu_ss {/*<freq-kHz vol-uV>*/
356   - operating-points = <
357   -/*overdrive*/ 800000 0 /*The first tuple is for core clock frequency*/
358   - 1000000 0 /*The second tuple is for shader clock frequency*/
359   -/*nominal*/ 650000 0
360   - 700000 0
361   -/*underdrive*/ 400000 0 /*core/shader clock share the same frequency on underdrive mode*/
362   - >;
363 288 };
364 289  
365 290 &A53_1 {