ColdFire: Add M5253DEMO platform support for MCF5253

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

ColdFire: Add M5253DEMO platform support for MCF5253
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
TsiChung Liew · John Rigby
1 parent 80ba61fd82
Showing 9 changed files with 1077 additions and 0 deletions Side-by-side Diff
MAINTAINERS
MAKEALL
Makefile
board/freescale/m5253demo/Makefile
board/freescale/m5253demo/config.mk
board/freescale/m5253demo/flash.c
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253demo/u-boot.lds
include/configs/M5253DEMO.h
@@ -698,6 +698,7 @@
  
 	M52277EVB	mcf5227x
 	M5235EVB	mcf52x2
+	M5253DEMO	mcf52x2
 	M5329EVB	mcf532x
 	M5373EVB	mcf532x
 	M54455EVB	mcf5445x
@@ -694,6 +694,7 @@
 	M52277EVB		\
 	M5235EVB		\
 	M5249EVB		\
+	M5253DEMO		\
 	M5253EVBE		\
 	M5271EVB		\
 	M5272C3			\
@@ -1851,6 +1851,9 @@
 M5249EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
  
+M5253DEMO_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253demo freescale
+
 M5253EVBE_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
  
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFF800000
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/immap.h>
+
+#ifndef CFG_FLASH_CFI
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x5555
+#define FLASH_CYCLE2    0x2aaa
+
+#define SYNC			__asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int write_word(flash_info_t * info, FPWV * dest, u16 data);
+void inline spin_wheel(void);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+	ulong size = 0;
+	ulong fbase = 0;
+
+	fbase = (ulong) CFG_FLASH_BASE;
+	flash_get_size((FPWV *) fbase, &flash_info[0]);
+	flash_get_offsets((ulong) fbase, &flash_info[0]);
+	fbase += flash_info[0].size;
+	size += flash_info[0].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+int flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int j, k;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+
+		info->start[0] = base;
+		for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) {
+			info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ;
+			info->protect[k] = 0;
+		}
+	}
+
+	return ERR_OK;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_SST6401B:
+		printf("SST39VF6401B\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	if (info->size > 0x100000) {
+		int remainder;
+
+		printf("  Size: %ld", info->size >> 20);
+
+		remainder = (info->size % 0x100000);
+		if (remainder) {
+			remainder >>= 10;
+			remainder = (int)((float)
+					  (((float)remainder / (float)1024) *
+					   10000));
+			printf(".%d ", remainder);
+		}
+
+		printf("MB in %d Sectors\n", info->sector_count);
+	} else
+		printf("  Size: %ld KB in %d Sectors\n",
+		       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	u16 value;
+
+	addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPWV) 0x00550055;	/* for Atmel, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPWV) 0x00900090;	/* selects Intel or Atmel */
+
+	switch (addr[0] & 0xffff) {
+	case (u8) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		value = addr[1];
+		break;
+	default:
+		printf("Unknown Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+
+		*addr = (FPW) 0x00F000F0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+	case (u16) SST_ID_xF6401B:
+		info->flash_id += FLASH_SST6401B;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	info->sector_count = 0;
+	info->size = 0;
+	info->sector_count = CFG_SST_SECT;
+	info->size = CFG_SST_SECT * CFG_SST_SECTSZ;
+
+	/* reset ID mode */
+	*addr = (FPWV) 0x00F000F0;
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	return (info->size);
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect, count;
+	ulong type, start, last;
+	int rcode = 0, flashtype = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+
+	switch (type) {
+	case FLASH_MAN_SST:
+		flashtype = 1;
+		break;
+	default:
+		type = (info->flash_id & FLASH_VENDMASK);
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	flag = disable_interrupts();
+
+	start = get_timer(0);
+	last = start;
+
+	if ((s_last - s_first) == (CFG_SST_SECT - 1)) {
+		if (prot == 0) {
+			addr = (FPWV *) info->start[0];
+
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			addr[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+			addr[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+			addr[FLASH_CYCLE2] = 0x0055;	/* unlock */
+			*addr = 0x0030;	/* erase chip */
+
+			count = 0;
+			start = get_timer(0);
+
+			while ((*addr & 0x0080) != 0x0080) {
+				if (count++ > 0x10000) {
+					spin_wheel();
+					count = 0;
+				}
+
+				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = 0x00F0;	/* reset to read mode */
+
+					return 1;
+				}
+			}
+
+			*addr = 0x00F0;	/* reset to read mode */
+
+			printf("\b. done\n");
+
+			if (flag)
+				enable_interrupts();
+
+			return 0;
+		} else if (prot == CFG_SST_SECT) {
+			return 1;
+		}
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			addr = (FPWV *) (info->start[sect]);
+
+			printf(".");
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			switch (flashtype) {
+			case 1:
+				{
+					FPWV *base;	/* first address in bank */
+
+					flag = disable_interrupts();
+
+					base = (FPWV *) (CFG_FLASH_BASE);	/* First sector */
+
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					base[FLASH_CYCLE1] = 0x0080;	/* erase mode */
+					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+					*addr = 0x0050;	/* erase sector */
+
+					if (flag)
+						enable_interrupts();
+
+					while ((*addr & 0x0080) != 0x0080) {
+						if (get_timer(start) >
+						    CFG_FLASH_ERASE_TOUT) {
+							printf("Timeout\n");
+							*addr = 0x00F0;	/* reset to read mode */
+
+							rcode = 1;
+							break;
+						}
+					}
+
+					*addr = 0x00F0;	/* reset to read mode */
+					break;
+				}
+			}	/* switch (flashtype) */
+		}
+	}
+	printf(" done\n");
+
+	if (flag)
+		enable_interrupts();
+
+	return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, count;
+	u16 data;
+	int rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	/* get lower word aligned address */
+	wp = addr;
+	port_width = sizeof(FPW);
+
+	/* handle unaligned start bytes */
+	if (wp & 1) {
+		data = *((FPWV *) wp);
+		data = (data << 8) | *src;
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		cnt -= 1;
+		src++;
+	}
+
+	while (cnt >= 2) {
+		/*
+		 * handle word aligned part
+		 */
+		count = 0;
+		data = *((FPWV *) src);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp += 2;
+		src += 2;
+		cnt -= 2;
+
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+	/* handle word aligned part */
+	if (cnt) {
+		/* handle word aligned part */
+		count = 0;
+		data = *((FPWV *) wp);
+
+		data = (data & 0x00FF) | (*src << 8);
+
+		if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+			return (rc);
+
+		wp++;
+		src++;
+		cnt -= 1;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash
+ * A word is 16 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word(flash_info_t * info, FPWV * dest, u16 data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & (u8) data) != (u8) data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CFG_FLASH_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (u8) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (u8) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (u8) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (u8) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	*dest++ = (u8) 0x00F000F0;	/* reset bank */
+
+	return (res);
+}
+
+void inline spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+#endif
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale MCF5253 DEMO\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize = 0;
+
+	/*
+	 * Check to see if the SDRAM has already been initialized
+	 * by a run control tool
+	 */
+	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+		u32 RC, temp;
+
+		RC = (CFG_CLK / 1000000) >> 1;
+		RC = (RC * 15) >> 4;
+
+		/* Initialize DRAM Control Register: DCR */
+		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+		__asm__("nop");
+
+		/* Initialize DMR0 */
+		dramsize = (CFG_SDRAM_SIZE << 20);
+		temp = (dramsize - 1) & 0xFFFC0000;
+		mbar_writeLong(MCFSIM_DMR0, temp | 1);
+		__asm__("nop");
+
+		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+		__asm__("nop");
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+		__asm__("nop");
+
+		/* Set RE bit in DACR */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
+		__asm__("nop");
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		udelay(500);
+
+		/* Finish the configuration by issuing the MRS */
+		mbar_writeLong(MCFSIM_DACR0,
+			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
+		__asm__("nop");
+
+		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+	}
+
+	return dramsize;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+	return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+	long period;
+	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
+	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
+	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
+	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
+	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
+	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
+	};
+
+	if (idereset) {
+		ata->cr = 0;	/* control reset */
+		udelay(100);
+	} else {
+		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
+
+		/*ata->ton = CALC_TIMING (180); */
+		ata->t1 = CALC_TIMING(piotms[2][0]);
+		ata->t2w = CALC_TIMING(piotms[2][1]);
+		ata->t2r = CALC_TIMING(piotms[2][1]);
+		ata->ta = CALC_TIMING(piotms[2][8]);
+		ata->trd = CALC_TIMING(piotms[2][7]);
+		ata->t4 = CALC_TIMING(piotms[2][3]);
+		ata->t9 = CALC_TIMING(piotms[2][6]);
+
+		ata->cr = 0x40;	/* IORDY enable */
+		udelay(2000);
+		ata->cr |= 0x01;	/* IORDY enable */
+	}
+}
+#endif				/* CONFIG_CMD_IDE */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253DEMO_H
+#define _M5253DEMO_H
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5253		/* define processor type */
+#define CONFIG_M5253DEMO	/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+#define CONFIG_BOOTDELAY	5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CFG_ENV_OFFSET		0x4000
+#	define CFG_ENV_SECT_SIZE	0x1000
+#	define CFG_ENV_IS_IN_FLASH	1
+#else
+#	define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#	define CFG_ENV_SECT_SIZE	0x1000
+#	define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_PING
+
+#ifdef CONFIG_CMD_IDE
+/* ATA */
+#	define CONFIG_DOS_PARTITION
+#	define CONFIG_MAC_PARTITION
+#	define CONFIG_IDE_RESET		1
+#	define CONFIG_IDE_PREINIT	1
+#	define CONFIG_ATAPI
+#	undef CONFIG_LBA48
+
+#	define CFG_IDE_MAXBUS		1
+#	define CFG_IDE_MAXDEVICE	2
+
+#	define CFG_ATA_BASE_ADDR	(CFG_MBAR2 + 0x800)
+#	define CFG_ATA_IDE0_OFFSET	0
+
+#	define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#	define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#	define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#	define CFG_ATA_STRIDE		4	/* Interval between registers */
+#	define _IO_BASE			0
+#endif
+
+#define CONFIG_DRIVER_DM9000
+#ifdef CONFIG_DRIVER_DM9000
+#	define CONFIG_DM9000_BASE	((CFG_CSAR1 << 16) | 0x300)
+#	define DM9000_IO		CONFIG_DM9000_BASE
+#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
+#	undef CONFIG_DM9000_DEBUG
+
+#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR		10.82.121.249
+#	define CONFIG_NETMASK		255.255.252.0
+#	define CONFIG_SERVERIP		10.82.120.80
+#	define CONFIG_GATEWAYIP		10.82.123.254
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#	define CONFIG_EXTRA_ENV_SETTINGS		\
+		"netdev=eth0\0"				\
+		"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0"	\
+		"loadaddr=10000\0"			\
+		"u-boot=u-boot.bin\0"			\
+		"load=tftp ${loadaddr) ${u-boot}\0"	\
+		"upd=run load; run prog\0"		\
+		"prog=prot off 0 2ffff;"	\
+		"era 0 2ffff;"			\
+		"cp.b ${loadaddr} 0 ${filesize};"	\
+		"save\0"				\
+		""
+#endif
+
+#define CONFIG_HOSTNAME		M5253DEMO
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#	define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR		0x00100000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+
+#undef CFG_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+#	define CFG_PLLCR	0x1243E054
+#	define CFG_CLK		140000000
+#else
+#	define CFG_PLLCR	0x135a4140
+#	define CFG_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CFG_MONITOR_BASE	0x20000
+#else
+#	define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x40000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE		(CFG_CSAR0 << 16)
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	1000
+
+#define FLASH_SST6401B		0x200
+#define SST_ID_xF6401B		0x236D236D
+
+#undef CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+/*
+ * Unable to use CFI driver, due to incompatible sector erase command by SST.
+ * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
+ * 0x30 is block erase in SST
+ */
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_SIZE		0x800000
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_FLASH_CFI_LEGACY
+#else
+#	define CFG_SST_SECT		2048
+#	define CFG_SST_SECTSZ		0x1000
+#	define CFG_FLASH_WRITE_TOUT	500
+#endif
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE	16
+
+/* Port configuration */
+#define CFG_FECI2C		0xF0
+
+#define CFG_CSAR0		0xFF80
+#define CFG_CSMR0		0x007F0021
+#define CFG_CSCR0		0x1D80
+
+#define CFG_CSAR1               0xE000
+#define CFG_CSMR1               0x00000001
+#define CFG_CSCR1               0x3DD8
+
+#define CFG_CSAR2		0
+#define CFG_CSMR2		0
+#define CFG_CSCR2		0
+
+#define CFG_CSAR3		0
+#define CFG_CSMR3		0
+#define CFG_CSCR3		0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CFG_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253DEMO_H */
...	...	@@ -698,6 +698,7 @@
698	698
699	699	M52277EVB mcf5227x
700	700	M5235EVB mcf52x2
	701	+ M5253DEMO mcf52x2
701	702	M5329EVB mcf532x
702	703	M5373EVB mcf532x
703	704	M54455EVB mcf5445x
...	...	@@ -694,6 +694,7 @@
694	694	M52277EVB \
695	695	M5235EVB \
696	696	M5249EVB \
	697	+ M5253DEMO \
697	698	M5253EVBE \
698	699	M5271EVB \
699	700	M5272C3 \
...	...	@@ -1851,6 +1851,9 @@
1851	1851	M5249EVB_config : unconfig
1852	1852	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
1853	1853
	1854	+M5253DEMO_config : unconfig
	1855	+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253demo freescale
	1856	+
1854	1857	M5253EVBE_config : unconfig
1855	1858	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
1856	1859
	1	+#
	2	+# (C) Copyright 2000-2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = $(obj)lib$(BOARD).a
	27	+
	28	+COBJS = $(BOARD).o flash.o
	29	+
	30	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	31	+OBJS := $(addprefix $(obj),$(COBJS))
	32	+SOBJS := $(addprefix $(obj),$(SOBJS))
	33	+
	34	+$(LIB): $(obj).depend $(OBJS)
	35	+ $(AR) $(ARFLAGS) $@ $(OBJS)
	36	+
	37	+#########################################################################
	38	+
	39	+# defines $(obj).depend target
	40	+include $(SRCTREE)/rules.mk
	41	+
	42	+sinclude $(obj).depend
	43	+
	44	+#########################################################################
	1	+#
	2	+# (C) Copyright 2000-2003
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
	5	+#
	6	+# See file CREDITS for list of people who contributed to this
	7	+# project.
	8	+#
	9	+# This program is free software; you can redistribute it and/or
	10	+# modify it under the terms of the GNU General Public License as
	11	+# published by the Free Software Foundation; either version 2 of
	12	+# the License, or (at your option) any later version.
	13	+#
	14	+# This program is distributed in the hope that it will be useful,
	15	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+# GNU General Public License for more details.
	18	+#
	19	+# You should have received a copy of the GNU General Public License
	20	+# along with this program; if not, write to the Free Software
	21	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+# MA 02111-1307 USA
	23	+#
	24	+
	25	+TEXT_BASE = 0xFF800000
	1	+/*
	2	+ * (C) Copyright 2000-2003
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	6	+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+#include <common.h>
	28	+
	29	+#include <asm/immap.h>
	30	+
	31	+#ifndef CFG_FLASH_CFI
	32	+typedef unsigned short FLASH_PORT_WIDTH;
	33	+typedef volatile unsigned short FLASH_PORT_WIDTHV;
	34	+
	35	+#define FPW FLASH_PORT_WIDTH
	36	+#define FPWV FLASH_PORT_WIDTHV
	37	+
	38	+#define FLASH_CYCLE1 0x5555
	39	+#define FLASH_CYCLE2 0x2aaa
	40	+
	41	+#define SYNC __asm__("nop")
	42	+
	43	+/*-----------------------------------------------------------------------
	44	+ * Functions
	45	+ */
	46	+
	47	+ulong flash_get_size(FPWV * addr, flash_info_t * info);
	48	+int flash_get_offsets(ulong base, flash_info_t * info);
	49	+int write_word(flash_info_t * info, FPWV * dest, u16 data);
	50	+void inline spin_wheel(void);
	51	+
	52	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
	53	+
	54	+ulong flash_init(void)
	55	+{
	56	+ ulong size = 0;
	57	+ ulong fbase = 0;
	58	+
	59	+ fbase = (ulong) CFG_FLASH_BASE;
	60	+ flash_get_size((FPWV *) fbase, &flash_info[0]);
	61	+ flash_get_offsets((ulong) fbase, &flash_info[0]);
	62	+ fbase += flash_info[0].size;
	63	+ size += flash_info[0].size;
	64	+
	65	+ /* Protect monitor and environment sectors */
	66	+ flash_protect(FLAG_PROTECT_SET,
	67	+ CFG_MONITOR_BASE,
	68	+ CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
	69	+
	70	+ return size;
	71	+}
	72	+
	73	+int flash_get_offsets(ulong base, flash_info_t * info)
	74	+{
	75	+ int j, k;
	76	+
	77	+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
	78	+
	79	+ info->start[0] = base;
	80	+ for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) {
	81	+ info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ;
	82	+ info->protect[k] = 0;
	83	+ }
	84	+ }
	85	+
	86	+ return ERR_OK;
	87	+}
	88	+
	89	+void flash_print_info(flash_info_t * info)
	90	+{
	91	+ int i;
	92	+
	93	+ switch (info->flash_id & FLASH_VENDMASK) {
	94	+ case FLASH_MAN_SST:
	95	+ printf("SST ");
	96	+ break;
	97	+ default:
	98	+ printf("Unknown Vendor ");
	99	+ break;
	100	+ }
	101	+
	102	+ switch (info->flash_id & FLASH_TYPEMASK) {
	103	+ case FLASH_SST6401B:
	104	+ printf("SST39VF6401B\n");
	105	+ break;
	106	+ default:
	107	+ printf("Unknown Chip Type\n");
	108	+ return;
	109	+ }
	110	+
	111	+ if (info->size > 0x100000) {
	112	+ int remainder;
	113	+
	114	+ printf(" Size: %ld", info->size >> 20);
	115	+
	116	+ remainder = (info->size % 0x100000);
	117	+ if (remainder) {
	118	+ remainder >>= 10;
	119	+ remainder = (int)((float)
	120	+ (((float)remainder / (float)1024) *
	121	+ 10000));
	122	+ printf(".%d ", remainder);
	123	+ }
	124	+
	125	+ printf("MB in %d Sectors\n", info->sector_count);
	126	+ } else
	127	+ printf(" Size: %ld KB in %d Sectors\n",
	128	+ info->size >> 10, info->sector_count);
	129	+
	130	+ printf(" Sector Start Addresses:");
	131	+ for (i = 0; i < info->sector_count; ++i) {
	132	+ if ((i % 5) == 0)
	133	+ printf("\n ");
	134	+ printf(" %08lX%s",
	135	+ info->start[i], info->protect[i] ? " (RO)" : " ");
	136	+ }
	137	+ printf("\n");
	138	+}
	139	+
	140	+/*
	141	+ * The following code cannot be run from FLASH!
	142	+ */
	143	+ulong flash_get_size(FPWV * addr, flash_info_t * info)
	144	+{
	145	+ u16 value;
	146	+
	147	+ addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
	148	+ addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
	149	+ addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
	150	+
	151	+ switch (addr[0] & 0xffff) {
	152	+ case (u8) SST_MANUFACT:
	153	+ info->flash_id = FLASH_MAN_SST;
	154	+ value = addr[1];
	155	+ break;
	156	+ default:
	157	+ printf("Unknown Flash\n");
	158	+ info->flash_id = FLASH_UNKNOWN;
	159	+ info->sector_count = 0;
	160	+ info->size = 0;
	161	+
	162	+ *addr = (FPW) 0x00F000F0;
	163	+ return (0); /* no or unknown flash */
	164	+ }
	165	+
	166	+ switch (value) {
	167	+ case (u16) SST_ID_xF6401B:
	168	+ info->flash_id += FLASH_SST6401B;
	169	+ break;
	170	+ default:
	171	+ info->flash_id = FLASH_UNKNOWN;
	172	+ break;
	173	+ }
	174	+
	175	+ info->sector_count = 0;
	176	+ info->size = 0;
	177	+ info->sector_count = CFG_SST_SECT;
	178	+ info->size = CFG_SST_SECT * CFG_SST_SECTSZ;
	179	+
	180	+ /* reset ID mode */
	181	+ *addr = (FPWV) 0x00F000F0;
	182	+
	183	+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
	184	+ printf(" ERROR: sector count %d > max (%d) \n",
	185	+ info->sector_count, CFG_MAX_FLASH_SECT);
	186	+ info->sector_count = CFG_MAX_FLASH_SECT;
	187	+ }
	188	+
	189	+ return (info->size);
	190	+}
	191	+
	192	+int flash_erase(flash_info_t * info, int s_first, int s_last)
	193	+{
	194	+ FPWV *addr;
	195	+ int flag, prot, sect, count;
	196	+ ulong type, start, last;
	197	+ int rcode = 0, flashtype = 0;
	198	+
	199	+ if ((s_first < 0) \|\| (s_first > s_last)) {
	200	+ if (info->flash_id == FLASH_UNKNOWN)
	201	+ printf("- missing\n");
	202	+ else
	203	+ printf("- no sectors to erase\n");
	204	+ return 1;
	205	+ }
	206	+
	207	+ type = (info->flash_id & FLASH_VENDMASK);
	208	+
	209	+ switch (type) {
	210	+ case FLASH_MAN_SST:
	211	+ flashtype = 1;
	212	+ break;
	213	+ default:
	214	+ type = (info->flash_id & FLASH_VENDMASK);
	215	+ printf("Can't erase unknown flash type %08lx - aborted\n",
	216	+ info->flash_id);
	217	+ return 1;
	218	+ }
	219	+
	220	+ prot = 0;
	221	+ for (sect = s_first; sect <= s_last; ++sect) {
	222	+ if (info->protect[sect]) {
	223	+ prot++;
	224	+ }
	225	+ }
	226	+
	227	+ if (prot)
	228	+ printf("- Warning: %d protected sectors will not be erased!\n",
	229	+ prot);
	230	+ else
	231	+ printf("\n");
	232	+
	233	+ flag = disable_interrupts();
	234	+
	235	+ start = get_timer(0);
	236	+ last = start;
	237	+
	238	+ if ((s_last - s_first) == (CFG_SST_SECT - 1)) {
	239	+ if (prot == 0) {
	240	+ addr = (FPWV *) info->start[0];
	241	+
	242	+ addr[FLASH_CYCLE1] = 0x00AA; /* unlock */
	243	+ addr[FLASH_CYCLE2] = 0x0055; /* unlock */
	244	+ addr[FLASH_CYCLE1] = 0x0080; /* erase mode */
	245	+ addr[FLASH_CYCLE1] = 0x00AA; /* unlock */
	246	+ addr[FLASH_CYCLE2] = 0x0055; /* unlock */
	247	+ addr = 0x0030; / erase chip */
	248	+
	249	+ count = 0;
	250	+ start = get_timer(0);
	251	+
	252	+ while ((*addr & 0x0080) != 0x0080) {
	253	+ if (count++ > 0x10000) {
	254	+ spin_wheel();
	255	+ count = 0;
	256	+ }
	257	+
	258	+ if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
	259	+ printf("Timeout\n");
	260	+ addr = 0x00F0; / reset to read mode */
	261	+
	262	+ return 1;
	263	+ }
	264	+ }
	265	+
	266	+ addr = 0x00F0; / reset to read mode */
	267	+
	268	+ printf("\b. done\n");
	269	+
	270	+ if (flag)
	271	+ enable_interrupts();
	272	+
	273	+ return 0;
	274	+ } else if (prot == CFG_SST_SECT) {
	275	+ return 1;
	276	+ }
	277	+ }
	278	+
	279	+ /* Start erase on unprotected sectors */
	280	+ for (sect = s_first; sect <= s_last; sect++) {
	281	+ if (info->protect[sect] == 0) { /* not protected */
	282	+
	283	+ addr = (FPWV *) (info->start[sect]);
	284	+
	285	+ printf(".");
	286	+
	287	+ /* arm simple, non interrupt dependent timer */
	288	+ start = get_timer(0);
	289	+
	290	+ switch (flashtype) {
	291	+ case 1:
	292	+ {
	293	+ FPWV base; / first address in bank */
	294	+
	295	+ flag = disable_interrupts();
	296	+
	297	+ base = (FPWV ) (CFG_FLASH_BASE); / First sector */
	298	+
	299	+ base[FLASH_CYCLE1] = 0x00AA; /* unlock */
	300	+ base[FLASH_CYCLE2] = 0x0055; /* unlock */
	301	+ base[FLASH_CYCLE1] = 0x0080; /* erase mode */
	302	+ base[FLASH_CYCLE1] = 0x00AA; /* unlock */
	303	+ base[FLASH_CYCLE2] = 0x0055; /* unlock */
	304	+ addr = 0x0050; / erase sector */
	305	+
	306	+ if (flag)
	307	+ enable_interrupts();
	308	+
	309	+ while ((*addr & 0x0080) != 0x0080) {
	310	+ if (get_timer(start) >
	311	+ CFG_FLASH_ERASE_TOUT) {
	312	+ printf("Timeout\n");
	313	+ addr = 0x00F0; / reset to read mode */
	314	+
	315	+ rcode = 1;
	316	+ break;
	317	+ }
	318	+ }
	319	+
	320	+ addr = 0x00F0; / reset to read mode */
	321	+ break;
	322	+ }
	323	+ } /* switch (flashtype) */
	324	+ }
	325	+ }
	326	+ printf(" done\n");
	327	+
	328	+ if (flag)
	329	+ enable_interrupts();
	330	+
	331	+ return rcode;
	332	+}
	333	+
	334	+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
	335	+{
	336	+ ulong wp, count;
	337	+ u16 data;
	338	+ int rc, port_width;
	339	+
	340	+ if (info->flash_id == FLASH_UNKNOWN)
	341	+ return 4;
	342	+
	343	+ /* get lower word aligned address */
	344	+ wp = addr;
	345	+ port_width = sizeof(FPW);
	346	+
	347	+ /* handle unaligned start bytes */
	348	+ if (wp & 1) {
	349	+ data = ((FPWV ) wp);
	350	+ data = (data << 8) \| *src;
	351	+
	352	+ if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
	353	+ return (rc);
	354	+
	355	+ wp++;
	356	+ cnt -= 1;
	357	+ src++;
	358	+ }
	359	+
	360	+ while (cnt >= 2) {
	361	+ /*
	362	+ * handle word aligned part
	363	+ */
	364	+ count = 0;
	365	+ data = ((FPWV ) src);
	366	+
	367	+ if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
	368	+ return (rc);
	369	+
	370	+ wp += 2;
	371	+ src += 2;
	372	+ cnt -= 2;
	373	+
	374	+ if (count++ > 0x800) {
	375	+ spin_wheel();
	376	+ count = 0;
	377	+ }
	378	+ }
	379	+ /* handle word aligned part */
	380	+ if (cnt) {
	381	+ /* handle word aligned part */
	382	+ count = 0;
	383	+ data = ((FPWV ) wp);
	384	+
	385	+ data = (data & 0x00FF) \| (*src << 8);
	386	+
	387	+ if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
	388	+ return (rc);
	389	+
	390	+ wp++;
	391	+ src++;
	392	+ cnt -= 1;
	393	+ if (count++ > 0x800) {
	394	+ spin_wheel();
	395	+ count = 0;
	396	+ }
	397	+ }
	398	+
	399	+ if (cnt == 0)
	400	+ return ERR_OK;
	401	+
	402	+ return ERR_OK;
	403	+}
	404	+
	405	+/*-----------------------------------------------------------------------
	406	+ * Write a word to Flash
	407	+ * A word is 16 bits, whichever the bus width of the flash bank
	408	+ * (not an individual chip) is.
	409	+ *
	410	+ * returns:
	411	+ * 0 - OK
	412	+ * 1 - write timeout
	413	+ * 2 - Flash not erased
	414	+ */
	415	+int write_word(flash_info_t * info, FPWV * dest, u16 data)
	416	+{
	417	+ ulong start;
	418	+ int flag;
	419	+ int res = 0; /* result, assume success */
	420	+ FPWV base; / first address in flash bank */
	421	+
	422	+ /* Check if Flash is (sufficiently) erased */
	423	+ if ((*dest & (u8) data) != (u8) data) {
	424	+ return (2);
	425	+ }
	426	+
	427	+ base = (FPWV *) (CFG_FLASH_BASE);
	428	+
	429	+ /* Disable interrupts which might cause a timeout here */
	430	+ flag = disable_interrupts();
	431	+
	432	+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
	433	+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
	434	+ base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
	435	+
	436	+ dest = data; / start programming the data */
	437	+
	438	+ /* re-enable interrupts if necessary */
	439	+ if (flag)
	440	+ enable_interrupts();
	441	+
	442	+ start = get_timer(0);
	443	+
	444	+ /* data polling for D7 */
	445	+ while (res == 0
	446	+ && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
	447	+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
	448	+ dest = (u8) 0x00F000F0; / reset bank */
	449	+ res = 1;
	450	+ }
	451	+ }
	452	+
	453	+ dest++ = (u8) 0x00F000F0; / reset bank */
	454	+
	455	+ return (res);
	456	+}
	457	+
	458	+void inline spin_wheel(void)
	459	+{
	460	+ static int p = 0;
	461	+ static char w[] = "\\/-";
	462	+
	463	+ printf("\010%c", w[p]);
	464	+ (++p == 3) ? (p = 0) : 0;
	465	+}
	466	+
	467	+#endif
	1	+/*
	2	+ * (C) Copyright 2000
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_ARCH(m68k)
	25	+/* Do we need any of these for elf?
	26	+ __DYNAMIC = 0; */
	27	+SECTIONS
	28	+{
	29	+ /* Read-only sections, merged into text segment: */
	30	+ . = + SIZEOF_HEADERS;
	31	+ .interp : { *(.interp) }
	32	+ .hash : { *(.hash) }
	33	+ .dynsym : { *(.dynsym) }
	34	+ .dynstr : { *(.dynstr) }
	35	+ .rel.text : { *(.rel.text) }
	36	+ .rela.text : { *(.rela.text) }
	37	+ .rel.data : { *(.rel.data) }
	38	+ .rela.data : { *(.rela.data) }
	39	+ .rel.rodata : { *(.rel.rodata) }
	40	+ .rela.rodata : { *(.rela.rodata) }
	41	+ .rel.got : { *(.rel.got) }
	42	+ .rela.got : { *(.rela.got) }
	43	+ .rel.ctors : { *(.rel.ctors) }
	44	+ .rela.ctors : { *(.rela.ctors) }
	45	+ .rel.dtors : { *(.rel.dtors) }
	46	+ .rela.dtors : { *(.rela.dtors) }
	47	+ .rel.bss : { *(.rel.bss) }
	48	+ .rela.bss : { *(.rela.bss) }
	49	+ .rel.plt : { *(.rel.plt) }
	50	+ .rela.plt : { *(.rela.plt) }
	51	+ .init : { *(.init) }
	52	+ .plt : { *(.plt) }
	53	+ .text :
	54	+ {
	55	+ /* WARNING - the following is hand-optimized to fit within */
	56	+ /* the sector layout of our flash chips! XXX FIXME XXX */
	57	+
	58	+ cpu/mcf52x2/start.o (.text)
	59	+ lib_m68k/traps.o (.text)
	60	+ cpu/mcf52x2/interrupts.o (.text)
	61	+ common/dlmalloc.o (.text)
	62	+ lib_generic/zlib.o (.text)
	63	+
	64	+ . = DEFINED(env_offset) ? env_offset : .;
	65	+ common/environment.o (.text)
	66	+
	67	+
	68	+ *(.text)
	69	+ *(.fixup)
	70	+ *(.got1)
	71	+ }
	72	+ _etext = .;
	73	+ PROVIDE (etext = .);
	74	+ .rodata :
	75	+ {
	76	+ *(.rodata)
	77	+ *(.rodata1)
	78	+ }
	79	+ .fini : { *(.fini) } =0
	80	+ .ctors : { *(.ctors) }
	81	+ .dtors : { *(.dtors) }
	82	+
	83	+ /* Read-write section, merged into data segment: */
	84	+ . = (. + 0x00FF) & 0xFFFFFF00;
	85	+ _erotext = .;
	86	+ PROVIDE (erotext = .);
	87	+
	88	+ .reloc :
	89	+ {
	90	+ __got_start = .;
	91	+ *(.got)
	92	+ __got_end = .;
	93	+ _GOT2_TABLE_ = .;
	94	+ *(.got2)
	95	+ _FIXUP_TABLE_ = .;
	96	+ *(.fixup)
	97	+ }
	98	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
	99	+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
	100	+
	101	+ .data :
	102	+ {
	103	+ *(.data)
	104	+ *(.data1)
	105	+ *(.sdata)
	106	+ *(.sdata2)
	107	+ *(.dynamic)
	108	+ CONSTRUCTORS
	109	+ }
	110	+ _edata = .;
	111	+ PROVIDE (edata = .);
	112	+
	113	+ . = .;
	114	+ __u_boot_cmd_start = .;
	115	+ .u_boot_cmd : { *(.u_boot_cmd) }
	116	+ __u_boot_cmd_end = .;
	117	+
	118	+
	119	+ . = .;
	120	+ __start___ex_table = .;
	121	+ __ex_table : { *(__ex_table) }
	122	+ __stop___ex_table = .;
	123	+
	124	+ . = ALIGN(256);
	125	+ __init_begin = .;
	126	+ .text.init : { *(.text.init) }
	127	+ .data.init : { *(.data.init) }
	128	+ . = ALIGN(256);
	129	+ __init_end = .;
	130	+
	131	+ __bss_start = .;
	132	+ .bss :
	133	+ {
	134	+ _sbss = .;
	135	+ (.sbss) (.scommon)
	136	+ *(.dynbss)
	137	+ *(.bss)
	138	+ *(COMMON)
	139	+ . = ALIGN(4);
	140	+ _ebss = .;
	141	+ }
	142	+ _end = . ;
	143	+ PROVIDE (end = .);
	144	+}
	1	+/*
	2	+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	+ * Hayden Fraser (Hayden.Fraser@freescale.com)
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#ifndef _M5253DEMO_H
	25	+#define _M5253DEMO_H
	26	+
	27	+#define CONFIG_MCF52x2 /* define processor family */
	28	+#define CONFIG_M5253 /* define processor type */
	29	+#define CONFIG_M5253DEMO /* define board type */
	30	+
	31	+#define CONFIG_MCFTMR
	32	+
	33	+#define CONFIG_MCFUART
	34	+#define CFG_UART_PORT (0)
	35	+#define CONFIG_BAUDRATE 115200
	36	+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
	37	+
	38	+#undef CONFIG_WATCHDOG /* disable watchdog */
	39	+
	40	+#define CONFIG_BOOTDELAY 5
	41	+
	42	+/* Configuration for environment
	43	+ * Environment is embedded in u-boot in the second sector of the flash
	44	+ */
	45	+#ifdef CONFIG_MONITOR_IS_IN_RAM
	46	+# define CFG_ENV_OFFSET 0x4000
	47	+# define CFG_ENV_SECT_SIZE 0x1000
	48	+# define CFG_ENV_IS_IN_FLASH 1
	49	+#else
	50	+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
	51	+# define CFG_ENV_SECT_SIZE 0x1000
	52	+# define CFG_ENV_IS_IN_FLASH 1
	53	+#endif
	54	+
	55	+/*
	56	+ * Command line configuration.
	57	+ */
	58	+#include <config_cmd_default.h>
	59	+
	60	+#define CONFIG_CMD_LOADB
	61	+#define CONFIG_CMD_LOADS
	62	+#define CONFIG_CMD_EXT2
	63	+#define CONFIG_CMD_FAT
	64	+#define CONFIG_CMD_IDE
	65	+#define CONFIG_CMD_MEMORY
	66	+#define CONFIG_CMD_MISC
	67	+#define CONFIG_CMD_PING
	68	+
	69	+#ifdef CONFIG_CMD_IDE
	70	+/* ATA */
	71	+# define CONFIG_DOS_PARTITION
	72	+# define CONFIG_MAC_PARTITION
	73	+# define CONFIG_IDE_RESET 1
	74	+# define CONFIG_IDE_PREINIT 1
	75	+# define CONFIG_ATAPI
	76	+# undef CONFIG_LBA48
	77	+
	78	+# define CFG_IDE_MAXBUS 1
	79	+# define CFG_IDE_MAXDEVICE 2
	80	+
	81	+# define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800)
	82	+# define CFG_ATA_IDE0_OFFSET 0
	83	+
	84	+# define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	85	+# define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	86	+# define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	87	+# define CFG_ATA_STRIDE 4 /* Interval between registers */
	88	+# define _IO_BASE 0
	89	+#endif
	90	+
	91	+#define CONFIG_DRIVER_DM9000
	92	+#ifdef CONFIG_DRIVER_DM9000
	93	+# define CONFIG_DM9000_BASE ((CFG_CSAR1 << 16) \| 0x300)
	94	+# define DM9000_IO CONFIG_DM9000_BASE
	95	+# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	96	+# undef CONFIG_DM9000_DEBUG
	97	+
	98	+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	99	+# define CONFIG_IPADDR 10.82.121.249
	100	+# define CONFIG_NETMASK 255.255.252.0
	101	+# define CONFIG_SERVERIP 10.82.120.80
	102	+# define CONFIG_GATEWAYIP 10.82.123.254
	103	+# define CONFIG_OVERWRITE_ETHADDR_ONCE
	104	+
	105	+# define CONFIG_EXTRA_ENV_SETTINGS \
	106	+ "netdev=eth0\0" \
	107	+ "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
	108	+ "loadaddr=10000\0" \
	109	+ "u-boot=u-boot.bin\0" \
	110	+ "load=tftp ${loadaddr) ${u-boot}\0" \
	111	+ "upd=run load; run prog\0" \
	112	+ "prog=prot off 0 2ffff;" \
	113	+ "era 0 2ffff;" \
	114	+ "cp.b ${loadaddr} 0 ${filesize};" \
	115	+ "save\0" \
	116	+ ""
	117	+#endif
	118	+
	119	+#define CONFIG_HOSTNAME M5253DEMO
	120	+
	121	+#define CFG_PROMPT "=> "
	122	+#define CFG_LONGHELP /* undef to save memory */
	123	+
	124	+#if defined(CONFIG_CMD_KGDB)
	125	+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	126	+#else
	127	+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	128	+#endif
	129	+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	130	+#define CFG_MAXARGS 16 /* max number of command args */
	131	+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	132	+
	133	+#define CFG_LOAD_ADDR 0x00100000
	134	+
	135	+#define CFG_MEMTEST_START 0x400
	136	+#define CFG_MEMTEST_END 0x380000
	137	+
	138	+#define CFG_HZ 1000
	139	+
	140	+#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
	141	+#define CFG_FAST_CLK
	142	+#ifdef CFG_FAST_CLK
	143	+# define CFG_PLLCR 0x1243E054
	144	+# define CFG_CLK 140000000
	145	+#else
	146	+# define CFG_PLLCR 0x135a4140
	147	+# define CFG_CLK 70000000
	148	+#endif
	149	+
	150	+/*
	151	+ * Low Level Configuration Settings
	152	+ * (address mappings, register initial values, etc.)
	153	+ * You should know what you are doing if you make changes here.
	154	+ */
	155	+
	156	+#define CFG_MBAR 0x10000000 /* Register Base Addrs */
	157	+#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */
	158	+
	159	+/*
	160	+ * Definitions for initial stack pointer and data area (in DPRAM)
	161	+ */
	162	+#define CFG_INIT_RAM_ADDR 0x20000000
	163	+#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
	164	+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	165	+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	166	+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	167	+
	168	+/*
	169	+ * Start addresses for the final memory configuration
	170	+ * (Set up by the startup code)
	171	+ * Please note that CFG_SDRAM_BASE _must_ start at 0
	172	+ */
	173	+#define CFG_SDRAM_BASE 0x00000000
	174	+#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
	175	+
	176	+#ifdef CONFIG_MONITOR_IS_IN_RAM
	177	+# define CFG_MONITOR_BASE 0x20000
	178	+#else
	179	+# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
	180	+#endif
	181	+
	182	+#define CFG_MONITOR_LEN 0x40000
	183	+#define CFG_MALLOC_LEN (256 << 10)
	184	+#define CFG_BOOTPARAMS_LEN (64*1024)
	185	+
	186	+/*
	187	+ * For booting Linux, the board info and command line data
	188	+ * have to be in the first 8 MB of memory, since this is
	189	+ * the maximum mapped by the Linux kernel during initialization ??
	190	+ */
	191	+#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
	192	+
	193	+/* FLASH organization */
	194	+#define CFG_FLASH_BASE (CFG_CSAR0 << 16)
	195	+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	196	+#define CFG_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	197	+#define CFG_FLASH_ERASE_TOUT 1000
	198	+
	199	+#define FLASH_SST6401B 0x200
	200	+#define SST_ID_xF6401B 0x236D236D
	201	+
	202	+#undef CFG_FLASH_CFI
	203	+#ifdef CFG_FLASH_CFI
	204	+/*
	205	+ * Unable to use CFI driver, due to incompatible sector erase command by SST.
	206	+ * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	207	+ * 0x30 is block erase in SST
	208	+ */
	209	+# define CFG_FLASH_CFI_DRIVER 1
	210	+# define CFG_FLASH_SIZE 0x800000
	211	+# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	212	+# define CONFIG_FLASH_CFI_LEGACY
	213	+#else
	214	+# define CFG_SST_SECT 2048
	215	+# define CFG_SST_SECTSZ 0x1000
	216	+# define CFG_FLASH_WRITE_TOUT 500
	217	+#endif
	218	+
	219	+/* Cache Configuration */
	220	+#define CFG_CACHELINE_SIZE 16
	221	+
	222	+/* Port configuration */
	223	+#define CFG_FECI2C 0xF0
	224	+
	225	+#define CFG_CSAR0 0xFF80
	226	+#define CFG_CSMR0 0x007F0021
	227	+#define CFG_CSCR0 0x1D80
	228	+
	229	+#define CFG_CSAR1 0xE000
	230	+#define CFG_CSMR1 0x00000001
	231	+#define CFG_CSCR1 0x3DD8
	232	+
	233	+#define CFG_CSAR2 0
	234	+#define CFG_CSMR2 0
	235	+#define CFG_CSCR2 0
	236	+
	237	+#define CFG_CSAR3 0
	238	+#define CFG_CSMR3 0
	239	+#define CFG_CSCR3 0
	240	+
	241	+/*-----------------------------------------------------------------------
	242	+ * Port configuration
	243	+ */
	244	+#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	245	+#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	246	+#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
	247	+#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	248	+#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
	249	+#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	250	+#define CFG_GPIO1_LED 0x00400000 /* user led */
	251	+
	252	+#endif /* _M5253DEMO_H */