mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL

This mainly converts the am335x_spl_bch driver to the "normal" format which means a slight change to nand_info within the driver. Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>

mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL
This mainly converts the am335x_spl_bch driver to the "normal" format which means a slight change to nand_info within the driver. Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini
1 parent 39b924a304
Showing 4 changed files with 33 additions and 27 deletions Side-by-side Diff
README
drivers/mtd/nand/am335x_spl_bch.c
include/configs/ti_armv7_common.h
spl/Makefile
@@ -3326,6 +3326,10 @@
 		Support for NAND boot using simple NAND drivers that
 		expose the cmd_ctrl() interface.
  
+		CONFIG_SPL_MTD_SUPPORT
+		Support for the MTD subsystem within SPL.  Useful for
+		environment on NAND support within SPL.
+
 		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 		Set for the SPL on PPC mpc8xxx targets, support for
 		drivers/ddr/fsl/libddr.o in SPL binary.
@@ -16,7 +16,7 @@
 #include <linux/mtd/nand_ecc.h>
  
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static nand_info_t mtd;
+nand_info_t nand_info[1];
 static struct nand_chip nand_chip;
  
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
  
@@ -30,12 +30,12 @@
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = nand_info[0].priv;
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
  
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(&nand_info[0]))
 		;
  
 	/* Emulate NAND_CMD_READOOB */
  
@@ -45,11 +45,11 @@
 	}
  
 	/* Begin command latch cycle */
-	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  
 	if (cmd == NAND_CMD_RESET) {
-		hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-		while (!this->dev_ready(&mtd))
+		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		while (!this->dev_ready(&nand_info[0]))
 			;
 		return 0;
 	}
  
  
  
  
  
  
  
  
  
@@ -60,35 +60,35 @@
  
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	hwctrl(&mtd, offs & 0xff,
+	hwctrl(&nand_info[0], offs & 0xff,
 		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
-	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+	hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+	hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+	hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
 		       NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 	/* One more address cycle for devices > 128MiB */
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  
 	if (cmd == NAND_CMD_READ0) {
 		/* Latch in address */
-		hwctrl(&mtd, NAND_CMD_READSTART,
+		hwctrl(&nand_info[0], NAND_CMD_READSTART,
 			   NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-		hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  
 		/*
 		 * Wait a while for the data to be ready
 		 */
-		while (!this->dev_ready(&mtd))
+		while (!this->dev_ready(&nand_info[0]))
 			;
 	} else if (cmd == NAND_CMD_RNDOUT) {
-		hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+		hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
 					NAND_CTRL_CHANGE);
-		hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 	}
  
 	return 0;
@@ -96,7 +96,7 @@
  
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = nand_info[0].priv;
  
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		NAND_CMD_READOOB);
@@ -117,7 +117,7 @@
  
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = nand_info[0].priv;
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  
  
@@ -133,15 +133,15 @@
 	nand_command(block, page, 0, NAND_CMD_READ0);
  
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		this->ecc.hwctl(&mtd, NAND_ECC_READ);
+		this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
 		nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
  
-		this->read_buf(&mtd, p, eccsize);
+		this->read_buf(&nand_info[0], p, eccsize);
  
 		nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
  
-		this->read_buf(&mtd, oob, eccbytes);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+		this->read_buf(&nand_info[0], oob, eccbytes);
+		this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
  
 		data_pos += eccsize;
 		oob_pos += eccbytes;
@@ -160,7 +160,7 @@
 		 * from correct_data(). We just hope that all possible errors
 		 * are corrected by this routine.
 		 */
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
 	}
  
 	return 0;
  
@@ -206,13 +206,13 @@
 	/*
 	 * Init board specific nand support
 	 */
-	mtd.priv = &nand_chip;
+	nand_info[0].priv = &nand_chip;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
  
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(&nand_info[0], 0);
  
 	/* NAND chip may require reset after power-on */
 	nand_command(0, 0, 0, NAND_CMD_RESET);
@@ -222,6 +222,6 @@
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, -1);
+		nand_chip.select_chip(&nand_info[0], -1);
 }
@@ -245,6 +245,7 @@
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MTD_SUPPORT
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #endif
@@ -104,6 +104,7 @@
 libs-y += fs/
 libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
 libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
+libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/
 libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
 libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
 libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
...	...	@@ -3326,6 +3326,10 @@
3326	3326	Support for NAND boot using simple NAND drivers that
3327	3327	expose the cmd_ctrl() interface.
3328	3328
	3329	+ CONFIG_SPL_MTD_SUPPORT
	3330	+ Support for the MTD subsystem within SPL. Useful for
	3331	+ environment on NAND support within SPL.
	3332	+
3329	3333	CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
3330	3334	Set for the SPL on PPC mpc8xxx targets, support for
3331	3335	drivers/ddr/fsl/libddr.o in SPL binary.
...	...	@@ -16,7 +16,7 @@
16	16	#include <linux/mtd/nand_ecc.h>
17	17
18	18	static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
19		-static nand_info_t mtd;
	19	+nand_info_t nand_info[1];
20	20	static struct nand_chip nand_chip;
21	21
22	22	#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
23	23
...	...	@@ -30,12 +30,12 @@
30	30	static int nand_command(int block, int page, uint32_t offs,
31	31	u8 cmd)
32	32	{
33		- struct nand_chip *this = mtd.priv;
	33	+ struct nand_chip *this = nand_info[0].priv;
34	34	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
35	35	void (hwctrl)(struct mtd_info mtd, int cmd,
36	36	unsigned int ctrl) = this->cmd_ctrl;
37	37
38		- while (!this->dev_ready(&mtd))
	38	+ while (!this->dev_ready(&nand_info[0]))
39	39	;
40	40
41	41	/* Emulate NAND_CMD_READOOB */
42	42
...	...	@@ -45,11 +45,11 @@
45	45	}
46	46
47	47	/* Begin command latch cycle */
48		- hwctrl(&mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
	48	+ hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
49	49
50	50	if (cmd == NAND_CMD_RESET) {
51		- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
52		- while (!this->dev_ready(&mtd))
	51	+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
	52	+ while (!this->dev_ready(&nand_info[0]))
53	53	;
54	54	return 0;
55	55	}
56	56
57	57
58	58
59	59
60	60
61	61
62	62
63	63
64	64
...	...	@@ -60,35 +60,35 @@
60	60
61	61	/* Set ALE and clear CLE to start address cycle */
62	62	/* Column address */
63		- hwctrl(&mtd, offs & 0xff,
	63	+ hwctrl(&nand_info[0], offs & 0xff,
64	64	NAND_CTRL_ALE \| NAND_CTRL_CHANGE); /* A[7:0] */
65		- hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
	65	+ hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
66	66	/* Row address */
67		- hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
68		- hwctrl(&mtd, ((page_addr >> 8) & 0xff),
	67	+ hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
	68	+ hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
69	69	NAND_CTRL_ALE); /* A[27:20] */
70	70	#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
71	71	/* One more address cycle for devices > 128MiB */
72		- hwctrl(&mtd, (page_addr >> 16) & 0x0f,
	72	+ hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
73	73	NAND_CTRL_ALE); /* A[31:28] */
74	74	#endif
75		- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
	75	+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
76	76
77	77	if (cmd == NAND_CMD_READ0) {
78	78	/* Latch in address */
79		- hwctrl(&mtd, NAND_CMD_READSTART,
	79	+ hwctrl(&nand_info[0], NAND_CMD_READSTART,
80	80	NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
81		- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
	81	+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
82	82
83	83	/*
84	84	* Wait a while for the data to be ready
85	85	*/
86		- while (!this->dev_ready(&mtd))
	86	+ while (!this->dev_ready(&nand_info[0]))
87	87	;
88	88	} else if (cmd == NAND_CMD_RNDOUT) {
89		- hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE \|
	89	+ hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE \|
90	90	NAND_CTRL_CHANGE);
91		- hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
	91	+ hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
92	92	}
93	93
94	94	return 0;
...	...	@@ -96,7 +96,7 @@
96	96
97	97	static int nand_is_bad_block(int block)
98	98	{
99		- struct nand_chip *this = mtd.priv;
	99	+ struct nand_chip *this = nand_info[0].priv;
100	100
101	101	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
102	102	NAND_CMD_READOOB);
...	...	@@ -117,7 +117,7 @@
117	117
118	118	static int nand_read_page(int block, int page, void *dst)
119	119	{
120		- struct nand_chip *this = mtd.priv;
	120	+ struct nand_chip *this = nand_info[0].priv;
121	121	u_char ecc_calc[ECCTOTAL];
122	122	u_char ecc_code[ECCTOTAL];
123	123	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
124	124
125	125
...	...	@@ -133,15 +133,15 @@
133	133	nand_command(block, page, 0, NAND_CMD_READ0);
134	134
135	135	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
136		- this->ecc.hwctl(&mtd, NAND_ECC_READ);
	136	+ this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
137	137	nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
138	138
139		- this->read_buf(&mtd, p, eccsize);
	139	+ this->read_buf(&nand_info[0], p, eccsize);
140	140
141	141	nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
142	142
143		- this->read_buf(&mtd, oob, eccbytes);
144		- this->ecc.calculate(&mtd, p, &ecc_calc[i]);
	143	+ this->read_buf(&nand_info[0], oob, eccbytes);
	144	+ this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
145	145
146	146	data_pos += eccsize;
147	147	oob_pos += eccbytes;
...	...	@@ -160,7 +160,7 @@
160	160	* from correct_data(). We just hope that all possible errors
161	161	* are corrected by this routine.
162	162	*/
163		- this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
	163	+ this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
164	164	}
165	165
166	166	return 0;
167	167
...	...	@@ -206,13 +206,13 @@
206	206	/*
207	207	* Init board specific nand support
208	208	*/
209		- mtd.priv = &nand_chip;
	209	+ nand_info[0].priv = &nand_chip;
210	210	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
211	211	(void __iomem *)CONFIG_SYS_NAND_BASE;
212	212	board_nand_init(&nand_chip);
213	213
214	214	if (nand_chip.select_chip)
215		- nand_chip.select_chip(&mtd, 0);
	215	+ nand_chip.select_chip(&nand_info[0], 0);
216	216
217	217	/* NAND chip may require reset after power-on */
218	218	nand_command(0, 0, 0, NAND_CMD_RESET);
...	...	@@ -222,6 +222,6 @@
222	222	void nand_deselect(void)
223	223	{
224	224	if (nand_chip.select_chip)
225		- nand_chip.select_chip(&mtd, -1);
	225	+ nand_chip.select_chip(&nand_info[0], -1);
226	226	}
...	...	@@ -245,6 +245,7 @@
245	245	#define CONFIG_SPL_NAND_BASE
246	246	#define CONFIG_SPL_NAND_DRIVERS
247	247	#define CONFIG_SPL_NAND_ECC
	248	+#define CONFIG_SPL_MTD_SUPPORT
248	249	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
249	250	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
250	251	#endif
...	...	@@ -104,6 +104,7 @@
104	104	libs-y += fs/
105	105	libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
106	106	libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
	107	+libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/
107	108	libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
108	109	libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
109	110	libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/