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Commit 6e9e06260d4fa8873fdebddc2a11f9205674d189

Authored by Oleksandr Tymoshenko
Committed by Marek Vasut
1 parent a7f2472224
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

usb: dwc2: Add driver for Synopsis DWC2 USB IP block 

This is the USB host controller used on the Altera SoCFPGA and Raspbery Pi.

This code has three checkpatch warnings, but to make sure it stays at least
readable and clear, these are not fixed. These bugs are in the USB request
handling combinatorial logic, so any abstracting of those is out of question.

Tested on DENX MCV (Altera SoCFPGA 5CSFXC6C6U23C8N) and RPi B+ (BCM2835).

Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Vince Bridgers <vbridger@altera.com>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Showing 5 changed files with 1843 additions and 1 deletions Side-by-side Diff

... ... @@ -1465,6 +1465,9 @@
1465 1465 CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
1466 1466 txfilltuning field in the EHCI controller on reset.
1467 1467  
  1468 + CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
  1469 + HW module registers.
  1470 +
1468 1471 - USB Device:
1469 1472 Define the below if you wish to use the USB console.
1470 1473 Once firmware is rebuilt from a serial console issue the
drivers/usb/host/Makefile
Diff comments   View file @ 6e9e062
... ... @@ -45,4 +45,7 @@
45 45 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
46 46 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
47 47 obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
  48 +
  49 +# designware
  50 +obj-$(CONFIG_USB_DWC2) += dwc2.o
drivers/usb/host/dwc2.c
Diff comments   View file @ 6e9e062
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
  3 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <errno.h>
  10 +#include <usb.h>
  11 +#include <malloc.h>
  12 +#include <usbroothubdes.h>
  13 +#include <asm/io.h>
  14 +
  15 +#include "dwc2.h"
  16 +
  17 +/* Use only HC channel 0. */
  18 +#define DWC2_HC_CHANNEL 0
  19 +
  20 +#define DWC2_STATUS_BUF_SIZE 64
  21 +#define DWC2_DATA_BUF_SIZE (64 * 1024)
  22 +
  23 +/* We need doubleword-aligned buffers for DMA transfers */
  24 +DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
  25 +DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
  26 +
  27 +#define MAX_DEVICE 16
  28 +#define MAX_ENDPOINT 16
  29 +static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  30 +static int control_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  31 +
  32 +static int root_hub_devnum;
  33 +
  34 +static struct dwc2_core_regs *regs =
  35 + (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
  36 +
  37 +/*
  38 + * DWC2 IP interface
  39 + */
  40 +static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  41 +{
  42 + unsigned int timeout = 1000000;
  43 + uint32_t val;
  44 +
  45 + while (--timeout) {
  46 + val = readl(reg);
  47 + if (!set)
  48 + val = ~val;
  49 +
  50 + if ((val & mask) == mask)
  51 + return 0;
  52 +
  53 + udelay(1);
  54 + }
  55 +
  56 + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  57 + __func__, reg, mask, set);
  58 +
  59 + return -ETIMEDOUT;
  60 +}
  61 +
  62 +/*
  63 + * Initializes the FSLSPClkSel field of the HCFG register
  64 + * depending on the PHY type.
  65 + */
  66 +static void init_fslspclksel(struct dwc2_core_regs *regs)
  67 +{
  68 + uint32_t phyclk;
  69 +
  70 +#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  71 + phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
  72 +#else
  73 + /* High speed PHY running at full speed or high speed */
  74 + phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  75 +#endif
  76 +
  77 +#ifdef CONFIG_DWC2_ULPI_FS_LS
  78 + uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  79 + uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  80 + DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  81 + uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  82 + DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  83 +
  84 + if (hval == 2 && fval == 1)
  85 + phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
  86 +#endif
  87 +
  88 + clrsetbits_le32(&regs->host_regs.hcfg,
  89 + DWC2_HCFG_FSLSPCLKSEL_MASK,
  90 + phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
  91 +}
  92 +
  93 +/*
  94 + * Flush a Tx FIFO.
  95 + *
  96 + * @param regs Programming view of DWC_otg controller.
  97 + * @param num Tx FIFO to flush.
  98 + */
  99 +static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
  100 +{
  101 + int ret;
  102 +
  103 + writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
  104 + &regs->grstctl);
  105 + ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
  106 + if (ret)
  107 + printf("%s: Timeout!\n", __func__);
  108 +
  109 + /* Wait for 3 PHY Clocks */
  110 + udelay(1);
  111 +}
  112 +
  113 +/*
  114 + * Flush Rx FIFO.
  115 + *
  116 + * @param regs Programming view of DWC_otg controller.
  117 + */
  118 +static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
  119 +{
  120 + int ret;
  121 +
  122 + writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
  123 + ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
  124 + if (ret)
  125 + printf("%s: Timeout!\n", __func__);
  126 +
  127 + /* Wait for 3 PHY Clocks */
  128 + udelay(1);
  129 +}
  130 +
  131 +/*
  132 + * Do core a soft reset of the core. Be careful with this because it
  133 + * resets all the internal state machines of the core.
  134 + */
  135 +static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
  136 +{
  137 + int ret;
  138 +
  139 + /* Wait for AHB master IDLE state. */
  140 + ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
  141 + if (ret)
  142 + printf("%s: Timeout!\n", __func__);
  143 +
  144 + /* Core Soft Reset */
  145 + writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
  146 + ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
  147 + if (ret)
  148 + printf("%s: Timeout!\n", __func__);
  149 +
  150 + /*
  151 + * Wait for core to come out of reset.
  152 + * NOTE: This long sleep is _very_ important, otherwise the core will
  153 + * not stay in host mode after a connector ID change!
  154 + */
  155 + mdelay(100);
  156 +}
  157 +
  158 +/*
  159 + * This function initializes the DWC_otg controller registers for
  160 + * host mode.
  161 + *
  162 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
  163 + * request queues. Host channels are reset to ensure that they are ready for
  164 + * performing transfers.
  165 + *
  166 + * @param regs Programming view of DWC_otg controller
  167 + *
  168 + */
  169 +static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
  170 +{
  171 + uint32_t nptxfifosize = 0;
  172 + uint32_t ptxfifosize = 0;
  173 + uint32_t hprt0 = 0;
  174 + int i, ret, num_channels;
  175 +
  176 + /* Restart the Phy Clock */
  177 + writel(0, &regs->pcgcctl);
  178 +
  179 + /* Initialize Host Configuration Register */
  180 + init_fslspclksel(regs);
  181 +#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
  182 + setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
  183 +#endif
  184 +
  185 + /* Configure data FIFO sizes */
  186 +#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
  187 + if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
  188 + /* Rx FIFO */
  189 + writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
  190 +
  191 + /* Non-periodic Tx FIFO */
  192 + nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
  193 + DWC2_FIFOSIZE_DEPTH_OFFSET;
  194 + nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
  195 + DWC2_FIFOSIZE_STARTADDR_OFFSET;
  196 + writel(nptxfifosize, &regs->gnptxfsiz);
  197 +
  198 + /* Periodic Tx FIFO */
  199 + ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
  200 + DWC2_FIFOSIZE_DEPTH_OFFSET;
  201 + ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
  202 + CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
  203 + DWC2_FIFOSIZE_STARTADDR_OFFSET;
  204 + writel(ptxfifosize, &regs->hptxfsiz);
  205 + }
  206 +#endif
  207 +
  208 + /* Clear Host Set HNP Enable in the OTG Control Register */
  209 + clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
  210 +
  211 + /* Make sure the FIFOs are flushed. */
  212 + dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
  213 + dwc_otg_flush_rx_fifo(regs);
  214 +
  215 + /* Flush out any leftover queued requests. */
  216 + num_channels = readl(&regs->ghwcfg2);
  217 + num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
  218 + num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
  219 + num_channels += 1;
  220 +
  221 + for (i = 0; i < num_channels; i++)
  222 + clrsetbits_le32(&regs->hc_regs[i].hcchar,
  223 + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
  224 + DWC2_HCCHAR_CHDIS);
  225 +
  226 + /* Halt all channels to put them into a known state. */
  227 + for (i = 0; i < num_channels; i++) {
  228 + clrsetbits_le32(&regs->hc_regs[i].hcchar,
  229 + DWC2_HCCHAR_EPDIR,
  230 + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
  231 + ret = wait_for_bit(&regs->hc_regs[i].hcchar,
  232 + DWC2_HCCHAR_CHEN, 0);
  233 + if (ret)
  234 + printf("%s: Timeout!\n", __func__);
  235 + }
  236 +
  237 + /* Turn on the vbus power. */
  238 + if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
  239 + hprt0 = readl(&regs->hprt0);
  240 + hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
  241 + hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
  242 + if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
  243 + hprt0 |= DWC2_HPRT0_PRTPWR;
  244 + writel(hprt0, &regs->hprt0);
  245 + }
  246 + }
  247 +}
  248 +
  249 +/*
  250 + * This function initializes the DWC_otg controller registers and
  251 + * prepares the core for device mode or host mode operation.
  252 + *
  253 + * @param regs Programming view of the DWC_otg controller
  254 + */
  255 +static void dwc_otg_core_init(struct dwc2_core_regs *regs)
  256 +{
  257 + uint32_t ahbcfg = 0;
  258 + uint32_t usbcfg = 0;
  259 + uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
  260 +
  261 + /* Common Initialization */
  262 + usbcfg = readl(&regs->gusbcfg);
  263 +
  264 + /* Program the ULPI External VBUS bit if needed */
  265 +#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
  266 + usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
  267 +#else
  268 + usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
  269 +#endif
  270 +
  271 + /* Set external TS Dline pulsing */
  272 +#ifdef CONFIG_DWC2_TS_DLINE
  273 + usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
  274 +#else
  275 + usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
  276 +#endif
  277 + writel(usbcfg, &regs->gusbcfg);
  278 +
  279 + /* Reset the Controller */
  280 + dwc_otg_core_reset(regs);
  281 +
  282 + /*
  283 + * This programming sequence needs to happen in FS mode before
  284 + * any other programming occurs
  285 + */
  286 +#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
  287 + (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  288 + /* If FS mode with FS PHY */
  289 + setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
  290 +
  291 + /* Reset after a PHY select */
  292 + dwc_otg_core_reset(regs);
  293 +
  294 + /*
  295 + * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
  296 + * Also do this on HNP Dev/Host mode switches (done in dev_init
  297 + * and host_init).
  298 + */
  299 + if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
  300 + init_fslspclksel(regs);
  301 +
  302 +#ifdef CONFIG_DWC2_I2C_ENABLE
  303 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
  304 + setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
  305 +
  306 + /* Program GI2CCTL.I2CEn */
  307 + clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
  308 + DWC2_GI2CCTL_I2CDEVADDR_MASK,
  309 + 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
  310 + setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
  311 +#endif
  312 +
  313 +#else
  314 + /* High speed PHY. */
  315 +
  316 + /*
  317 + * HS PHY parameters. These parameters are preserved during
  318 + * soft reset so only program the first time. Do a soft reset
  319 + * immediately after setting phyif.
  320 + */
  321 + usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
  322 + usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
  323 +
  324 + if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
  325 +#ifdef CONFIG_DWC2_PHY_ULPI_DDR
  326 + usbcfg |= DWC2_GUSBCFG_DDRSEL;
  327 +#else
  328 + usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
  329 +#endif
  330 + } else { /* UTMI+ interface */
  331 +#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
  332 + usbcfg |= DWC2_GUSBCFG_PHYIF;
  333 +#endif
  334 + }
  335 +
  336 + writel(usbcfg, &regs->gusbcfg);
  337 +
  338 + /* Reset after setting the PHY parameters */
  339 + dwc_otg_core_reset(regs);
  340 +#endif
  341 +
  342 + usbcfg = readl(&regs->gusbcfg);
  343 + usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
  344 +#ifdef CONFIG_DWC2_ULPI_FS_LS
  345 + uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  346 + uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  347 + DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  348 + uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  349 + DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  350 + if (hval == 2 && fval == 1) {
  351 + usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
  352 + usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
  353 + }
  354 +#endif
  355 + writel(usbcfg, &regs->gusbcfg);
  356 +
  357 + /* Program the GAHBCFG Register. */
  358 + switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
  359 + case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
  360 + break;
  361 + case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
  362 + while (brst_sz > 1) {
  363 + ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
  364 + ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
  365 + brst_sz >>= 1;
  366 + }
  367 +
  368 +#ifdef CONFIG_DWC2_DMA_ENABLE
  369 + ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
  370 +#endif
  371 + break;
  372 +
  373 + case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
  374 + ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
  375 +#ifdef CONFIG_DWC2_DMA_ENABLE
  376 + ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
  377 +#endif
  378 + break;
  379 + }
  380 +
  381 + writel(ahbcfg, &regs->gahbcfg);
  382 +
  383 + /* Program the GUSBCFG register for HNP/SRP. */
  384 + setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
  385 +
  386 +#ifdef CONFIG_DWC2_IC_USB_CAP
  387 + setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
  388 +#endif
  389 +}
  390 +
  391 +/*
  392 + * Prepares a host channel for transferring packets to/from a specific
  393 + * endpoint. The HCCHARn register is set up with the characteristics specified
  394 + * in _hc. Host channel interrupts that may need to be serviced while this
  395 + * transfer is in progress are enabled.
  396 + *
  397 + * @param regs Programming view of DWC_otg controller
  398 + * @param hc Information needed to initialize the host channel
  399 + */
  400 +static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
  401 + uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
  402 + uint8_t ep_type, uint16_t max_packet)
  403 +{
  404 + struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
  405 + const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
  406 + (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
  407 + (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
  408 + (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
  409 + (max_packet << DWC2_HCCHAR_MPS_OFFSET);
  410 +
  411 + /* Clear old interrupt conditions for this host channel. */
  412 + writel(0x3fff, &hc_regs->hcint);
  413 +
  414 + /*
  415 + * Program the HCCHARn register with the endpoint characteristics
  416 + * for the current transfer.
  417 + */
  418 + writel(hcchar, &hc_regs->hcchar);
  419 +
  420 + /* Program the HCSPLIT register for SPLITs */
  421 + writel(0, &hc_regs->hcsplt);
  422 +}
  423 +
  424 +/*
  425 + * DWC2 to USB API interface
  426 + */
  427 +/* Direction: In ; Request: Status */
  428 +static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
  429 + int txlen, struct devrequest *cmd)
  430 +{
  431 + uint32_t hprt0 = 0;
  432 + uint32_t port_status = 0;
  433 + uint32_t port_change = 0;
  434 + int len = 0;
  435 + int stat = 0;
  436 +
  437 + switch (cmd->requesttype & ~USB_DIR_IN) {
  438 + case 0:
  439 + *(uint16_t *)buffer = cpu_to_le16(1);
  440 + len = 2;
  441 + break;
  442 + case USB_RECIP_INTERFACE:
  443 + case USB_RECIP_ENDPOINT:
  444 + *(uint16_t *)buffer = cpu_to_le16(0);
  445 + len = 2;
  446 + break;
  447 + case USB_TYPE_CLASS:
  448 + *(uint32_t *)buffer = cpu_to_le32(0);
  449 + len = 4;
  450 + break;
  451 + case USB_RECIP_OTHER | USB_TYPE_CLASS:
  452 + hprt0 = readl(&regs->hprt0);
  453 + if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
  454 + port_status |= USB_PORT_STAT_CONNECTION;
  455 + if (hprt0 & DWC2_HPRT0_PRTENA)
  456 + port_status |= USB_PORT_STAT_ENABLE;
  457 + if (hprt0 & DWC2_HPRT0_PRTSUSP)
  458 + port_status |= USB_PORT_STAT_SUSPEND;
  459 + if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
  460 + port_status |= USB_PORT_STAT_OVERCURRENT;
  461 + if (hprt0 & DWC2_HPRT0_PRTRST)
  462 + port_status |= USB_PORT_STAT_RESET;
  463 + if (hprt0 & DWC2_HPRT0_PRTPWR)
  464 + port_status |= USB_PORT_STAT_POWER;
  465 +
  466 + port_status |= USB_PORT_STAT_HIGH_SPEED;
  467 +
  468 + if (hprt0 & DWC2_HPRT0_PRTENCHNG)
  469 + port_change |= USB_PORT_STAT_C_ENABLE;
  470 + if (hprt0 & DWC2_HPRT0_PRTCONNDET)
  471 + port_change |= USB_PORT_STAT_C_CONNECTION;
  472 + if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
  473 + port_change |= USB_PORT_STAT_C_OVERCURRENT;
  474 +
  475 + *(uint32_t *)buffer = cpu_to_le32(port_status |
  476 + (port_change << 16));
  477 + len = 4;
  478 + break;
  479 + default:
  480 + puts("unsupported root hub command\n");
  481 + stat = USB_ST_STALLED;
  482 + }
  483 +
  484 + dev->act_len = min(len, txlen);
  485 + dev->status = stat;
  486 +
  487 + return stat;
  488 +}
  489 +
  490 +/* Direction: In ; Request: Descriptor */
  491 +static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
  492 + void *buffer, int txlen,
  493 + struct devrequest *cmd)
  494 +{
  495 + unsigned char data[32];
  496 + uint32_t dsc;
  497 + int len = 0;
  498 + int stat = 0;
  499 + uint16_t wValue = cpu_to_le16(cmd->value);
  500 + uint16_t wLength = cpu_to_le16(cmd->length);
  501 +
  502 + switch (cmd->requesttype & ~USB_DIR_IN) {
  503 + case 0:
  504 + switch (wValue & 0xff00) {
  505 + case 0x0100: /* device descriptor */
  506 + len = min3(txlen, sizeof(root_hub_dev_des), wLength);
  507 + memcpy(buffer, root_hub_dev_des, len);
  508 + break;
  509 + case 0x0200: /* configuration descriptor */
  510 + len = min3(txlen, sizeof(root_hub_config_des), wLength);
  511 + memcpy(buffer, root_hub_config_des, len);
  512 + break;
  513 + case 0x0300: /* string descriptors */
  514 + switch (wValue & 0xff) {
  515 + case 0x00:
  516 + len = min3(txlen, sizeof(root_hub_str_index0),
  517 + wLength);
  518 + memcpy(buffer, root_hub_str_index0, len);
  519 + break;
  520 + case 0x01:
  521 + len = min3(txlen, sizeof(root_hub_str_index1),
  522 + wLength);
  523 + memcpy(buffer, root_hub_str_index1, len);
  524 + break;
  525 + }
  526 + break;
  527 + default:
  528 + stat = USB_ST_STALLED;
  529 + }
  530 + break;
  531 +
  532 + case USB_TYPE_CLASS:
  533 + /* Root port config, set 1 port and nothing else. */
  534 + dsc = 0x00000001;
  535 +
  536 + data[0] = 9; /* min length; */
  537 + data[1] = 0x29;
  538 + data[2] = dsc & RH_A_NDP;
  539 + data[3] = 0;
  540 + if (dsc & RH_A_PSM)
  541 + data[3] |= 0x1;
  542 + if (dsc & RH_A_NOCP)
  543 + data[3] |= 0x10;
  544 + else if (dsc & RH_A_OCPM)
  545 + data[3] |= 0x8;
  546 +
  547 + /* corresponds to data[4-7] */
  548 + data[5] = (dsc & RH_A_POTPGT) >> 24;
  549 + data[7] = dsc & RH_B_DR;
  550 + if (data[2] < 7) {
  551 + data[8] = 0xff;
  552 + } else {
  553 + data[0] += 2;
  554 + data[8] = (dsc & RH_B_DR) >> 8;
  555 + data[9] = 0xff;
  556 + data[10] = data[9];
  557 + }
  558 +
  559 + len = min3(txlen, data[0], wLength);
  560 + memcpy(buffer, data, len);
  561 + break;
  562 + default:
  563 + puts("unsupported root hub command\n");
  564 + stat = USB_ST_STALLED;
  565 + }
  566 +
  567 + dev->act_len = min(len, txlen);
  568 + dev->status = stat;
  569 +
  570 + return stat;
  571 +}
  572 +
  573 +/* Direction: In ; Request: Configuration */
  574 +static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
  575 + void *buffer, int txlen,
  576 + struct devrequest *cmd)
  577 +{
  578 + int len = 0;
  579 + int stat = 0;
  580 +
  581 + switch (cmd->requesttype & ~USB_DIR_IN) {
  582 + case 0:
  583 + *(uint8_t *)buffer = 0x01;
  584 + len = 1;
  585 + break;
  586 + default:
  587 + puts("unsupported root hub command\n");
  588 + stat = USB_ST_STALLED;
  589 + }
  590 +
  591 + dev->act_len = min(len, txlen);
  592 + dev->status = stat;
  593 +
  594 + return stat;
  595 +}
  596 +
  597 +/* Direction: In */
  598 +static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
  599 + void *buffer, int txlen,
  600 + struct devrequest *cmd)
  601 +{
  602 + switch (cmd->request) {
  603 + case USB_REQ_GET_STATUS:
  604 + return dwc_otg_submit_rh_msg_in_status(dev, buffer,
  605 + txlen, cmd);
  606 + case USB_REQ_GET_DESCRIPTOR:
  607 + return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
  608 + txlen, cmd);
  609 + case USB_REQ_GET_CONFIGURATION:
  610 + return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
  611 + txlen, cmd);
  612 + default:
  613 + puts("unsupported root hub command\n");
  614 + return USB_ST_STALLED;
  615 + }
  616 +}
  617 +
  618 +/* Direction: Out */
  619 +static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
  620 + void *buffer, int txlen,
  621 + struct devrequest *cmd)
  622 +{
  623 + int len = 0;
  624 + int stat = 0;
  625 + uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
  626 + uint16_t wValue = cpu_to_le16(cmd->value);
  627 +
  628 + switch (bmrtype_breq & ~USB_DIR_IN) {
  629 + case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
  630 + case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
  631 + break;
  632 +
  633 + case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
  634 + switch (wValue) {
  635 + case USB_PORT_FEAT_C_CONNECTION:
  636 + setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
  637 + break;
  638 + }
  639 + break;
  640 +
  641 + case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
  642 + switch (wValue) {
  643 + case USB_PORT_FEAT_SUSPEND:
  644 + break;
  645 +
  646 + case USB_PORT_FEAT_RESET:
  647 + clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  648 + DWC2_HPRT0_PRTCONNDET |
  649 + DWC2_HPRT0_PRTENCHNG |
  650 + DWC2_HPRT0_PRTOVRCURRCHNG,
  651 + DWC2_HPRT0_PRTRST);
  652 + mdelay(50);
  653 + clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
  654 + break;
  655 +
  656 + case USB_PORT_FEAT_POWER:
  657 + clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  658 + DWC2_HPRT0_PRTCONNDET |
  659 + DWC2_HPRT0_PRTENCHNG |
  660 + DWC2_HPRT0_PRTOVRCURRCHNG,
  661 + DWC2_HPRT0_PRTRST);
  662 + break;
  663 +
  664 + case USB_PORT_FEAT_ENABLE:
  665 + break;
  666 + }
  667 + break;
  668 + case (USB_REQ_SET_ADDRESS << 8):
  669 + root_hub_devnum = wValue;
  670 + break;
  671 + case (USB_REQ_SET_CONFIGURATION << 8):
  672 + break;
  673 + default:
  674 + puts("unsupported root hub command\n");
  675 + stat = USB_ST_STALLED;
  676 + }
  677 +
  678 + len = min(len, txlen);
  679 +
  680 + dev->act_len = len;
  681 + dev->status = stat;
  682 +
  683 + return stat;
  684 +}
  685 +
  686 +static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  687 + void *buffer, int txlen,
  688 + struct devrequest *cmd)
  689 +{
  690 + int stat = 0;
  691 +
  692 + if (usb_pipeint(pipe)) {
  693 + puts("Root-Hub submit IRQ: NOT implemented\n");
  694 + return 0;
  695 + }
  696 +
  697 + if (cmd->requesttype & USB_DIR_IN)
  698 + stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
  699 + else
  700 + stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
  701 +
  702 + mdelay(1);
  703 +
  704 + return stat;
  705 +}
  706 +
  707 +/* U-Boot USB transmission interface */
  708 +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  709 + int len)
  710 +{
  711 + int devnum = usb_pipedevice(pipe);
  712 + int ep = usb_pipeendpoint(pipe);
  713 + int max = usb_maxpacket(dev, pipe);
  714 + int done = 0;
  715 + uint32_t hctsiz, sub, tmp;
  716 + struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
  717 + uint32_t hcint;
  718 + uint32_t xfer_len;
  719 + uint32_t num_packets;
  720 + int stop_transfer = 0;
  721 + unsigned int timeout = 1000000;
  722 +
  723 + if (devnum == root_hub_devnum) {
  724 + dev->status = 0;
  725 + return -EINVAL;
  726 + }
  727 +
  728 + if (len > DWC2_DATA_BUF_SIZE) {
  729 + printf("%s: %d is more then available buffer size (%d)\n",
  730 + __func__, len, DWC2_DATA_BUF_SIZE);
  731 + dev->status = 0;
  732 + dev->act_len = 0;
  733 + return -EINVAL;
  734 + }
  735 +
  736 + while ((done < len) && !stop_transfer) {
  737 + /* Initialize channel */
  738 + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
  739 + usb_pipein(pipe), DWC2_HCCHAR_EPTYPE_BULK, max);
  740 +
  741 + xfer_len = len - done;
  742 + /* Make sure that xfer_len is a multiple of max packet size. */
  743 + if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
  744 + xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
  745 +
  746 + if (xfer_len > 0) {
  747 + num_packets = (xfer_len + max - 1) / max;
  748 + if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
  749 + num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
  750 + xfer_len = num_packets * max;
  751 + }
  752 + } else {
  753 + num_packets = 1;
  754 + }
  755 +
  756 + if (usb_pipein(pipe))
  757 + xfer_len = num_packets * max;
  758 +
  759 + writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
  760 + (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
  761 + (bulk_data_toggle[devnum][ep] <<
  762 + DWC2_HCTSIZ_PID_OFFSET),
  763 + &hc_regs->hctsiz);
  764 +
  765 + memcpy(aligned_buffer, (char *)buffer + done, len - done);
  766 + writel((uint32_t)aligned_buffer, &hc_regs->hcdma);
  767 +
  768 + /* Set host channel enable after all other setup is complete. */
  769 + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
  770 + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
  771 + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
  772 + DWC2_HCCHAR_CHEN);
  773 +
  774 + while (1) {
  775 + hcint = readl(&hc_regs->hcint);
  776 +
  777 + if (!(hcint & DWC2_HCINT_CHHLTD))
  778 + continue;
  779 +
  780 + if (hcint & DWC2_HCINT_XFERCOMP) {
  781 + hctsiz = readl(&hc_regs->hctsiz);
  782 + done += xfer_len;
  783 +
  784 + sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
  785 + sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
  786 +
  787 + if (usb_pipein(pipe)) {
  788 + done -= sub;
  789 + if (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK)
  790 + stop_transfer = 1;
  791 + }
  792 +
  793 + tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
  794 + tmp >>= DWC2_HCTSIZ_PID_OFFSET;
  795 + if (tmp == DWC2_HC_PID_DATA1) {
  796 + bulk_data_toggle[devnum][ep] =
  797 + DWC2_HC_PID_DATA1;
  798 + } else {
  799 + bulk_data_toggle[devnum][ep] =
  800 + DWC2_HC_PID_DATA0;
  801 + }
  802 + break;
  803 + }
  804 +
  805 + if (hcint & DWC2_HCINT_STALL) {
  806 + puts("DWC OTG: Channel halted\n");
  807 + bulk_data_toggle[devnum][ep] =
  808 + DWC2_HC_PID_DATA0;
  809 +
  810 + stop_transfer = 1;
  811 + break;
  812 + }
  813 +
  814 + if (!--timeout) {
  815 + printf("%s: Timeout!\n", __func__);
  816 + break;
  817 + }
  818 + }
  819 + }
  820 +
  821 + if (done && usb_pipein(pipe))
  822 + memcpy(buffer, aligned_buffer, done);
  823 +
  824 + writel(0, &hc_regs->hcintmsk);
  825 + writel(0xFFFFFFFF, &hc_regs->hcint);
  826 +
  827 + dev->status = 0;
  828 + dev->act_len = done;
  829 +
  830 + return 0;
  831 +}
  832 +
  833 +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  834 + int len, struct devrequest *setup)
  835 +{
  836 + struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
  837 + int done = 0;
  838 + int devnum = usb_pipedevice(pipe);
  839 + int ep = usb_pipeendpoint(pipe);
  840 + int max = usb_maxpacket(dev, pipe);
  841 + uint32_t hctsiz = 0, sub, tmp, ret;
  842 + uint32_t hcint;
  843 + const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP |
  844 + DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK;
  845 + unsigned int timeout = 1000000;
  846 +
  847 + /* For CONTROL endpoint pid should start with DATA1 */
  848 + int status_direction;
  849 +
  850 + if (devnum == root_hub_devnum) {
  851 + dev->status = 0;
  852 + dev->speed = USB_SPEED_HIGH;
  853 + return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
  854 + }
  855 +
  856 + if (len > DWC2_DATA_BUF_SIZE) {
  857 + printf("%s: %d is more then available buffer size(%d)\n",
  858 + __func__, len, DWC2_DATA_BUF_SIZE);
  859 + dev->status = 0;
  860 + dev->act_len = 0;
  861 + return -EINVAL;
  862 + }
  863 +
  864 + /* Initialize channel, OUT for setup buffer */
  865 + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, 0,
  866 + DWC2_HCCHAR_EPTYPE_CONTROL, max);
  867 +
  868 + /* SETUP stage */
  869 + writel((8 << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
  870 + (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
  871 + (DWC2_HC_PID_SETUP << DWC2_HCTSIZ_PID_OFFSET),
  872 + &hc_regs->hctsiz);
  873 +
  874 + writel((uint32_t)setup, &hc_regs->hcdma);
  875 +
  876 + /* Set host channel enable after all other setup is complete. */
  877 + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
  878 + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
  879 + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
  880 +
  881 + ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, 1);
  882 + if (ret)
  883 + printf("%s: Timeout!\n", __func__);
  884 +
  885 + hcint = readl(&hc_regs->hcint);
  886 +
  887 + if (!(hcint & DWC2_HCINT_CHHLTD) || !(hcint & DWC2_HCINT_XFERCOMP)) {
  888 + printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
  889 + dev->status = 0;
  890 + dev->act_len = 0;
  891 + return -EINVAL;
  892 + }
  893 +
  894 + /* Clear interrupts */
  895 + writel(0, &hc_regs->hcintmsk);
  896 + writel(0xFFFFFFFF, &hc_regs->hcint);
  897 +
  898 + if (buffer) {
  899 + /* DATA stage */
  900 + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
  901 + usb_pipein(pipe),
  902 + DWC2_HCCHAR_EPTYPE_CONTROL, max);
  903 +
  904 + /* TODO: check if len < 64 */
  905 + control_data_toggle[devnum][ep] = DWC2_HC_PID_DATA1;
  906 + writel((len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
  907 + (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
  908 + (control_data_toggle[devnum][ep] <<
  909 + DWC2_HCTSIZ_PID_OFFSET),
  910 + &hc_regs->hctsiz);
  911 +
  912 + writel((uint32_t)buffer, &hc_regs->hcdma);
  913 +
  914 + /* Set host channel enable after all other setup is complete */
  915 + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
  916 + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
  917 + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
  918 + DWC2_HCCHAR_CHEN);
  919 +
  920 + while (1) {
  921 + hcint = readl(&hc_regs->hcint);
  922 + if (!(hcint & DWC2_HCINT_CHHLTD))
  923 + continue;
  924 +
  925 + if (hcint & DWC2_HCINT_XFERCOMP) {
  926 + hctsiz = readl(&hc_regs->hctsiz);
  927 + done = len;
  928 +
  929 + sub = hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK;
  930 + sub >>= DWC2_HCTSIZ_XFERSIZE_OFFSET;
  931 +
  932 + if (usb_pipein(pipe))
  933 + done -= sub;
  934 + }
  935 +
  936 + if (hcint & DWC2_HCINT_ACK) {
  937 + tmp = hctsiz & DWC2_HCTSIZ_PID_MASK;
  938 + tmp >>= DWC2_HCTSIZ_PID_OFFSET;
  939 + if (tmp == DWC2_HC_PID_DATA0) {
  940 + control_data_toggle[devnum][ep] =
  941 + DWC2_HC_PID_DATA0;
  942 + } else {
  943 + control_data_toggle[devnum][ep] =
  944 + DWC2_HC_PID_DATA1;
  945 + }
  946 + }
  947 +
  948 + if (hcint != hcint_comp_hlt_ack) {
  949 + printf("%s: Error (HCINT=%08x)\n",
  950 + __func__, hcint);
  951 + goto out;
  952 + }
  953 +
  954 + if (!--timeout) {
  955 + printf("%s: Timeout!\n", __func__);
  956 + goto out;
  957 + }
  958 +
  959 + break;
  960 + }
  961 + } /* End of DATA stage */
  962 +
  963 + /* STATUS stage */
  964 + if ((len == 0) || usb_pipeout(pipe))
  965 + status_direction = 1;
  966 + else
  967 + status_direction = 0;
  968 +
  969 + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
  970 + status_direction, DWC2_HCCHAR_EPTYPE_CONTROL, max);
  971 +
  972 + writel((1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
  973 + (DWC2_HC_PID_DATA1 << DWC2_HCTSIZ_PID_OFFSET),
  974 + &hc_regs->hctsiz);
  975 +
  976 + writel((uint32_t)status_buffer, &hc_regs->hcdma);
  977 +
  978 + /* Set host channel enable after all other setup is complete. */
  979 + clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
  980 + DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
  981 + (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
  982 +
  983 + while (1) {
  984 + hcint = readl(&hc_regs->hcint);
  985 + if (hcint & DWC2_HCINT_CHHLTD)
  986 + break;
  987 + }
  988 +
  989 + if (hcint != hcint_comp_hlt_ack)
  990 + printf("%s: Error (HCINT=%08x)\n", __func__, hcint);
  991 +
  992 +out:
  993 + dev->act_len = done;
  994 + dev->status = 0;
  995 +
  996 + return done;
  997 +}
  998 +
  999 +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1000 + int len, int interval)
  1001 +{
  1002 + printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
  1003 + dev, pipe, buffer, len, interval);
  1004 + return -ENOSYS;
  1005 +}
  1006 +
  1007 +/* U-Boot USB control interface */
  1008 +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1009 +{
  1010 + uint32_t snpsid;
  1011 + int i, j;
  1012 +
  1013 + root_hub_devnum = 0;
  1014 +
  1015 + snpsid = readl(&regs->gsnpsid);
  1016 + printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
  1017 +
  1018 + if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
  1019 + printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
  1020 + return -ENODEV;
  1021 + }
  1022 +
  1023 + dwc_otg_core_init(regs);
  1024 + dwc_otg_core_host_init(regs);
  1025 +
  1026 + clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  1027 + DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
  1028 + DWC2_HPRT0_PRTOVRCURRCHNG,
  1029 + DWC2_HPRT0_PRTRST);
  1030 + mdelay(50);
  1031 + clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
  1032 + DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
  1033 + DWC2_HPRT0_PRTRST);
  1034 +
  1035 + for (i = 0; i < MAX_DEVICE; i++) {
  1036 + for (j = 0; j < MAX_ENDPOINT; j++) {
  1037 + control_data_toggle[i][j] = DWC2_HC_PID_DATA1;
  1038 + bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
  1039 + }
  1040 + }
  1041 +
  1042 + return 0;
  1043 +}
  1044 +
  1045 +int usb_lowlevel_stop(int index)
  1046 +{
  1047 + /* Put everything in reset. */
  1048 + clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  1049 + DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
  1050 + DWC2_HPRT0_PRTOVRCURRCHNG,
  1051 + DWC2_HPRT0_PRTRST);
  1052 + return 0;
  1053 +}
drivers/usb/host/dwc2.h
Diff comments   View file @ 6e9e062
  1 +/*
  2 + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DWC2_H__
  8 +#define __DWC2_H__
  9 +
  10 +struct dwc2_hc_regs {
  11 + u32 hcchar; /* 0x00 */
  12 + u32 hcsplt;
  13 + u32 hcint;
  14 + u32 hcintmsk;
  15 + u32 hctsiz; /* 0x10 */
  16 + u32 hcdma;
  17 + u32 reserved;
  18 + u32 hcdmab;
  19 +};
  20 +
  21 +struct dwc2_host_regs {
  22 + u32 hcfg; /* 0x00 */
  23 + u32 hfir;
  24 + u32 hfnum;
  25 + u32 _pad_0x40c;
  26 + u32 hptxsts; /* 0x10 */
  27 + u32 haint;
  28 + u32 haintmsk;
  29 + u32 hflbaddr;
  30 +};
  31 +
  32 +struct dwc2_core_regs {
  33 + u32 gotgctl; /* 0x000 */
  34 + u32 gotgint;
  35 + u32 gahbcfg;
  36 + u32 gusbcfg;
  37 + u32 grstctl; /* 0x010 */
  38 + u32 gintsts;
  39 + u32 gintmsk;
  40 + u32 grxstsr;
  41 + u32 grxstsp; /* 0x020 */
  42 + u32 grxfsiz;
  43 + u32 gnptxfsiz;
  44 + u32 gnptxsts;
  45 + u32 gi2cctl; /* 0x030 */
  46 + u32 gpvndctl;
  47 + u32 ggpio;
  48 + u32 guid;
  49 + u32 gsnpsid; /* 0x040 */
  50 + u32 ghwcfg1;
  51 + u32 ghwcfg2;
  52 + u32 ghwcfg3;
  53 + u32 ghwcfg4; /* 0x050 */
  54 + u32 glpmcfg;
  55 + u32 _pad_0x58_0x9c[42];
  56 + u32 hptxfsiz; /* 0x100 */
  57 + u32 dptxfsiz_dieptxf[15];
  58 + u32 _pad_0x140_0x3fc[176];
  59 + struct dwc2_host_regs host_regs; /* 0x400 */
  60 + u32 _pad_0x420_0x43c[8];
  61 + u32 hprt0; /* 0x440 */
  62 + u32 _pad_0x444_0x4fc[47];
  63 + struct dwc2_hc_regs hc_regs[16]; /* 0x500 */
  64 + u32 _pad_0x700_0xe00[448];
  65 + u32 pcgcctl; /* 0xe00 */
  66 +};
  67 +
  68 +#define DWC2_GOTGCTL_SESREQSCS (1 << 0)
  69 +#define DWC2_GOTGCTL_SESREQSCS_OFFSET 0
  70 +#define DWC2_GOTGCTL_SESREQ (1 << 1)
  71 +#define DWC2_GOTGCTL_SESREQ_OFFSET 1
  72 +#define DWC2_GOTGCTL_HSTNEGSCS (1 << 8)
  73 +#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET 8
  74 +#define DWC2_GOTGCTL_HNPREQ (1 << 9)
  75 +#define DWC2_GOTGCTL_HNPREQ_OFFSET 9
  76 +#define DWC2_GOTGCTL_HSTSETHNPEN (1 << 10)
  77 +#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET 10
  78 +#define DWC2_GOTGCTL_DEVHNPEN (1 << 11)
  79 +#define DWC2_GOTGCTL_DEVHNPEN_OFFSET 11
  80 +#define DWC2_GOTGCTL_CONIDSTS (1 << 16)
  81 +#define DWC2_GOTGCTL_CONIDSTS_OFFSET 16
  82 +#define DWC2_GOTGCTL_DBNCTIME (1 << 17)
  83 +#define DWC2_GOTGCTL_DBNCTIME_OFFSET 17
  84 +#define DWC2_GOTGCTL_ASESVLD (1 << 18)
  85 +#define DWC2_GOTGCTL_ASESVLD_OFFSET 18
  86 +#define DWC2_GOTGCTL_BSESVLD (1 << 19)
  87 +#define DWC2_GOTGCTL_BSESVLD_OFFSET 19
  88 +#define DWC2_GOTGCTL_OTGVER (1 << 20)
  89 +#define DWC2_GOTGCTL_OTGVER_OFFSET 20
  90 +#define DWC2_GOTGINT_SESENDDET (1 << 2)
  91 +#define DWC2_GOTGINT_SESENDDET_OFFSET 2
  92 +#define DWC2_GOTGINT_SESREQSUCSTSCHNG (1 << 8)
  93 +#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET 8
  94 +#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG (1 << 9)
  95 +#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 9
  96 +#define DWC2_GOTGINT_RESERVER10_16_MASK (0x7F << 10)
  97 +#define DWC2_GOTGINT_RESERVER10_16_OFFSET 10
  98 +#define DWC2_GOTGINT_HSTNEGDET (1 << 17)
  99 +#define DWC2_GOTGINT_HSTNEGDET_OFFSET 17
  100 +#define DWC2_GOTGINT_ADEVTOUTCHNG (1 << 18)
  101 +#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET 18
  102 +#define DWC2_GOTGINT_DEBDONE (1 << 19)
  103 +#define DWC2_GOTGINT_DEBDONE_OFFSET 19
  104 +#define DWC2_GAHBCFG_GLBLINTRMSK (1 << 0)
  105 +#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET 0
  106 +#define DWC2_GAHBCFG_HBURSTLEN_SINGLE (0 << 1)
  107 +#define DWC2_GAHBCFG_HBURSTLEN_INCR (1 << 1)
  108 +#define DWC2_GAHBCFG_HBURSTLEN_INCR4 (3 << 1)
  109 +#define DWC2_GAHBCFG_HBURSTLEN_INCR8 (5 << 1)
  110 +#define DWC2_GAHBCFG_HBURSTLEN_INCR16 (7 << 1)
  111 +#define DWC2_GAHBCFG_HBURSTLEN_MASK (0xF << 1)
  112 +#define DWC2_GAHBCFG_HBURSTLEN_OFFSET 1
  113 +#define DWC2_GAHBCFG_DMAENABLE (1 << 5)
  114 +#define DWC2_GAHBCFG_DMAENABLE_OFFSET 5
  115 +#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL (1 << 7)
  116 +#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET 7
  117 +#define DWC2_GAHBCFG_PTXFEMPLVL (1 << 8)
  118 +#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET 8
  119 +#define DWC2_GUSBCFG_TOUTCAL_MASK (0x7 << 0)
  120 +#define DWC2_GUSBCFG_TOUTCAL_OFFSET 0
  121 +#define DWC2_GUSBCFG_PHYIF (1 << 3)
  122 +#define DWC2_GUSBCFG_PHYIF_OFFSET 3
  123 +#define DWC2_GUSBCFG_ULPI_UTMI_SEL (1 << 4)
  124 +#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET 4
  125 +#define DWC2_GUSBCFG_FSINTF (1 << 5)
  126 +#define DWC2_GUSBCFG_FSINTF_OFFSET 5
  127 +#define DWC2_GUSBCFG_PHYSEL (1 << 6)
  128 +#define DWC2_GUSBCFG_PHYSEL_OFFSET 6
  129 +#define DWC2_GUSBCFG_DDRSEL (1 << 7)
  130 +#define DWC2_GUSBCFG_DDRSEL_OFFSET 7
  131 +#define DWC2_GUSBCFG_SRPCAP (1 << 8)
  132 +#define DWC2_GUSBCFG_SRPCAP_OFFSET 8
  133 +#define DWC2_GUSBCFG_HNPCAP (1 << 9)
  134 +#define DWC2_GUSBCFG_HNPCAP_OFFSET 9
  135 +#define DWC2_GUSBCFG_USBTRDTIM_MASK (0xF << 10)
  136 +#define DWC2_GUSBCFG_USBTRDTIM_OFFSET 10
  137 +#define DWC2_GUSBCFG_NPTXFRWNDEN (1 << 14)
  138 +#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET 14
  139 +#define DWC2_GUSBCFG_PHYLPWRCLKSEL (1 << 15)
  140 +#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET 15
  141 +#define DWC2_GUSBCFG_OTGUTMIFSSEL (1 << 16)
  142 +#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET 16
  143 +#define DWC2_GUSBCFG_ULPI_FSLS (1 << 17)
  144 +#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET 17
  145 +#define DWC2_GUSBCFG_ULPI_AUTO_RES (1 << 18)
  146 +#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET 18
  147 +#define DWC2_GUSBCFG_ULPI_CLK_SUS_M (1 << 19)
  148 +#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET 19
  149 +#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
  150 +#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET 20
  151 +#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR (1 << 21)
  152 +#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21
  153 +#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE (1 << 22)
  154 +#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET 22
  155 +#define DWC2_GUSBCFG_IC_USB_CAP (1 << 26)
  156 +#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET 26
  157 +#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE (1 << 27)
  158 +#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET 27
  159 +#define DWC2_GUSBCFG_TX_END_DELAY (1 << 28)
  160 +#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET 28
  161 +#define DWC2_GUSBCFG_FORCEHOSTMODE (1 << 29)
  162 +#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET 29
  163 +#define DWC2_GUSBCFG_FORCEDEVMODE (1 << 30)
  164 +#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET 30
  165 +#define DWC2_GLPMCTL_LPM_CAP_EN (1 << 0)
  166 +#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET 0
  167 +#define DWC2_GLPMCTL_APPL_RESP (1 << 1)
  168 +#define DWC2_GLPMCTL_APPL_RESP_OFFSET 1
  169 +#define DWC2_GLPMCTL_HIRD_MASK (0xF << 2)
  170 +#define DWC2_GLPMCTL_HIRD_OFFSET 2
  171 +#define DWC2_GLPMCTL_REM_WKUP_EN (1 << 6)
  172 +#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET 6
  173 +#define DWC2_GLPMCTL_EN_UTMI_SLEEP (1 << 7)
  174 +#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET 7
  175 +#define DWC2_GLPMCTL_HIRD_THRES_MASK (0x1F << 8)
  176 +#define DWC2_GLPMCTL_HIRD_THRES_OFFSET 8
  177 +#define DWC2_GLPMCTL_LPM_RESP_MASK (0x3 << 13)
  178 +#define DWC2_GLPMCTL_LPM_RESP_OFFSET 13
  179 +#define DWC2_GLPMCTL_PRT_SLEEP_STS (1 << 15)
  180 +#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET 15
  181 +#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK (1 << 16)
  182 +#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET 16
  183 +#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK (0xF << 17)
  184 +#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET 17
  185 +#define DWC2_GLPMCTL_RETRY_COUNT_MASK (0x7 << 21)
  186 +#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET 21
  187 +#define DWC2_GLPMCTL_SEND_LPM (1 << 24)
  188 +#define DWC2_GLPMCTL_SEND_LPM_OFFSET 24
  189 +#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK (0x7 << 25)
  190 +#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET 25
  191 +#define DWC2_GLPMCTL_HSIC_CONNECT (1 << 30)
  192 +#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET 30
  193 +#define DWC2_GLPMCTL_INV_SEL_HSIC (1 << 31)
  194 +#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET 31
  195 +#define DWC2_GRSTCTL_CSFTRST (1 << 0)
  196 +#define DWC2_GRSTCTL_CSFTRST_OFFSET 0
  197 +#define DWC2_GRSTCTL_HSFTRST (1 << 1)
  198 +#define DWC2_GRSTCTL_HSFTRST_OFFSET 1
  199 +#define DWC2_GRSTCTL_HSTFRM (1 << 2)
  200 +#define DWC2_GRSTCTL_HSTFRM_OFFSET 2
  201 +#define DWC2_GRSTCTL_INTKNQFLSH (1 << 3)
  202 +#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET 3
  203 +#define DWC2_GRSTCTL_RXFFLSH (1 << 4)
  204 +#define DWC2_GRSTCTL_RXFFLSH_OFFSET 4
  205 +#define DWC2_GRSTCTL_TXFFLSH (1 << 5)
  206 +#define DWC2_GRSTCTL_TXFFLSH_OFFSET 5
  207 +#define DWC2_GRSTCTL_TXFNUM_MASK (0x1F << 6)
  208 +#define DWC2_GRSTCTL_TXFNUM_OFFSET 6
  209 +#define DWC2_GRSTCTL_DMAREQ (1 << 30)
  210 +#define DWC2_GRSTCTL_DMAREQ_OFFSET 30
  211 +#define DWC2_GRSTCTL_AHBIDLE (1 << 31)
  212 +#define DWC2_GRSTCTL_AHBIDLE_OFFSET 31
  213 +#define DWC2_GINTMSK_MODEMISMATCH (1 << 1)
  214 +#define DWC2_GINTMSK_MODEMISMATCH_OFFSET 1
  215 +#define DWC2_GINTMSK_OTGINTR (1 << 2)
  216 +#define DWC2_GINTMSK_OTGINTR_OFFSET 2
  217 +#define DWC2_GINTMSK_SOFINTR (1 << 3)
  218 +#define DWC2_GINTMSK_SOFINTR_OFFSET 3
  219 +#define DWC2_GINTMSK_RXSTSQLVL (1 << 4)
  220 +#define DWC2_GINTMSK_RXSTSQLVL_OFFSET 4
  221 +#define DWC2_GINTMSK_NPTXFEMPTY (1 << 5)
  222 +#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET 5
  223 +#define DWC2_GINTMSK_GINNAKEFF (1 << 6)
  224 +#define DWC2_GINTMSK_GINNAKEFF_OFFSET 6
  225 +#define DWC2_GINTMSK_GOUTNAKEFF (1 << 7)
  226 +#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET 7
  227 +#define DWC2_GINTMSK_I2CINTR (1 << 9)
  228 +#define DWC2_GINTMSK_I2CINTR_OFFSET 9
  229 +#define DWC2_GINTMSK_ERLYSUSPEND (1 << 10)
  230 +#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET 10
  231 +#define DWC2_GINTMSK_USBSUSPEND (1 << 11)
  232 +#define DWC2_GINTMSK_USBSUSPEND_OFFSET 11
  233 +#define DWC2_GINTMSK_USBRESET (1 << 12)
  234 +#define DWC2_GINTMSK_USBRESET_OFFSET 12
  235 +#define DWC2_GINTMSK_ENUMDONE (1 << 13)
  236 +#define DWC2_GINTMSK_ENUMDONE_OFFSET 13
  237 +#define DWC2_GINTMSK_ISOOUTDROP (1 << 14)
  238 +#define DWC2_GINTMSK_ISOOUTDROP_OFFSET 14
  239 +#define DWC2_GINTMSK_EOPFRAME (1 << 15)
  240 +#define DWC2_GINTMSK_EOPFRAME_OFFSET 15
  241 +#define DWC2_GINTMSK_EPMISMATCH (1 << 17)
  242 +#define DWC2_GINTMSK_EPMISMATCH_OFFSET 17
  243 +#define DWC2_GINTMSK_INEPINTR (1 << 18)
  244 +#define DWC2_GINTMSK_INEPINTR_OFFSET 18
  245 +#define DWC2_GINTMSK_OUTEPINTR (1 << 19)
  246 +#define DWC2_GINTMSK_OUTEPINTR_OFFSET 19
  247 +#define DWC2_GINTMSK_INCOMPLISOIN (1 << 20)
  248 +#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET 20
  249 +#define DWC2_GINTMSK_INCOMPLISOOUT (1 << 21)
  250 +#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET 21
  251 +#define DWC2_GINTMSK_PORTINTR (1 << 24)
  252 +#define DWC2_GINTMSK_PORTINTR_OFFSET 24
  253 +#define DWC2_GINTMSK_HCINTR (1 << 25)
  254 +#define DWC2_GINTMSK_HCINTR_OFFSET 25
  255 +#define DWC2_GINTMSK_PTXFEMPTY (1 << 26)
  256 +#define DWC2_GINTMSK_PTXFEMPTY_OFFSET 26
  257 +#define DWC2_GINTMSK_LPMTRANRCVD (1 << 27)
  258 +#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET 27
  259 +#define DWC2_GINTMSK_CONIDSTSCHNG (1 << 28)
  260 +#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET 28
  261 +#define DWC2_GINTMSK_DISCONNECT (1 << 29)
  262 +#define DWC2_GINTMSK_DISCONNECT_OFFSET 29
  263 +#define DWC2_GINTMSK_SESSREQINTR (1 << 30)
  264 +#define DWC2_GINTMSK_SESSREQINTR_OFFSET 30
  265 +#define DWC2_GINTMSK_WKUPINTR (1 << 31)
  266 +#define DWC2_GINTMSK_WKUPINTR_OFFSET 31
  267 +#define DWC2_GINTSTS_CURMODE_DEVICE (0 << 0)
  268 +#define DWC2_GINTSTS_CURMODE_HOST (1 << 0)
  269 +#define DWC2_GINTSTS_CURMODE (1 << 0)
  270 +#define DWC2_GINTSTS_CURMODE_OFFSET 0
  271 +#define DWC2_GINTSTS_MODEMISMATCH (1 << 1)
  272 +#define DWC2_GINTSTS_MODEMISMATCH_OFFSET 1
  273 +#define DWC2_GINTSTS_OTGINTR (1 << 2)
  274 +#define DWC2_GINTSTS_OTGINTR_OFFSET 2
  275 +#define DWC2_GINTSTS_SOFINTR (1 << 3)
  276 +#define DWC2_GINTSTS_SOFINTR_OFFSET 3
  277 +#define DWC2_GINTSTS_RXSTSQLVL (1 << 4)
  278 +#define DWC2_GINTSTS_RXSTSQLVL_OFFSET 4
  279 +#define DWC2_GINTSTS_NPTXFEMPTY (1 << 5)
  280 +#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET 5
  281 +#define DWC2_GINTSTS_GINNAKEFF (1 << 6)
  282 +#define DWC2_GINTSTS_GINNAKEFF_OFFSET 6
  283 +#define DWC2_GINTSTS_GOUTNAKEFF (1 << 7)
  284 +#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET 7
  285 +#define DWC2_GINTSTS_I2CINTR (1 << 9)
  286 +#define DWC2_GINTSTS_I2CINTR_OFFSET 9
  287 +#define DWC2_GINTSTS_ERLYSUSPEND (1 << 10)
  288 +#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET 10
  289 +#define DWC2_GINTSTS_USBSUSPEND (1 << 11)
  290 +#define DWC2_GINTSTS_USBSUSPEND_OFFSET 11
  291 +#define DWC2_GINTSTS_USBRESET (1 << 12)
  292 +#define DWC2_GINTSTS_USBRESET_OFFSET 12
  293 +#define DWC2_GINTSTS_ENUMDONE (1 << 13)
  294 +#define DWC2_GINTSTS_ENUMDONE_OFFSET 13
  295 +#define DWC2_GINTSTS_ISOOUTDROP (1 << 14)
  296 +#define DWC2_GINTSTS_ISOOUTDROP_OFFSET 14
  297 +#define DWC2_GINTSTS_EOPFRAME (1 << 15)
  298 +#define DWC2_GINTSTS_EOPFRAME_OFFSET 15
  299 +#define DWC2_GINTSTS_INTOKENRX (1 << 16)
  300 +#define DWC2_GINTSTS_INTOKENRX_OFFSET 16
  301 +#define DWC2_GINTSTS_EPMISMATCH (1 << 17)
  302 +#define DWC2_GINTSTS_EPMISMATCH_OFFSET 17
  303 +#define DWC2_GINTSTS_INEPINT (1 << 18)
  304 +#define DWC2_GINTSTS_INEPINT_OFFSET 18
  305 +#define DWC2_GINTSTS_OUTEPINTR (1 << 19)
  306 +#define DWC2_GINTSTS_OUTEPINTR_OFFSET 19
  307 +#define DWC2_GINTSTS_INCOMPLISOIN (1 << 20)
  308 +#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET 20
  309 +#define DWC2_GINTSTS_INCOMPLISOOUT (1 << 21)
  310 +#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET 21
  311 +#define DWC2_GINTSTS_PORTINTR (1 << 24)
  312 +#define DWC2_GINTSTS_PORTINTR_OFFSET 24
  313 +#define DWC2_GINTSTS_HCINTR (1 << 25)
  314 +#define DWC2_GINTSTS_HCINTR_OFFSET 25
  315 +#define DWC2_GINTSTS_PTXFEMPTY (1 << 26)
  316 +#define DWC2_GINTSTS_PTXFEMPTY_OFFSET 26
  317 +#define DWC2_GINTSTS_LPMTRANRCVD (1 << 27)
  318 +#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET 27
  319 +#define DWC2_GINTSTS_CONIDSTSCHNG (1 << 28)
  320 +#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET 28
  321 +#define DWC2_GINTSTS_DISCONNECT (1 << 29)
  322 +#define DWC2_GINTSTS_DISCONNECT_OFFSET 29
  323 +#define DWC2_GINTSTS_SESSREQINTR (1 << 30)
  324 +#define DWC2_GINTSTS_SESSREQINTR_OFFSET 30
  325 +#define DWC2_GINTSTS_WKUPINTR (1 << 31)
  326 +#define DWC2_GINTSTS_WKUPINTR_OFFSET 31
  327 +#define DWC2_GRXSTS_EPNUM_MASK (0xF << 0)
  328 +#define DWC2_GRXSTS_EPNUM_OFFSET 0
  329 +#define DWC2_GRXSTS_BCNT_MASK (0x7FF << 4)
  330 +#define DWC2_GRXSTS_BCNT_OFFSET 4
  331 +#define DWC2_GRXSTS_DPID_MASK (0x3 << 15)
  332 +#define DWC2_GRXSTS_DPID_OFFSET 15
  333 +#define DWC2_GRXSTS_PKTSTS_MASK (0xF << 17)
  334 +#define DWC2_GRXSTS_PKTSTS_OFFSET 17
  335 +#define DWC2_GRXSTS_FN_MASK (0xF << 21)
  336 +#define DWC2_GRXSTS_FN_OFFSET 21
  337 +#define DWC2_FIFOSIZE_STARTADDR_MASK (0xFFFF << 0)
  338 +#define DWC2_FIFOSIZE_STARTADDR_OFFSET 0
  339 +#define DWC2_FIFOSIZE_DEPTH_MASK (0xFFFF << 16)
  340 +#define DWC2_FIFOSIZE_DEPTH_OFFSET 16
  341 +#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK (0xFFFF << 0)
  342 +#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET 0
  343 +#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK (0xFF << 16)
  344 +#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET 16
  345 +#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE (1 << 24)
  346 +#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET 24
  347 +#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK (0x3 << 25)
  348 +#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET 25
  349 +#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK (0xF << 27)
  350 +#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET 27
  351 +#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK (0xFFFF << 0)
  352 +#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET 0
  353 +#define DWC2_GI2CCTL_RWDATA_MASK (0xFF << 0)
  354 +#define DWC2_GI2CCTL_RWDATA_OFFSET 0
  355 +#define DWC2_GI2CCTL_REGADDR_MASK (0xFF << 8)
  356 +#define DWC2_GI2CCTL_REGADDR_OFFSET 8
  357 +#define DWC2_GI2CCTL_ADDR_MASK (0x7F << 16)
  358 +#define DWC2_GI2CCTL_ADDR_OFFSET 16
  359 +#define DWC2_GI2CCTL_I2CEN (1 << 23)
  360 +#define DWC2_GI2CCTL_I2CEN_OFFSET 23
  361 +#define DWC2_GI2CCTL_ACK (1 << 24)
  362 +#define DWC2_GI2CCTL_ACK_OFFSET 24
  363 +#define DWC2_GI2CCTL_I2CSUSPCTL (1 << 25)
  364 +#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET 25
  365 +#define DWC2_GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
  366 +#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET 26
  367 +#define DWC2_GI2CCTL_RW (1 << 30)
  368 +#define DWC2_GI2CCTL_RW_OFFSET 30
  369 +#define DWC2_GI2CCTL_BSYDNE (1 << 31)
  370 +#define DWC2_GI2CCTL_BSYDNE_OFFSET 31
  371 +#define DWC2_HWCFG1_EP_DIR0_MASK (0x3 << 0)
  372 +#define DWC2_HWCFG1_EP_DIR0_OFFSET 0
  373 +#define DWC2_HWCFG1_EP_DIR1_MASK (0x3 << 2)
  374 +#define DWC2_HWCFG1_EP_DIR1_OFFSET 2
  375 +#define DWC2_HWCFG1_EP_DIR2_MASK (0x3 << 4)
  376 +#define DWC2_HWCFG1_EP_DIR2_OFFSET 4
  377 +#define DWC2_HWCFG1_EP_DIR3_MASK (0x3 << 6)
  378 +#define DWC2_HWCFG1_EP_DIR3_OFFSET 6
  379 +#define DWC2_HWCFG1_EP_DIR4_MASK (0x3 << 8)
  380 +#define DWC2_HWCFG1_EP_DIR4_OFFSET 8
  381 +#define DWC2_HWCFG1_EP_DIR5_MASK (0x3 << 10)
  382 +#define DWC2_HWCFG1_EP_DIR5_OFFSET 10
  383 +#define DWC2_HWCFG1_EP_DIR6_MASK (0x3 << 12)
  384 +#define DWC2_HWCFG1_EP_DIR6_OFFSET 12
  385 +#define DWC2_HWCFG1_EP_DIR7_MASK (0x3 << 14)
  386 +#define DWC2_HWCFG1_EP_DIR7_OFFSET 14
  387 +#define DWC2_HWCFG1_EP_DIR8_MASK (0x3 << 16)
  388 +#define DWC2_HWCFG1_EP_DIR8_OFFSET 16
  389 +#define DWC2_HWCFG1_EP_DIR9_MASK (0x3 << 18)
  390 +#define DWC2_HWCFG1_EP_DIR9_OFFSET 18
  391 +#define DWC2_HWCFG1_EP_DIR10_MASK (0x3 << 20)
  392 +#define DWC2_HWCFG1_EP_DIR10_OFFSET 20
  393 +#define DWC2_HWCFG1_EP_DIR11_MASK (0x3 << 22)
  394 +#define DWC2_HWCFG1_EP_DIR11_OFFSET 22
  395 +#define DWC2_HWCFG1_EP_DIR12_MASK (0x3 << 24)
  396 +#define DWC2_HWCFG1_EP_DIR12_OFFSET 24
  397 +#define DWC2_HWCFG1_EP_DIR13_MASK (0x3 << 26)
  398 +#define DWC2_HWCFG1_EP_DIR13_OFFSET 26
  399 +#define DWC2_HWCFG1_EP_DIR14_MASK (0x3 << 28)
  400 +#define DWC2_HWCFG1_EP_DIR14_OFFSET 28
  401 +#define DWC2_HWCFG1_EP_DIR15_MASK (0x3 << 30)
  402 +#define DWC2_HWCFG1_EP_DIR15_OFFSET 30
  403 +#define DWC2_HWCFG2_OP_MODE_MASK (0x7 << 0)
  404 +#define DWC2_HWCFG2_OP_MODE_OFFSET 0
  405 +#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0x0 << 3)
  406 +#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA (0x1 << 3)
  407 +#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA (0x2 << 3)
  408 +#define DWC2_HWCFG2_ARCHITECTURE_MASK (0x3 << 3)
  409 +#define DWC2_HWCFG2_ARCHITECTURE_OFFSET 3
  410 +#define DWC2_HWCFG2_POINT2POINT (1 << 5)
  411 +#define DWC2_HWCFG2_POINT2POINT_OFFSET 5
  412 +#define DWC2_HWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
  413 +#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET 6
  414 +#define DWC2_HWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
  415 +#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET 8
  416 +#define DWC2_HWCFG2_NUM_DEV_EP_MASK (0xF << 10)
  417 +#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET 10
  418 +#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK (0xF << 14)
  419 +#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET 14
  420 +#define DWC2_HWCFG2_PERIO_EP_SUPPORTED (1 << 18)
  421 +#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET 18
  422 +#define DWC2_HWCFG2_DYNAMIC_FIFO (1 << 19)
  423 +#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET 19
  424 +#define DWC2_HWCFG2_MULTI_PROC_INT (1 << 20)
  425 +#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET 20
  426 +#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
  427 +#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET 22
  428 +#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
  429 +#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET 24
  430 +#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1F << 26)
  431 +#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET 26
  432 +#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xF << 0)
  433 +#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET 0
  434 +#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
  435 +#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET 4
  436 +#define DWC2_HWCFG3_OTG_FUNC (1 << 7)
  437 +#define DWC2_HWCFG3_OTG_FUNC_OFFSET 7
  438 +#define DWC2_HWCFG3_I2C (1 << 8)
  439 +#define DWC2_HWCFG3_I2C_OFFSET 8
  440 +#define DWC2_HWCFG3_VENDOR_CTRL_IF (1 << 9)
  441 +#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET 9
  442 +#define DWC2_HWCFG3_OPTIONAL_FEATURES (1 << 10)
  443 +#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET 10
  444 +#define DWC2_HWCFG3_SYNCH_RESET_TYPE (1 << 11)
  445 +#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET 11
  446 +#define DWC2_HWCFG3_OTG_ENABLE_IC_USB (1 << 12)
  447 +#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET 12
  448 +#define DWC2_HWCFG3_OTG_ENABLE_HSIC (1 << 13)
  449 +#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET 13
  450 +#define DWC2_HWCFG3_OTG_LPM_EN (1 << 15)
  451 +#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET 15
  452 +#define DWC2_HWCFG3_DFIFO_DEPTH_MASK (0xFFFF << 16)
  453 +#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET 16
  454 +#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xF << 0)
  455 +#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET 0
  456 +#define DWC2_HWCFG4_POWER_OPTIMIZ (1 << 4)
  457 +#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET 4
  458 +#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK (0x1FF << 5)
  459 +#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET 5
  460 +#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
  461 +#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET 14
  462 +#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xF << 16)
  463 +#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET 16
  464 +#define DWC2_HWCFG4_IDDIG_FILT_EN (1 << 20)
  465 +#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET 20
  466 +#define DWC2_HWCFG4_VBUS_VALID_FILT_EN (1 << 21)
  467 +#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET 21
  468 +#define DWC2_HWCFG4_A_VALID_FILT_EN (1 << 22)
  469 +#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET 22
  470 +#define DWC2_HWCFG4_B_VALID_FILT_EN (1 << 23)
  471 +#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET 23
  472 +#define DWC2_HWCFG4_SESSION_END_FILT_EN (1 << 24)
  473 +#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET 24
  474 +#define DWC2_HWCFG4_DED_FIFO_EN (1 << 25)
  475 +#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET 25
  476 +#define DWC2_HWCFG4_NUM_IN_EPS_MASK (0xF << 26)
  477 +#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET 26
  478 +#define DWC2_HWCFG4_DESC_DMA (1 << 30)
  479 +#define DWC2_HWCFG4_DESC_DMA_OFFSET 30
  480 +#define DWC2_HWCFG4_DESC_DMA_DYN (1 << 31)
  481 +#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET 31
  482 +#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ 0
  483 +#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ 1
  484 +#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ 2
  485 +#define DWC2_HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
  486 +#define DWC2_HCFG_FSLSPCLKSEL_OFFSET 0
  487 +#define DWC2_HCFG_FSLSSUPP (1 << 2)
  488 +#define DWC2_HCFG_FSLSSUPP_OFFSET 2
  489 +#define DWC2_HCFG_DESCDMA (1 << 23)
  490 +#define DWC2_HCFG_DESCDMA_OFFSET 23
  491 +#define DWC2_HCFG_FRLISTEN_MASK (0x3 << 24)
  492 +#define DWC2_HCFG_FRLISTEN_OFFSET 24
  493 +#define DWC2_HCFG_PERSCHEDENA (1 << 26)
  494 +#define DWC2_HCFG_PERSCHEDENA_OFFSET 26
  495 +#define DWC2_HCFG_PERSCHEDSTAT (1 << 27)
  496 +#define DWC2_HCFG_PERSCHEDSTAT_OFFSET 27
  497 +#define DWC2_HFIR_FRINT_MASK (0xFFFF << 0)
  498 +#define DWC2_HFIR_FRINT_OFFSET 0
  499 +#define DWC2_HFNUM_FRNUM_MASK (0xFFFF << 0)
  500 +#define DWC2_HFNUM_FRNUM_OFFSET 0
  501 +#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16)
  502 +#define DWC2_HFNUM_FRREM_OFFSET 16
  503 +#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0)
  504 +#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0
  505 +#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16)
  506 +#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET 16
  507 +#define DWC2_HPTXSTS_PTXQTOP_TERMINATE (1 << 24)
  508 +#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET 24
  509 +#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK (0x3 << 25)
  510 +#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET 25
  511 +#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK (0xF << 27)
  512 +#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET 27
  513 +#define DWC2_HPTXSTS_PTXQTOP_ODD (1 << 31)
  514 +#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET 31
  515 +#define DWC2_HPRT0_PRTCONNSTS (1 << 0)
  516 +#define DWC2_HPRT0_PRTCONNSTS_OFFSET 0
  517 +#define DWC2_HPRT0_PRTCONNDET (1 << 1)
  518 +#define DWC2_HPRT0_PRTCONNDET_OFFSET 1
  519 +#define DWC2_HPRT0_PRTENA (1 << 2)
  520 +#define DWC2_HPRT0_PRTENA_OFFSET 2
  521 +#define DWC2_HPRT0_PRTENCHNG (1 << 3)
  522 +#define DWC2_HPRT0_PRTENCHNG_OFFSET 3
  523 +#define DWC2_HPRT0_PRTOVRCURRACT (1 << 4)
  524 +#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET 4
  525 +#define DWC2_HPRT0_PRTOVRCURRCHNG (1 << 5)
  526 +#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET 5
  527 +#define DWC2_HPRT0_PRTRES (1 << 6)
  528 +#define DWC2_HPRT0_PRTRES_OFFSET 6
  529 +#define DWC2_HPRT0_PRTSUSP (1 << 7)
  530 +#define DWC2_HPRT0_PRTSUSP_OFFSET 7
  531 +#define DWC2_HPRT0_PRTRST (1 << 8)
  532 +#define DWC2_HPRT0_PRTRST_OFFSET 8
  533 +#define DWC2_HPRT0_PRTLNSTS_MASK (0x3 << 10)
  534 +#define DWC2_HPRT0_PRTLNSTS_OFFSET 10
  535 +#define DWC2_HPRT0_PRTPWR (1 << 12)
  536 +#define DWC2_HPRT0_PRTPWR_OFFSET 12
  537 +#define DWC2_HPRT0_PRTTSTCTL_MASK (0xF << 13)
  538 +#define DWC2_HPRT0_PRTTSTCTL_OFFSET 13
  539 +#define DWC2_HPRT0_PRTSPD_MASK (0x3 << 17)
  540 +#define DWC2_HPRT0_PRTSPD_OFFSET 17
  541 +#define DWC2_HAINT_CH0 (1 << 0)
  542 +#define DWC2_HAINT_CH0_OFFSET 0
  543 +#define DWC2_HAINT_CH1 (1 << 1)
  544 +#define DWC2_HAINT_CH1_OFFSET 1
  545 +#define DWC2_HAINT_CH2 (1 << 2)
  546 +#define DWC2_HAINT_CH2_OFFSET 2
  547 +#define DWC2_HAINT_CH3 (1 << 3)
  548 +#define DWC2_HAINT_CH3_OFFSET 3
  549 +#define DWC2_HAINT_CH4 (1 << 4)
  550 +#define DWC2_HAINT_CH4_OFFSET 4
  551 +#define DWC2_HAINT_CH5 (1 << 5)
  552 +#define DWC2_HAINT_CH5_OFFSET 5
  553 +#define DWC2_HAINT_CH6 (1 << 6)
  554 +#define DWC2_HAINT_CH6_OFFSET 6
  555 +#define DWC2_HAINT_CH7 (1 << 7)
  556 +#define DWC2_HAINT_CH7_OFFSET 7
  557 +#define DWC2_HAINT_CH8 (1 << 8)
  558 +#define DWC2_HAINT_CH8_OFFSET 8
  559 +#define DWC2_HAINT_CH9 (1 << 9)
  560 +#define DWC2_HAINT_CH9_OFFSET 9
  561 +#define DWC2_HAINT_CH10 (1 << 10)
  562 +#define DWC2_HAINT_CH10_OFFSET 10
  563 +#define DWC2_HAINT_CH11 (1 << 11)
  564 +#define DWC2_HAINT_CH11_OFFSET 11
  565 +#define DWC2_HAINT_CH12 (1 << 12)
  566 +#define DWC2_HAINT_CH12_OFFSET 12
  567 +#define DWC2_HAINT_CH13 (1 << 13)
  568 +#define DWC2_HAINT_CH13_OFFSET 13
  569 +#define DWC2_HAINT_CH14 (1 << 14)
  570 +#define DWC2_HAINT_CH14_OFFSET 14
  571 +#define DWC2_HAINT_CH15 (1 << 15)
  572 +#define DWC2_HAINT_CH15_OFFSET 15
  573 +#define DWC2_HAINT_CHINT_MASK 0xffff
  574 +#define DWC2_HAINT_CHINT_OFFSET 0
  575 +#define DWC2_HAINTMSK_CH0 (1 << 0)
  576 +#define DWC2_HAINTMSK_CH0_OFFSET 0
  577 +#define DWC2_HAINTMSK_CH1 (1 << 1)
  578 +#define DWC2_HAINTMSK_CH1_OFFSET 1
  579 +#define DWC2_HAINTMSK_CH2 (1 << 2)
  580 +#define DWC2_HAINTMSK_CH2_OFFSET 2
  581 +#define DWC2_HAINTMSK_CH3 (1 << 3)
  582 +#define DWC2_HAINTMSK_CH3_OFFSET 3
  583 +#define DWC2_HAINTMSK_CH4 (1 << 4)
  584 +#define DWC2_HAINTMSK_CH4_OFFSET 4
  585 +#define DWC2_HAINTMSK_CH5 (1 << 5)
  586 +#define DWC2_HAINTMSK_CH5_OFFSET 5
  587 +#define DWC2_HAINTMSK_CH6 (1 << 6)
  588 +#define DWC2_HAINTMSK_CH6_OFFSET 6
  589 +#define DWC2_HAINTMSK_CH7 (1 << 7)
  590 +#define DWC2_HAINTMSK_CH7_OFFSET 7
  591 +#define DWC2_HAINTMSK_CH8 (1 << 8)
  592 +#define DWC2_HAINTMSK_CH8_OFFSET 8
  593 +#define DWC2_HAINTMSK_CH9 (1 << 9)
  594 +#define DWC2_HAINTMSK_CH9_OFFSET 9
  595 +#define DWC2_HAINTMSK_CH10 (1 << 10)
  596 +#define DWC2_HAINTMSK_CH10_OFFSET 10
  597 +#define DWC2_HAINTMSK_CH11 (1 << 11)
  598 +#define DWC2_HAINTMSK_CH11_OFFSET 11
  599 +#define DWC2_HAINTMSK_CH12 (1 << 12)
  600 +#define DWC2_HAINTMSK_CH12_OFFSET 12
  601 +#define DWC2_HAINTMSK_CH13 (1 << 13)
  602 +#define DWC2_HAINTMSK_CH13_OFFSET 13
  603 +#define DWC2_HAINTMSK_CH14 (1 << 14)
  604 +#define DWC2_HAINTMSK_CH14_OFFSET 14
  605 +#define DWC2_HAINTMSK_CH15 (1 << 15)
  606 +#define DWC2_HAINTMSK_CH15_OFFSET 15
  607 +#define DWC2_HAINTMSK_CHINT_MASK 0xffff
  608 +#define DWC2_HAINTMSK_CHINT_OFFSET 0
  609 +#define DWC2_HCCHAR_MPS_MASK (0x7FF << 0)
  610 +#define DWC2_HCCHAR_MPS_OFFSET 0
  611 +#define DWC2_HCCHAR_EPNUM_MASK (0xF << 11)
  612 +#define DWC2_HCCHAR_EPNUM_OFFSET 11
  613 +#define DWC2_HCCHAR_EPDIR (1 << 15)
  614 +#define DWC2_HCCHAR_EPDIR_OFFSET 15
  615 +#define DWC2_HCCHAR_LSPDDEV (1 << 17)
  616 +#define DWC2_HCCHAR_LSPDDEV_OFFSET 17
  617 +#define DWC2_HCCHAR_EPTYPE_CONTROL 0
  618 +#define DWC2_HCCHAR_EPTYPE_ISOC 1
  619 +#define DWC2_HCCHAR_EPTYPE_BULK 2
  620 +#define DWC2_HCCHAR_EPTYPE_INTR 3
  621 +#define DWC2_HCCHAR_EPTYPE_MASK (0x3 << 18)
  622 +#define DWC2_HCCHAR_EPTYPE_OFFSET 18
  623 +#define DWC2_HCCHAR_MULTICNT_MASK (0x3 << 20)
  624 +#define DWC2_HCCHAR_MULTICNT_OFFSET 20
  625 +#define DWC2_HCCHAR_DEVADDR_MASK (0x7F << 22)
  626 +#define DWC2_HCCHAR_DEVADDR_OFFSET 22
  627 +#define DWC2_HCCHAR_ODDFRM (1 << 29)
  628 +#define DWC2_HCCHAR_ODDFRM_OFFSET 29
  629 +#define DWC2_HCCHAR_CHDIS (1 << 30)
  630 +#define DWC2_HCCHAR_CHDIS_OFFSET 30
  631 +#define DWC2_HCCHAR_CHEN (1 << 31)
  632 +#define DWC2_HCCHAR_CHEN_OFFSET 31
  633 +#define DWC2_HCSPLT_PRTADDR_MASK (0x7F << 0)
  634 +#define DWC2_HCSPLT_PRTADDR_OFFSET 0
  635 +#define DWC2_HCSPLT_HUBADDR_MASK (0x7F << 7)
  636 +#define DWC2_HCSPLT_HUBADDR_OFFSET 7
  637 +#define DWC2_HCSPLT_XACTPOS_MASK (0x3 << 14)
  638 +#define DWC2_HCSPLT_XACTPOS_OFFSET 14
  639 +#define DWC2_HCSPLT_COMPSPLT (1 << 16)
  640 +#define DWC2_HCSPLT_COMPSPLT_OFFSET 16
  641 +#define DWC2_HCSPLT_SPLTENA (1 << 31)
  642 +#define DWC2_HCSPLT_SPLTENA_OFFSET 31
  643 +#define DWC2_HCINT_XFERCOMP (1 << 0)
  644 +#define DWC2_HCINT_XFERCOMP_OFFSET 0
  645 +#define DWC2_HCINT_CHHLTD (1 << 1)
  646 +#define DWC2_HCINT_CHHLTD_OFFSET 1
  647 +#define DWC2_HCINT_AHBERR (1 << 2)
  648 +#define DWC2_HCINT_AHBERR_OFFSET 2
  649 +#define DWC2_HCINT_STALL (1 << 3)
  650 +#define DWC2_HCINT_STALL_OFFSET 3
  651 +#define DWC2_HCINT_NAK (1 << 4)
  652 +#define DWC2_HCINT_NAK_OFFSET 4
  653 +#define DWC2_HCINT_ACK (1 << 5)
  654 +#define DWC2_HCINT_ACK_OFFSET 5
  655 +#define DWC2_HCINT_NYET (1 << 6)
  656 +#define DWC2_HCINT_NYET_OFFSET 6
  657 +#define DWC2_HCINT_XACTERR (1 << 7)
  658 +#define DWC2_HCINT_XACTERR_OFFSET 7
  659 +#define DWC2_HCINT_BBLERR (1 << 8)
  660 +#define DWC2_HCINT_BBLERR_OFFSET 8
  661 +#define DWC2_HCINT_FRMOVRUN (1 << 9)
  662 +#define DWC2_HCINT_FRMOVRUN_OFFSET 9
  663 +#define DWC2_HCINT_DATATGLERR (1 << 10)
  664 +#define DWC2_HCINT_DATATGLERR_OFFSET 10
  665 +#define DWC2_HCINT_BNA (1 << 11)
  666 +#define DWC2_HCINT_BNA_OFFSET 11
  667 +#define DWC2_HCINT_XCS_XACT (1 << 12)
  668 +#define DWC2_HCINT_XCS_XACT_OFFSET 12
  669 +#define DWC2_HCINT_FRM_LIST_ROLL (1 << 13)
  670 +#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET 13
  671 +#define DWC2_HCINTMSK_XFERCOMPL (1 << 0)
  672 +#define DWC2_HCINTMSK_XFERCOMPL_OFFSET 0
  673 +#define DWC2_HCINTMSK_CHHLTD (1 << 1)
  674 +#define DWC2_HCINTMSK_CHHLTD_OFFSET 1
  675 +#define DWC2_HCINTMSK_AHBERR (1 << 2)
  676 +#define DWC2_HCINTMSK_AHBERR_OFFSET 2
  677 +#define DWC2_HCINTMSK_STALL (1 << 3)
  678 +#define DWC2_HCINTMSK_STALL_OFFSET 3
  679 +#define DWC2_HCINTMSK_NAK (1 << 4)
  680 +#define DWC2_HCINTMSK_NAK_OFFSET 4
  681 +#define DWC2_HCINTMSK_ACK (1 << 5)
  682 +#define DWC2_HCINTMSK_ACK_OFFSET 5
  683 +#define DWC2_HCINTMSK_NYET (1 << 6)
  684 +#define DWC2_HCINTMSK_NYET_OFFSET 6
  685 +#define DWC2_HCINTMSK_XACTERR (1 << 7)
  686 +#define DWC2_HCINTMSK_XACTERR_OFFSET 7
  687 +#define DWC2_HCINTMSK_BBLERR (1 << 8)
  688 +#define DWC2_HCINTMSK_BBLERR_OFFSET 8
  689 +#define DWC2_HCINTMSK_FRMOVRUN (1 << 9)
  690 +#define DWC2_HCINTMSK_FRMOVRUN_OFFSET 9
  691 +#define DWC2_HCINTMSK_DATATGLERR (1 << 10)
  692 +#define DWC2_HCINTMSK_DATATGLERR_OFFSET 10
  693 +#define DWC2_HCINTMSK_BNA (1 << 11)
  694 +#define DWC2_HCINTMSK_BNA_OFFSET 11
  695 +#define DWC2_HCINTMSK_XCS_XACT (1 << 12)
  696 +#define DWC2_HCINTMSK_XCS_XACT_OFFSET 12
  697 +#define DWC2_HCINTMSK_FRM_LIST_ROLL (1 << 13)
  698 +#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET 13
  699 +#define DWC2_HCTSIZ_XFERSIZE_MASK 0x7ffff
  700 +#define DWC2_HCTSIZ_XFERSIZE_OFFSET 0
  701 +#define DWC2_HCTSIZ_SCHINFO_MASK 0xff
  702 +#define DWC2_HCTSIZ_SCHINFO_OFFSET 0
  703 +#define DWC2_HCTSIZ_NTD_MASK (0xff << 8)
  704 +#define DWC2_HCTSIZ_NTD_OFFSET 8
  705 +#define DWC2_HCTSIZ_PKTCNT_MASK (0x3ff << 19)
  706 +#define DWC2_HCTSIZ_PKTCNT_OFFSET 19
  707 +#define DWC2_HCTSIZ_PID_MASK (0x3 << 29)
  708 +#define DWC2_HCTSIZ_PID_OFFSET 29
  709 +#define DWC2_HCTSIZ_DOPNG (1 << 31)
  710 +#define DWC2_HCTSIZ_DOPNG_OFFSET 31
  711 +#define DWC2_HCDMA_CTD_MASK (0xFF << 3)
  712 +#define DWC2_HCDMA_CTD_OFFSET 3
  713 +#define DWC2_HCDMA_DMA_ADDR_MASK (0x1FFFFF << 11)
  714 +#define DWC2_HCDMA_DMA_ADDR_OFFSET 11
  715 +#define DWC2_PCGCCTL_STOPPCLK (1 << 0)
  716 +#define DWC2_PCGCCTL_STOPPCLK_OFFSET 0
  717 +#define DWC2_PCGCCTL_GATEHCLK (1 << 1)
  718 +#define DWC2_PCGCCTL_GATEHCLK_OFFSET 1
  719 +#define DWC2_PCGCCTL_PWRCLMP (1 << 2)
  720 +#define DWC2_PCGCCTL_PWRCLMP_OFFSET 2
  721 +#define DWC2_PCGCCTL_RSTPDWNMODULE (1 << 3)
  722 +#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET 3
  723 +#define DWC2_PCGCCTL_PHYSUSPENDED (1 << 4)
  724 +#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET 4
  725 +#define DWC2_PCGCCTL_ENBL_SLEEP_GATING (1 << 5)
  726 +#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET 5
  727 +#define DWC2_PCGCCTL_PHY_IN_SLEEP (1 << 6)
  728 +#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET 6
  729 +#define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7)
  730 +#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7
  731 +#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
  732 +#define DWC2_SNPSID_DEVID_MASK (0xfffff << 12)
  733 +#define DWC2_SNPSID_DEVID_OFFSET 12
  734 +
  735 +/* Host controller specific */
  736 +#define DWC2_HC_PID_DATA0 0
  737 +#define DWC2_HC_PID_DATA2 1
  738 +#define DWC2_HC_PID_DATA1 2
  739 +#define DWC2_HC_PID_MDATA 3
  740 +#define DWC2_HC_PID_SETUP 3
  741 +
  742 +/* roothub.a masks */
  743 +#define RH_A_NDP (0xff << 0) /* number of downstream ports */
  744 +#define RH_A_PSM (1 << 8) /* power switching mode */
  745 +#define RH_A_NPS (1 << 9) /* no power switching */
  746 +#define RH_A_DT (1 << 10) /* device type (mbz) */
  747 +#define RH_A_OCPM (1 << 11) /* over current protection mode */
  748 +#define RH_A_NOCP (1 << 12) /* no over current protection */
  749 +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
  750 +
  751 +/* roothub.b masks */
  752 +#define RH_B_DR 0x0000ffff /* device removable flags */
  753 +#define RH_B_PPCM 0xffff0000 /* port power control mask */
  754 +
  755 +/* Default driver configuration */
  756 +#define CONFIG_DWC2_DMA_ENABLE
  757 +#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
  758 +#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
  759 +#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
  760 +#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */
  761 +#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS)
  762 +#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
  763 +#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
  764 +#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535
  765 +#define CONFIG_DWC2_MAX_PACKET_COUNT 511
  766 +
  767 +#define DWC2_PHY_TYPE_FS 0
  768 +#define DWC2_PHY_TYPE_UTMI 1
  769 +#define DWC2_PHY_TYPE_ULPI 2
  770 +#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
  771 +#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
  772 +
  773 +#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
  774 +#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
  775 +#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */
  776 +#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */
  777 +#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */
  778 +#undef CONFIG_DWC2_THR_CTL /* Threshold control */
  779 +#define CONFIG_DWC2_TX_THR_LENGTH 64
  780 +#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */
  781 +
  782 +#endif /* __DWC2_H__ */
... ... @@ -150,7 +150,8 @@
150 150 defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
151 151 defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
152 152 defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
153   - defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI)
  153 + defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) || \
  154 + defined(CONFIG_USB_DWC2)
154 155  
155 156 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
156 157 int usb_lowlevel_stop(int index);