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Commit 6eefd5279c4e80d613420066364ec3c8ba551a56

Authored by David Feng
Committed by Tom Rini
1 parent af21f2fb6f
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

PCI: add 64-bit prefetchable memory support 

PCI specification allow prefetchable memory to be 32-bit or 64-bit.
PCI express specification states that all memmory bars for prefetchable
memory must be implemented as 64-bit. They all require that 64 bit
prefetchble memory are suported especially when u-boot is ported to
more and more 64bit processors.

Signed-off-by: David Feng <fenghua@phytium.com.cn>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 1 changed file with 35 additions and 1 deletions Side-by-side Diff

drivers/pci/pci_auto.c
Diff comments   View file @ 6eefd52
... ... @@ -223,9 +223,12 @@
223 223 struct pci_region *pci_mem = hose->pci_mem;
224 224 struct pci_region *pci_prefetch = hose->pci_prefetch;
225 225 struct pci_region *pci_io = hose->pci_io;
226   - u16 cmdstat;
  226 + u16 cmdstat, prefechable_64;
227 227  
228 228 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  229 + pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
  230 + &prefechable_64);
  231 + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
229 232  
230 233 /* Configure bus number registers */
231 234 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
232 235  
... ... @@ -252,12 +255,26 @@
252 255 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
253 256 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
254 257 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
  258 + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  259 +#ifdef CONFIG_SYS_PCI_64BIT
  260 + pci_hose_write_config_dword(hose, dev,
  261 + PCI_PREF_BASE_UPPER32,
  262 + pci_prefetch->bus_lower >> 32);
  263 +#else
  264 + pci_hose_write_config_dword(hose, dev,
  265 + PCI_PREF_BASE_UPPER32,
  266 + 0x0);
  267 +#endif
255 268  
256 269 cmdstat |= PCI_COMMAND_MEMORY;
257 270 } else {
258 271 /* We don't support prefetchable memory for now, so disable */
259 272 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
260 273 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
  274 + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
  275 + pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
  276 + pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  277 + }
261 278 }
262 279  
263 280 if (pci_io) {
264 281  
... ... @@ -297,11 +314,28 @@
297 314 }
298 315  
299 316 if (pci_prefetch) {
  317 + u16 prefechable_64;
  318 +
  319 + pci_hose_read_config_word(hose, dev,
  320 + PCI_PREF_MEMORY_LIMIT,
  321 + &prefechable_64);
  322 + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  323 +
300 324 /* Round memory allocator to 1MB boundary */
301 325 pciauto_region_align(pci_prefetch, 0x100000);
302 326  
303 327 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
304 328 (pci_prefetch->bus_lower - 1) >> 16);
  329 + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  330 +#ifdef CONFIG_SYS_PCI_64BIT
  331 + pci_hose_write_config_dword(hose, dev,
  332 + PCI_PREF_LIMIT_UPPER32,
  333 + (pci_prefetch->bus_lower - 1) >> 32);
  334 +#else
  335 + pci_hose_write_config_dword(hose, dev,
  336 + PCI_PREF_LIMIT_UPPER32,
  337 + 0x0);
  338 +#endif
305 339 }
306 340  
307 341 if (pci_io) {