Eric Lee / smarc-uboot

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Commit 6f21347d49b1741e4b8247f5e2d3fa83ef169c25

Authored by wdenk
1 parent c29fdfc1d8
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by George G. Davis, 19 Aug 2003: 

fix TI Innovator/OMAP1510 pin configs

* Patches by Kshitij, 18 Aug 2003
  - add support for arm926ejs cpu core
  - add support for TI OMAP 1610 Innovator Board

Showing 25 changed files with 2490 additions and 9 deletions Side-by-side Diff

... ... @@ -2,6 +2,13 @@
2 2 Changes for U-Boot 0.4.7:
3 3 ======================================================================
4 4  
  5 +* Patch by George G. Davis, 19 Aug 2003:
  6 + fix TI Innovator/OMAP1510 pin configs
  7 +
  8 +* Patches by Kshitij, 18 Aug 2003
  9 + - add support for arm926ejs cpu core
  10 + - add support for TI OMAP 1610 Innovator Board
  11 +
5 12 * Patch by Yuli Barcohen, 14 Aug 2003:
6 13 add support for bzip2 uncompression
7 14  
... ... @@ -278,6 +278,7 @@
278 278  
279 279 Kshitij Gupta <kshitij@ti.com>
280 280 omap1510inn ARM925T
  281 + omap1610inn ARM926EJS
281 282  
282 283 David Müller <d.mueller@elsoft.ch>
283 284  
... ... @@ -117,7 +117,11 @@
117 117 ## ARM9 Systems
118 118 #########################################################################
119 119  
120   -LIST_ARM9="at91rm9200dk omap1510inn smdk2400 smdk2410 trab VCMA9"
  120 +LIST_ARM9=" \
  121 + at91rm9200dk omap1510inn omap1610inn \
  122 + smdk2400 smdk2410 trab \
  123 + VCMA9 \
  124 +"
121 125  
122 126 #########################################################################
123 127 ## Xscale Systems
... ... @@ -776,6 +776,9 @@
776 776 omap1510inn_config : unconfig
777 777 @./mkconfig $(@:_config=) arm arm925t omap1510inn
778 778  
  779 +omap1610inn_config : unconfig
  780 + @./mkconfig $(@:_config=) arm arm926ejs omap1610inn
  781 +
779 782 smdk2400_config : unconfig
780 783 @./mkconfig $(@:_config=) arm arm920t smdk2400
781 784  
... ... @@ -141,6 +141,7 @@
141 141  
142 142 - cpu/74xx_7xx Files specific to Motorola MPC74xx and 7xx CPUs
143 143 - cpu/arm925t Files specific to ARM 925 CPUs
  144 +- cpu/arm926ejs Files specific to ARM 926 CPUs
144 145 - cpu/mpc5xx Files specific to Motorola MPC5xx CPUs
145 146 - cpu/mpc8xx Files specific to Motorola MPC8xx CPUs
146 147 - cpu/mpc824x Files specific to Motorola MPC824x CPUs
... ... @@ -208,6 +209,8 @@
208 209 - board/oxc Files specific to OXC boards
209 210 - board/omap1510inn
210 211 Files specific to OMAP 1510 Innovator boards
  212 +- board/omap1610inn
  213 + Files specific to OMAP 1610 Innovator boards
211 214 - board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
212 215 - board/pm826 Files specific to PM826 boards
213 216 - board/ppmc8260
... ... @@ -357,7 +360,7 @@
357 360  
358 361 CONFIG_HHP_CRADLE, CONFIG_DNP1110, CONFIG_EP7312,
359 362 CONFIG_IMPA7, CONFIG_LART, CONFIG_LUBBOCK,
360   - CONFIG_INNOVATOROMAP1510,
  363 + CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610
361 364 CONFIG_SHANNON, CONFIG_SMDK2400, CONFIG_SMDK2410,
362 365 CONFIG_TRAB, CONFIG_AT91RM9200DK
363 366  
... ... @@ -1905,7 +1908,7 @@
1905 1908 GEN860T_config EBONY_config FPS860L_config
1906 1909 ELPT860_config cmi_mpc5xx_config NETVIA_config
1907 1910 at91rm9200dk_config omap1510inn_config MPC8260ADS_config
1908   -
  1911 + omap1610inn_config
1909 1912 Note: for some board special configuration names may exist; check if
1910 1913 additional information is available from the board vendor; for
1911 1914 instance, the TQM8xxL systems run normally at 50 MHz and use a
board/omap1510inn/platform.S
Diff comments   View file @ 6f21347
... ... @@ -84,6 +84,9 @@
84 84 ldr r0, REG_FUNC_MUX_CTRL_C
85 85 ldr r1, VAL_FUNC_MUX_CTRL_C
86 86 str r1, [r0]
  87 + ldr r0, REG_FUNC_MUX_CTRL_D
  88 + ldr r1, VAL_FUNC_MUX_CTRL_D
  89 + str r1, [r0]
87 90 ldr r0, REG_VOLTAGE_CTRL_0
88 91 ldr r1, VAL_VOLTAGE_CTRL_0
89 92 str r1, [r0]
90 93  
... ... @@ -352,9 +355,9 @@
352 355 VAL_PULL_DWN_CTRL_1:
353 356 .word 0x2e047fff
354 357 VAL_PULL_DWN_CTRL_2:
355   - .word 0xffd7d3e6
  358 + .word 0xffd603a6
356 359 VAL_PULL_DWN_CTRL_3:
357   - .word 0x00003f03
  360 + .word 0x00003e03
358 361 VAL_VOLTAGE_CTRL_0:
359 362 .word 0x00000007
360 363 VAL_TEST_DBG_CTRL_0:
board/omap1610inn/Makefile
Diff comments   View file @ 6f21347
  1 +#
  2 +# (C) Copyright 2000, 2001, 2002
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS := omap1610innovator.o flash.o
  29 +SOBJS := platform.o
  30 +
  31 +$(LIB): $(OBJS) $(SOBJS)
  32 + $(AR) crv $@ $^
  33 +
  34 +clean:
  35 + rm -f $(SOBJS) $(OBJS)
  36 +
  37 +distclean: clean
  38 + rm -f $(LIB) core *.bak .depend
  39 +
  40 +#########################################################################
  41 +
  42 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  43 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  44 +
  45 +-include .depend
  46 +
  47 +#########################################################################
board/omap1610inn/config.mk
Diff comments   View file @ 6f21347
  1 +#
  2 +# (C) Copyright 2002
  3 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  4 +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  5 +#
  6 +# (C) Copyright 2003
  7 +# Texas Instruments, <www.ti.com>
  8 +# Kshitij Gupta <Kshitij@ti.com>
  9 +#
  10 +# TI Innovator board with OMAP1610 (ARM925EJS) cpu
  11 +# see http://www.ti.com/ for more information on Texas Instruments
  12 +#
  13 +# Innovator has 1 bank of 256 MB SDRAM
  14 +# Physical Address:
  15 +# 1000'0000 to 2000'0000
  16 +#
  17 +#
  18 +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
  19 +# (mem base + reserved)
  20 +#
  21 +# we load ourself to 1100'0000
  22 +#
  23 +#
  24 +
  25 +
  26 +TEXT_BASE = 0x11000000
board/omap1610inn/flash.c
Diff comments   View file @ 6f21347
  1 +/*
  2 + * (C) Copyright 2001
  3 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  4 + *
  5 + * (C) Copyright 2001
  6 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7 + *
  8 + * (C) Copyright 2003
  9 + * Texas Instruments, <www.ti.com>
  10 + * Kshitij Gupta <Kshitij@ti.com>
  11 + *
  12 + * See file CREDITS for list of people who contributed to this
  13 + * project.
  14 + *
  15 + * This program is free software; you can redistribute it and/or
  16 + * modify it under the terms of the GNU General Public License as
  17 + * published by the Free Software Foundation; either version 2 of
  18 + * the License, or (at your option) any later version.
  19 + *
  20 + * This program is distributed in the hope that it will be useful,
  21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23 + * GNU General Public License for more details.
  24 + *
  25 + * You should have received a copy of the GNU General Public License
  26 + * along with this program; if not, write to the Free Software
  27 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 + * MA 02111-1307 USA
  29 + */
  30 +
  31 +#include <common.h>
  32 +#include <linux/byteorder/swab.h>
  33 +
  34 +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
  35 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  36 +
  37 +/* Board support for 1 or 2 flash devices */
  38 +#undef FLASH_PORT_WIDTH32
  39 +#define FLASH_PORT_WIDTH16
  40 +
  41 +#ifdef FLASH_PORT_WIDTH16
  42 +#define FLASH_PORT_WIDTH ushort
  43 +#define FLASH_PORT_WIDTHV vu_short
  44 +#define SWAP(x) __swab16(x)
  45 +#else
  46 +#define FLASH_PORT_WIDTH ulong
  47 +#define FLASH_PORT_WIDTHV vu_long
  48 +#define SWAP(x) __swab32(x)
  49 +#endif
  50 +
  51 +#define FPW FLASH_PORT_WIDTH
  52 +#define FPWV FLASH_PORT_WIDTHV
  53 +
  54 +#define mb() __asm__ __volatile__ ("" : : : "memory")
  55 +
  56 +
  57 +
  58 +/* Flash Organization Structure */
  59 +typedef struct OrgDef {
  60 + unsigned int sector_number;
  61 + unsigned int sector_size;
  62 +} OrgDef;
  63 +
  64 +
  65 +/* Flash Organizations */
  66 +OrgDef OrgIntel_28F256L18T[] = {
  67 + {4, 32 * 1024}, /* 4 * 32kBytes sectors */
  68 + {255, 128 * 1024}, /* 255 * 128kBytes sectors */
  69 +};
  70 +
  71 +
  72 +/*-----------------------------------------------------------------------
  73 + * Functions
  74 + */
  75 +unsigned long flash_init (void);
  76 +static ulong flash_get_size (FPW * addr, flash_info_t * info);
  77 +static int write_data (flash_info_t * info, ulong dest, FPW data);
  78 +static void flash_get_offsets (ulong base, flash_info_t * info);
  79 +void inline spin_wheel (void);
  80 +void flash_print_info (flash_info_t * info);
  81 +void flash_unprotect_sectors (FPWV * addr);
  82 +int flash_erase (flash_info_t * info, int s_first, int s_last);
  83 +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
  84 +
  85 +/*-----------------------------------------------------------------------
  86 + */
  87 +
  88 +unsigned long flash_init (void)
  89 +{
  90 + int i;
  91 + ulong size = 0;
  92 + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
  93 + switch (i) {
  94 + case 0:
  95 + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
  96 + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
  97 + break;
  98 + default:
  99 + panic ("configured to many flash banks!\n");
  100 + break;
  101 + }
  102 + size += flash_info[i].size;
  103 + }
  104 +
  105 + /* Protect monitor and environment sectors
  106 + */
  107 + flash_protect (FLAG_PROTECT_SET,
  108 + CFG_FLASH_BASE,
  109 + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
  110 +
  111 + flash_protect (FLAG_PROTECT_SET,
  112 + CFG_ENV_ADDR,
  113 + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
  114 +
  115 + return size;
  116 +}
  117 +
  118 +/*-----------------------------------------------------------------------
  119 + */
  120 +static void flash_get_offsets (ulong base, flash_info_t * info)
  121 +{
  122 + int i;
  123 + OrgDef *pOrgDef;
  124 +
  125 + pOrgDef = OrgIntel_28F256L18T;
  126 + if (info->flash_id == FLASH_UNKNOWN) {
  127 + return;
  128 + }
  129 +
  130 + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
  131 + for (i = 0; i < info->sector_count; i++) {
  132 + if (i > 255) {
  133 + info->start[i] = base + (i * 0x8000);
  134 + info->protect[i] = 0;
  135 + } else {
  136 + info->start[i] = base +
  137 + (i * PHYS_FLASH_SECT_SIZE);
  138 + info->protect[i] = 0;
  139 + }
  140 + }
  141 + }
  142 +}
  143 +
  144 +/*-----------------------------------------------------------------------
  145 + */
  146 +void flash_print_info (flash_info_t * info)
  147 +{
  148 + int i;
  149 +
  150 + if (info->flash_id == FLASH_UNKNOWN) {
  151 + printf ("missing or unknown FLASH type\n");
  152 + return;
  153 + }
  154 +
  155 + switch (info->flash_id & FLASH_VENDMASK) {
  156 + case FLASH_MAN_INTEL:
  157 + printf ("INTEL ");
  158 + break;
  159 + default:
  160 + printf ("Unknown Vendor ");
  161 + break;
  162 + }
  163 +
  164 + switch (info->flash_id & FLASH_TYPEMASK) {
  165 + case FLASH_28F256L18T:
  166 + printf ("FLASH 28F256L18T\n");
  167 + break;
  168 + default:
  169 + printf ("Unknown Chip Type\n");
  170 + break;
  171 + }
  172 +
  173 + printf (" Size: %ld MB in %d Sectors\n",
  174 + info->size >> 20, info->sector_count);
  175 +
  176 + printf (" Sector Start Addresses:");
  177 + for (i = 0; i < info->sector_count; ++i) {
  178 + if ((i % 5) == 0)
  179 + printf ("\n ");
  180 + printf (" %08lX%s",
  181 + info->start[i], info->protect[i] ? " (RO)" : " ");
  182 + }
  183 + printf ("\n");
  184 + return;
  185 +}
  186 +
  187 +/*
  188 + * The following code cannot be run from FLASH!
  189 + */
  190 +static ulong flash_get_size (FPW * addr, flash_info_t * info)
  191 +{
  192 + volatile FPW value;
  193 +
  194 + /* Write auto select command: read Manufacturer ID */
  195 + addr[0x5555] = (FPW) 0x00AA00AA;
  196 + addr[0x2AAA] = (FPW) 0x00550055;
  197 + addr[0x5555] = (FPW) 0x00900090;
  198 +
  199 + mb ();
  200 + value = addr[0];
  201 +
  202 + switch (value) {
  203 +
  204 + case (FPW) INTEL_MANUFACT:
  205 + info->flash_id = FLASH_MAN_INTEL;
  206 + break;
  207 +
  208 + default:
  209 + info->flash_id = FLASH_UNKNOWN;
  210 + info->sector_count = 0;
  211 + info->size = 0;
  212 + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
  213 + return (0); /* no or unknown flash */
  214 + }
  215 +
  216 + mb ();
  217 + value = addr[1]; /* device ID */
  218 + switch (value) {
  219 +
  220 + case (FPW) (INTEL_ID_28F256L18T):
  221 + info->flash_id += FLASH_28F256L18T;
  222 + info->sector_count = 259;
  223 + info->size = 0x02000000;
  224 + break; /* => 32 MB */
  225 +
  226 + default:
  227 + info->flash_id = FLASH_UNKNOWN;
  228 + break;
  229 + }
  230 +
  231 + if (info->sector_count > CFG_MAX_FLASH_SECT) {
  232 + printf ("** ERROR: sector count %d > max (%d) **\n",
  233 + info->sector_count, CFG_MAX_FLASH_SECT);
  234 + info->sector_count = CFG_MAX_FLASH_SECT;
  235 + }
  236 +
  237 + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
  238 +
  239 + return (info->size);
  240 +}
  241 +
  242 +
  243 +
  244 +
  245 +/* unprotects a sector for write and erase
  246 + * on some intel parts, this unprotects the entire chip, but it
  247 + * wont hurt to call this additional times per sector...
  248 + */
  249 +void flash_unprotect_sectors (FPWV * addr)
  250 +{
  251 +#define PD_FINTEL_WSMS_READY_MASK 0x0080
  252 +
  253 + *addr = (FPW) 0x00500050; /* clear status register */
  254 +
  255 + /* this sends the clear lock bit command */
  256 + *addr = (FPW) 0x00600060;
  257 + *addr = (FPW) 0x00D000D0;
  258 +}
  259 +
  260 +
  261 +/*-----------------------------------------------------------------------
  262 + */
  263 +
  264 +int flash_erase (flash_info_t * info, int s_first, int s_last)
  265 +{
  266 + int flag, prot, sect;
  267 + ulong type, start, last;
  268 + int rcode = 0;
  269 +
  270 + if ((s_first < 0) || (s_first > s_last)) {
  271 + if (info->flash_id == FLASH_UNKNOWN) {
  272 + printf ("- missing\n");
  273 + } else {
  274 + printf ("- no sectors to erase\n");
  275 + }
  276 + return 1;
  277 + }
  278 +
  279 + type = (info->flash_id & FLASH_VENDMASK);
  280 + if ((type != FLASH_MAN_INTEL)) {
  281 + printf ("Can't erase unknown flash type %08lx - aborted\n",
  282 + info->flash_id);
  283 + return 1;
  284 + }
  285 +
  286 + prot = 0;
  287 + for (sect = s_first; sect <= s_last; ++sect) {
  288 + if (info->protect[sect]) {
  289 + prot++;
  290 + }
  291 + }
  292 +
  293 + if (prot) {
  294 + printf ("- Warning: %d protected sectors will not be erased!\n",
  295 + prot);
  296 + } else {
  297 + printf ("\n");
  298 + }
  299 +
  300 +
  301 +
  302 +
  303 + start = get_timer (0);
  304 + last = start;
  305 +
  306 + /* Disable interrupts which might cause a timeout here */
  307 + flag = disable_interrupts ();
  308 +
  309 + /* Start erase on unprotected sectors */
  310 + for (sect = s_first; sect <= s_last; sect++) {
  311 + if (info->protect[sect] == 0) { /* not protected */
  312 + FPWV *addr = (FPWV *) (info->start[sect]);
  313 + FPW status;
  314 +
  315 + printf ("Erasing sector %2d ... ", sect);
  316 +
  317 + flash_unprotect_sectors (addr);
  318 +
  319 + /* arm simple, non interrupt dependent timer */
  320 + reset_timer_masked ();
  321 +
  322 + *addr = (FPW) 0x00500050;/* clear status register */
  323 + *addr = (FPW) 0x00200020;/* erase setup */
  324 + *addr = (FPW) 0x00D000D0;/* erase confirm */
  325 +
  326 + while (((status =
  327 + *addr) & (FPW) 0x00800080) !=
  328 + (FPW) 0x00800080) {
  329 + if (get_timer_masked () >
  330 + CFG_FLASH_ERASE_TOUT) {
  331 + printf ("Timeout\n");
  332 + /* suspend erase */
  333 + *addr = (FPW) 0x00B000B0;
  334 + /* reset to read mode */
  335 + *addr = (FPW) 0x00FF00FF;
  336 + rcode = 1;
  337 + break;
  338 + }
  339 + }
  340 +
  341 + /* clear status register cmd. */
  342 + *addr = (FPW) 0x00500050;
  343 + *addr = (FPW) 0x00FF00FF;/* resest to read mode */
  344 + printf (" done\n");
  345 + }
  346 + }
  347 + return rcode;
  348 +}
  349 +
  350 +/*-----------------------------------------------------------------------
  351 + * Copy memory to flash, returns:
  352 + * 0 - OK
  353 + * 1 - write timeout
  354 + * 2 - Flash not erased
  355 + * 4 - Flash not identified
  356 + */
  357 +
  358 +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  359 +{
  360 + ulong cp, wp;
  361 + FPW data;
  362 + int count, i, l, rc, port_width;
  363 +
  364 + if (info->flash_id == FLASH_UNKNOWN) {
  365 + return 4;
  366 + }
  367 +/* get lower word aligned address */
  368 +#ifdef FLASH_PORT_WIDTH16
  369 + wp = (addr & ~1);
  370 + port_width = 2;
  371 +#else
  372 + wp = (addr & ~3);
  373 + port_width = 4;
  374 +#endif
  375 +
  376 + /*
  377 + * handle unaligned start bytes
  378 + */
  379 + if ((l = addr - wp) != 0) {
  380 + data = 0;
  381 + for (i = 0, cp = wp; i < l; ++i, ++cp) {
  382 + data = (data << 8) | (*(uchar *) cp);
  383 + }
  384 + for (; i < port_width && cnt > 0; ++i) {
  385 + data = (data << 8) | *src++;
  386 + --cnt;
  387 + ++cp;
  388 + }
  389 + for (; cnt == 0 && i < port_width; ++i, ++cp) {
  390 + data = (data << 8) | (*(uchar *) cp);
  391 + }
  392 +
  393 + if ((rc = write_data (info, wp, SWAP (data))) != 0) {
  394 + return (rc);
  395 + }
  396 + wp += port_width;
  397 + }
  398 +
  399 + /*
  400 + * handle word aligned part
  401 + */
  402 + count = 0;
  403 + while (cnt >= port_width) {
  404 + data = 0;
  405 + for (i = 0; i < port_width; ++i) {
  406 + data = (data << 8) | *src++;
  407 + }
  408 + if ((rc = write_data (info, wp, SWAP (data))) != 0) {
  409 + return (rc);
  410 + }
  411 + wp += port_width;
  412 + cnt -= port_width;
  413 + if (count++ > 0x800) {
  414 + spin_wheel ();
  415 + count = 0;
  416 + }
  417 + }
  418 +
  419 + if (cnt == 0) {
  420 + return (0);
  421 + }
  422 +
  423 + /*
  424 + * handle unaligned tail bytes
  425 + */
  426 + data = 0;
  427 + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
  428 + data = (data << 8) | *src++;
  429 + --cnt;
  430 + }
  431 + for (; i < port_width; ++i, ++cp) {
  432 + data = (data << 8) | (*(uchar *) cp);
  433 + }
  434 +
  435 + return (write_data (info, wp, SWAP (data)));
  436 +}
  437 +
  438 +/*-----------------------------------------------------------------------
  439 + * Write a word or halfword to Flash, returns:
  440 + * 0 - OK
  441 + * 1 - write timeout
  442 + * 2 - Flash not erased
  443 + */
  444 +static int write_data (flash_info_t * info, ulong dest, FPW data)
  445 +{
  446 + FPWV *addr = (FPWV *) dest;
  447 + ulong status;
  448 + int flag;
  449 +
  450 + /* Check if Flash is (sufficiently) erased */
  451 + if ((*addr & data) != data) {
  452 + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
  453 + return (2);
  454 + }
  455 + flash_unprotect_sectors (addr);
  456 + /* Disable interrupts which might cause a timeout here */
  457 + flag = disable_interrupts ();
  458 + *addr = (FPW) 0x00400040; /* write setup */
  459 + *addr = data;
  460 +
  461 + /* arm simple, non interrupt dependent timer */
  462 + reset_timer_masked ();
  463 +
  464 + /* wait while polling the status register */
  465 + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
  466 + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
  467 + *addr = (FPW) 0x00FF00FF; /* restore read mode */
  468 + return (1);
  469 + }
  470 + }
  471 + *addr = (FPW) 0x00FF00FF; /* restore read mode */
  472 + return (0);
  473 +}
  474 +
  475 +void inline spin_wheel (void)
  476 +{
  477 + static int p = 0;
  478 + static char w[] = "\\/-";
  479 +
  480 + printf ("\010%c", w[p]);
  481 + (++p == 3) ? (p = 0) : 0;
  482 +}
board/omap1610inn/omap1610innovator.c
Diff comments   View file @ 6f21347
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4 + * Marius Groeger <mgroeger@sysgo.de>
  5 + *
  6 + * (C) Copyright 2002
  7 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  8 + *
  9 + * (C) Copyright 2003
  10 + * Texas Instruments, <www.ti.com>
  11 + * Kshitij Gupta <Kshitij@ti.com>
  12 + *
  13 + * See file CREDITS for list of people who contributed to this
  14 + * project.
  15 + *
  16 + * This program is free software; you can redistribute it and/or
  17 + * modify it under the terms of the GNU General Public License as
  18 + * published by the Free Software Foundation; either version 2 of
  19 + * the License, or (at your option) any later version.
  20 + *
  21 + * This program is distributed in the hope that it will be useful,
  22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24 + * GNU General Public License for more details.
  25 + *
  26 + * You should have received a copy of the GNU General Public License
  27 + * along with this program; if not, write to the Free Software
  28 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29 + * MA 02111-1307 USA
  30 + */
  31 +
  32 +#include <common.h>
  33 +#if defined(CONFIG_OMAP1610)
  34 +#include <./configs/omap1510.h>
  35 +#endif
  36 +
  37 +void flash__init (void);
  38 +void ether__init (void);
  39 +void set_muxconf_regs (void);
  40 +void peripheral_power_enable (void);
  41 +
  42 +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
  43 +
  44 +static inline void delay (unsigned long loops)
  45 +{
  46 + __asm__ volatile ("1:\n"
  47 + "subs %0, %1, #1\n"
  48 + "bne 1b":"=r" (loops):"0" (loops));
  49 +}
  50 +
  51 +/*
  52 + * Miscellaneous platform dependent initialisations
  53 + */
  54 +
  55 +int board_init (void)
  56 +{
  57 + DECLARE_GLOBAL_DATA_PTR;
  58 +
  59 + /* arch number of OMAP 1510-Board */
  60 + /* to be changed for OMAP 1610 Board */
  61 + gd->bd->bi_arch_number = 234;
  62 +
  63 + /* adress of boot parameters */
  64 + gd->bd->bi_boot_params = 0x10000100;
  65 +
  66 + /* Configure MUX settings */
  67 + set_muxconf_regs ();
  68 + peripheral_power_enable ();
  69 +
  70 +/* this speeds up your boot a quite a bit. However to make it
  71 + * work, you need make sure your kernel startup flush bug is fixed.
  72 + * ... rkw ...
  73 + */
  74 + icache_enable ();
  75 +
  76 + flash__init ();
  77 + ether__init ();
  78 + return 0;
  79 +}
  80 +
  81 +
  82 +int misc_init_r (void)
  83 +{
  84 + /* currently empty */
  85 + return (0);
  86 +}
  87 +
  88 +/******************************
  89 + Routine:
  90 + Description:
  91 +******************************/
  92 +void flash__init (void)
  93 +{
  94 +#define EMIFS_GlB_Config_REG 0xfffecc0c
  95 + unsigned int regval;
  96 + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
  97 + /* Turn off write protection for flash devices. */
  98 + regval = regval | 0x0001;
  99 + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
  100 +}
  101 +/*************************************************************
  102 + Routine:ether__init
  103 + Description: take the Ethernet controller out of reset and wait
  104 + for the EEPROM load to complete.
  105 +*************************************************************/
  106 +void ether__init (void)
  107 +{
  108 +#define ETH_CONTROL_REG 0x0400000b
  109 +
  110 + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
  111 + udelay (3);
  112 +}
  113 +
  114 +/******************************
  115 + Routine:
  116 + Description:
  117 +******************************/
  118 +int dram_init (void)
  119 +{
  120 + DECLARE_GLOBAL_DATA_PTR;
  121 +
  122 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  123 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  124 +
  125 + return 0;
  126 +}
  127 +
  128 +/******************************************************
  129 + Routine: set_muxconf_regs
  130 + Description: Setting up the configuration Mux registers
  131 + specific to the hardware
  132 +*******************************************************/
  133 +void set_muxconf_regs (void)
  134 +{
  135 + volatile unsigned int *MuxConfReg;
  136 + /* set each registers to its reset value; */
  137 + MuxConfReg =
  138 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
  139 + /* setup for UART1 */
  140 + *MuxConfReg &= ~(0x02000000); /* bit 25 */
  141 + /* setup for UART2 */
  142 + *MuxConfReg &= ~(0x01000000); /* bit 24 */
  143 + /* Disable Uwire CS Hi-Z */
  144 + *MuxConfReg |= 0x08000000;
  145 + MuxConfReg =
  146 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
  147 + *MuxConfReg = 0x00000000;
  148 + MuxConfReg =
  149 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
  150 + *MuxConfReg = 0x00000000;
  151 + MuxConfReg =
  152 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
  153 + *MuxConfReg = 0x00000000;
  154 + MuxConfReg =
  155 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
  156 + /*setup mux for UART3 */
  157 + *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
  158 + *MuxConfReg &= ~0x0000003e;
  159 + MuxConfReg =
  160 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
  161 + *MuxConfReg = 0x00000000;
  162 + MuxConfReg =
  163 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
  164 + /* Disable Uwire CS Hi-Z */
  165 + *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
  166 + MuxConfReg =
  167 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
  168 + /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
  169 + /* hardware will actually use TX and RTS based on bit 25 in */
  170 + /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
  171 + *MuxConfReg |= 0x00201000;
  172 + MuxConfReg =
  173 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
  174 + *MuxConfReg = 0x00000000;
  175 + MuxConfReg =
  176 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
  177 + *MuxConfReg = 0x00000000;
  178 + MuxConfReg =
  179 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
  180 + /* setup for UART2 */
  181 + /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
  182 + /* hardware will actually use TX and RTS based on bit 24 in */
  183 + /* FUNC_MUX_CTRL_0. */
  184 + *MuxConfReg |= 0x09000000;
  185 + MuxConfReg =
  186 + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
  187 + *MuxConfReg = 0x00000000;
  188 + MuxConfReg =
  189 + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
  190 + *MuxConfReg = 0x00000000;
  191 + /* mux setup for SD/MMC driver */
  192 + MuxConfReg =
  193 + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
  194 + *MuxConfReg &= 0xFFFE0FFF;
  195 + MuxConfReg =
  196 + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
  197 + *MuxConfReg = 0x00000000;
  198 + MuxConfReg =
  199 + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
  200 + /* bit 13 for MMC2 XOR_CLK */
  201 + *MuxConfReg &= ~(0x00002000);
  202 + /* bit 29 for UART 1 */
  203 + *MuxConfReg &= ~(0x00002000);
  204 + MuxConfReg =
  205 + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
  206 + /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
  207 + *MuxConfReg |= 0x000C0000;
  208 + MuxConfReg =
  209 + (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
  210 + *MuxConfReg &= ~(0x00000070);
  211 + *MuxConfReg &= ~(0x00000008);
  212 + *MuxConfReg |= 0x00000003;
  213 + *MuxConfReg |= 0x00000180;
  214 + MuxConfReg =
  215 + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
  216 + /* bit 17, software controls VBUS */
  217 + *MuxConfReg &= ~(0x00020000);
  218 + /* Enable USB 48 and 12M clocks */
  219 + *MuxConfReg |= 0x00000200;
  220 + *MuxConfReg &= ~(0x00000180);
  221 + /*2.75V for MMCSDIO1 */
  222 + MuxConfReg =
  223 + (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
  224 + *MuxConfReg = 0x00001FE7;
  225 + MuxConfReg =
  226 + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
  227 + *MuxConfReg = 0x00000000;
  228 + MuxConfReg =
  229 + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
  230 + *MuxConfReg = 0x00000000;
  231 + MuxConfReg =
  232 + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
  233 + *MuxConfReg = 0x00000000;
  234 + MuxConfReg =
  235 + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
  236 + *MuxConfReg = 0x00000000;
  237 + MuxConfReg =
  238 + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
  239 + *MuxConfReg = 0x00000000;
  240 + MuxConfReg =
  241 + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
  242 + *MuxConfReg = 0x00000000;
  243 + /* Turn on UART2 48 MHZ clock */
  244 + MuxConfReg =
  245 + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
  246 + *MuxConfReg |= 0x40000000;
  247 + MuxConfReg =
  248 + (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
  249 + /* setup for USB VBus detection OMAP161x */
  250 + *MuxConfReg |= 0x00040000; /* bit 18 */
  251 + MuxConfReg =
  252 + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
  253 + /* PullUps for SD/MMC driver */
  254 + *MuxConfReg |= ~(0xFFFE0FFF);
  255 + MuxConfReg =
  256 + (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
  257 + *MuxConfReg = COMP_MODE_ENABLE;
  258 +}
  259 +
  260 +/******************************************************
  261 + Routine: peripheral_power_enable
  262 + Description: Enable the power for UART1
  263 +*******************************************************/
  264 +void peripheral_power_enable (void)
  265 +{
  266 +#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
  267 +#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
  268 +
  269 + *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
  270 +}
board/omap1610inn/platform.S
Diff comments   View file @ 6f21347
  1 +/*
  2 + * Board specific setup info
  3 + *
  4 + * (C) Copyright 2003
  5 + * Texas Instruments, <www.ti.com>
  6 + * Kshitij Gupta <Kshitij@ti.com>
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <config.h>
  28 +#include <version.h>
  29 +
  30 +#if defined(CONFIG_OMAP1610)
  31 +#include <./configs/omap1510.h>
  32 +#endif
  33 +
  34 +
  35 +_TEXT_BASE:
  36 + .word TEXT_BASE /* sdram load addr from config.mk */
  37 +
  38 +.globl platformsetup
  39 +platformsetup:
  40 +
  41 +
  42 + /*------------------------------------------------------*
  43 + * Set up ARM CLM registers (IDLECT1) *
  44 + *------------------------------------------------------*/
  45 + ldr r0, REG_ARM_IDLECT1
  46 + ldr r1, VAL_ARM_IDLECT1
  47 + str r1, [r0]
  48 +
  49 + /*------------------------------------------------------*
  50 + * Set up ARM CLM registers (IDLECT2) *
  51 + *------------------------------------------------------*/
  52 + ldr r0, REG_ARM_IDLECT2
  53 + ldr r1, VAL_ARM_IDLECT2
  54 + str r1, [r0]
  55 +
  56 + /*------------------------------------------------------*
  57 + * Set up ARM CLM registers (IDLECT3) *
  58 + *------------------------------------------------------*/
  59 + ldr r0, REG_ARM_IDLECT3
  60 + ldr r1, VAL_ARM_IDLECT3
  61 + str r1, [r0]
  62 +
  63 +
  64 + mov r1, #0x01 /* PER_EN bit */
  65 + ldr r0, REG_ARM_RSTCT2
  66 + strh r1, [r0] /* CLKM; Peripheral reset. */
  67 +
  68 + /* Set CLKM to Sync-Scalable */
  69 + /* I supposedly need to enable the dsp clock before switching */
  70 + mov r1, #0x0000
  71 + ldr r0, REG_ARM_SYSST
  72 + strh r1, [r0]
  73 + mov r0, #0x400
  74 +1:
  75 + subs r0, r0, #0x1 /* wait for any bubbles to finish */
  76 + bne 1b
  77 + ldr r1, VAL_ARM_CKCTL
  78 + ldr r0, REG_ARM_CKCTL
  79 + strh r1, [r0]
  80 +
  81 + /* a few nops to let settle */
  82 + nop
  83 + nop
  84 + nop
  85 + nop
  86 + nop
  87 + nop
  88 + nop
  89 + nop
  90 + nop
  91 + nop
  92 +
  93 + /* setup DPLL 1 */
  94 + /* Ramp up the clock to 96Mhz */
  95 + ldr r1, VAL_DPLL1_CTL
  96 + ldr r0, REG_DPLL1_CTL
  97 + strh r1, [r0]
  98 + ands r1, r1, #0x10 /* Check if PLL is enabled. */
  99 + beq lock_end /* Do not look for lock if BYPASS selected */
  100 +2:
  101 + ldrh r1, [r0]
  102 + ands r1, r1, #0x01 /* Check the LOCK bit.*/
  103 + beq 2b /* loop until bit goes hi. */
  104 +lock_end:
  105 +
  106 +
  107 + /*------------------------------------------------------*
  108 + * Turn off the watchdog during init... *
  109 + *------------------------------------------------------*/
  110 + ldr r0, REG_WATCHDOG
  111 + ldr r1, WATCHDOG_VAL1
  112 + str r1, [r0]
  113 + ldr r1, WATCHDOG_VAL2
  114 + str r1, [r0]
  115 + ldr r0, REG_WSPRDOG
  116 + ldr r1, WSPRDOG_VAL1
  117 + str r1, [r0]
  118 + ldr r0, REG_WWPSDOG
  119 +
  120 +watch1Wait:
  121 + ldr r1, [r0]
  122 + tst r1, #0x10
  123 + bne watch1Wait
  124 +
  125 + ldr r0, REG_WSPRDOG
  126 + ldr r1, WSPRDOG_VAL2
  127 + str r1, [r0]
  128 + ldr r0, REG_WWPSDOG
  129 +watch2Wait:
  130 + ldr r1, [r0]
  131 + tst r1, #0x10
  132 + bne watch2Wait
  133 +
  134 +
  135 +
  136 +
  137 + /* Set memory timings corresponding to the new clock speed */
  138 +
  139 + /* Check execution location to determine current execution location
  140 + * and branch to appropriate initialization code.
  141 + */
  142 + /* Load physical SDRAM base. */
  143 + mov r0, #0x10000000
  144 + /* Get current execution location. */
  145 + mov r1, pc
  146 + /* Compare. */
  147 + cmp r1, r0
  148 + /* Skip over EMIF-fast initialization if running from SDRAM. */
  149 + bge skip_sdram
  150 +
  151 + /*
  152 + * Delay for SDRAM initialization.
  153 + */
  154 + mov r3, #0x1800 /* value should be checked */
  155 +3:
  156 + subs r3, r3, #0x1 /* Decrement count */
  157 + bne 3b
  158 +
  159 +
  160 + /*
  161 + * Set SDRAM control values. Disable refresh before MRS command.
  162 + */
  163 +
  164 + /* mobile ddr operation */
  165 + ldr r0, REG_SDRAM_OPERATION
  166 + mov r2, #07
  167 + str r2, [r0]
  168 +
  169 + /* config register */
  170 + ldr r0, REG_SDRAM_CONFIG
  171 + ldr r1, SDRAM_CONFIG_VAL
  172 + str r1, [r0]
  173 +
  174 + /* manual command register */
  175 + ldr r0, REG_SDRAM_MANUAL_CMD
  176 + /* issue set cke high */
  177 + mov r1, #CMD_SDRAM_CKE_SET_HIGH
  178 + str r1, [r0]
  179 + /* issue nop */
  180 + mov r1, #CMD_SDRAM_NOP
  181 + str r1, [r0]
  182 +
  183 + mov r2, #0x0100
  184 +waitMDDR1:
  185 + subs r2, r2, #1
  186 + bne waitMDDR1 /* delay loop */
  187 +
  188 + /* issue precharge */
  189 + mov r1, #CMD_SDRAM_PRECHARGE
  190 + str r1, [r0]
  191 +
  192 + /* issue autorefresh x 2 */
  193 + mov r1, #CMD_SDRAM_AUTOREFRESH
  194 + str r1, [r0]
  195 + str r1, [r0]
  196 +
  197 + /* mrs register ddr mobile */
  198 + ldr r0, REG_SDRAM_MRS
  199 + mov r1, #0x33
  200 + str r1, [r0]
  201 +
  202 + /* emrs1 low-power register */
  203 + ldr r0, REG_SDRAM_EMRS1
  204 + /* self refresh on all banks */
  205 + mov r1, #0
  206 + str r1, [r0]
  207 +
  208 + ldr r0, REG_DLL_URD_CONTROL
  209 + ldr r1, DLL_URD_CONTROL_VAL
  210 + str r1, [r0]
  211 +
  212 + ldr r0, REG_DLL_LRD_CONTROL
  213 + ldr r1, DLL_LRD_CONTROL_VAL
  214 + str r1, [r0]
  215 +
  216 + ldr r0, REG_DLL_WRT_CONTROL
  217 + ldr r1, DLL_WRT_CONTROL_VAL
  218 + str r1, [r0]
  219 +
  220 + /* delay loop */
  221 + mov r2, #0x0100
  222 +waitMDDR2:
  223 + subs r2, r2, #1
  224 + bne waitMDDR2
  225 +
  226 + /*
  227 + * Delay for SDRAM initialization.
  228 + */
  229 + mov r3, #0x1800
  230 +4:
  231 + subs r3, r3, #1 /* Decrement count. */
  232 + bne 4b
  233 + b common_tc
  234 +
  235 +skip_sdram:
  236 +
  237 + ldr r0, REG_SDRAM_CONFIG
  238 + ldr r1, SDRAM_CONFIG_VAL
  239 + str r1, [r0]
  240 +
  241 +common_tc:
  242 + /* slow interface */
  243 + ldr r1, VAL_TC_EMIFS_CS0_CONFIG
  244 + ldr r0, REG_TC_EMIFS_CS0_CONFIG
  245 + str r1, [r0] /* Chip Select 0 */
  246 +
  247 + ldr r1, VAL_TC_EMIFS_CS1_CONFIG
  248 + ldr r0, REG_TC_EMIFS_CS1_CONFIG
  249 + str r1, [r0] /* Chip Select 1 */
  250 + ldr r1, VAL_TC_EMIFS_CS3_CONFIG
  251 + ldr r0, REG_TC_EMIFS_CS3_CONFIG
  252 + str r1, [r0] /* Chip Select 3 */
  253 + /* back to arch calling code */
  254 + mov pc, lr
  255 +
  256 + /* the literal pools origin */
  257 + .ltorg
  258 +
  259 +
  260 +REG_TC_EMIFS_CONFIG: /* 32 bits */
  261 + .word 0xfffecc0c
  262 +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
  263 + .word 0xfffecc10
  264 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
  265 + .word 0xfffecc14
  266 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
  267 + .word 0xfffecc18
  268 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
  269 + .word 0xfffecc1c
  270 +
  271 +/* MPU clock/reset/power mode control registers */
  272 +REG_ARM_CKCTL: /* 16 bits */
  273 + .word 0xfffece00
  274 +
  275 +REG_ARM_IDLECT3: /* 16 bits */
  276 + .word 0xfffece24
  277 +REG_ARM_IDLECT2: /* 16 bits */
  278 + .word 0xfffece08
  279 +REG_ARM_IDLECT1: /* 16 bits */
  280 + .word 0xfffece04
  281 +
  282 +REG_ARM_RSTCT2: /* 16 bits */
  283 + .word 0xfffece14
  284 +REG_ARM_SYSST: /* 16 bits */
  285 + .word 0xfffece18
  286 +/* DPLL control registers */
  287 +REG_DPLL1_CTL: /* 16 bits */
  288 + .word 0xfffecf00
  289 +
  290 +/* Watch Dog register */
  291 +/* secure watchdog stop */
  292 +REG_WSPRDOG:
  293 + .word 0xfffeb048
  294 +/* watchdog write pending */
  295 +REG_WWPSDOG:
  296 + .word 0xfffeb034
  297 +
  298 +WSPRDOG_VAL1:
  299 + .word 0x0000aaaa
  300 +WSPRDOG_VAL2:
  301 + .word 0x00005555
  302 +
  303 +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
  304 + counter @8192 rows, 10 ns, 8 burst */
  305 +REG_SDRAM_CONFIG:
  306 + .word 0xfffecc20
  307 +
  308 +/* Operation register */
  309 +REG_SDRAM_OPERATION:
  310 + .word 0xfffecc80
  311 +
  312 +/* Manual command register */
  313 +REG_SDRAM_MANUAL_CMD:
  314 + .word 0xfffecc84
  315 +
  316 +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
  317 +REG_SDRAM_MRS:
  318 + .word 0xfffecc70
  319 +
  320 +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
  321 +REG_SDRAM_EMRS1:
  322 + .word 0xfffecc78
  323 +
  324 +/* WRT DLL register */
  325 +REG_DLL_WRT_CONTROL:
  326 + .word 0xfffecc68
  327 +DLL_WRT_CONTROL_VAL:
  328 + .word 0x03f00002
  329 +
  330 +/* URD DLL register */
  331 +REG_DLL_URD_CONTROL:
  332 + .word 0xfffeccc0
  333 +DLL_URD_CONTROL_VAL:
  334 + .word 0x00800002
  335 +
  336 +/* LRD DLL register */
  337 +REG_DLL_LRD_CONTROL:
  338 + .word 0xfffecccc
  339 +
  340 +REG_WATCHDOG:
  341 + .word 0xfffec808
  342 +
  343 +/* 96 MHz Samsung Mobile DDR */
  344 +SDRAM_CONFIG_VAL:
  345 + .word 0x001200f4
  346 +
  347 +DLL_LRD_CONTROL_VAL:
  348 + .word 0x00800002
  349 +
  350 +VAL_ARM_CKCTL:
  351 + .word 0x3000
  352 +VAL_DPLL1_CTL:
  353 + .word 0x2830
  354 +
  355 +VAL_TC_EMIFS_CS0_CONFIG:
  356 + .word 0x002130b0
  357 +VAL_TC_EMIFS_CS1_CONFIG:
  358 + .word 0x00001131
  359 +VAL_TC_EMIFS_CS2_CONFIG:
  360 + .word 0x000055f0
  361 +VAL_TC_EMIFS_CS3_CONFIG:
  362 + .word 0x88011131
  363 +VAL_TC_EMIFF_SDRAM_CONFIG:
  364 + .word 0x010290fc
  365 +VAL_TC_EMIFF_MRS:
  366 + .word 0x00000027
  367 +
  368 +VAL_ARM_IDLECT1:
  369 + .word 0x00000400
  370 +
  371 +VAL_ARM_IDLECT2:
  372 + .word 0x00000886
  373 +VAL_ARM_IDLECT3:
  374 + .word 0x00000015
  375 +
  376 +WATCHDOG_VAL1:
  377 + .word 0x000000f5
  378 +WATCHDOG_VAL2:
  379 + .word 0x000000a0
  380 +
  381 +/* command values */
  382 +.equ CMD_SDRAM_NOP, 0x00000000
  383 +.equ CMD_SDRAM_PRECHARGE, 0x00000001
  384 +.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
  385 +.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
board/omap1610inn/u-boot.lds
Diff comments   View file @ 6f21347
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  25 +OUTPUT_ARCH(arm)
  26 +ENTRY(_start)
  27 +SECTIONS
  28 +{
  29 + . = 0x00000000;
  30 + . = ALIGN(4);
  31 + .text :
  32 + {
  33 + cpu/arm926ejs/start.o (.text)
  34 + *(.text)
  35 + }
  36 + . = ALIGN(4);
  37 + .rodata : { *(.rodata) }
  38 + . = ALIGN(4);
  39 + .data : { *(.data) }
  40 + . = ALIGN(4);
  41 + .got : { *(.got) }
  42 +
  43 + __u_boot_cmd_start = .;
  44 + .u_boot_cmd : { *(.u_boot_cmd) }
  45 + __u_boot_cmd_end = .;
  46 +
  47 + armboot_end_data = .;
  48 + . = ALIGN(4);
  49 + .bss : { *(.bss) }
  50 + armboot_end = .;
  51 +}
cpu/arm926ejs/Makefile
Diff comments   View file @ 6f21347
  1 +#
  2 +# (C) Copyright 2000-2003
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(CPU).a
  27 +
  28 +START = start.o
  29 +OBJS = interrupts.o cpu.o
  30 +
  31 +all: .depend $(START) $(LIB)
  32 +
  33 +$(LIB): $(OBJS)
  34 + $(AR) crv $@ $(OBJS)
  35 +
  36 +#########################################################################
  37 +
  38 +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
  39 + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
  40 +
  41 +sinclude .depend
  42 +
  43 +#########################################################################
cpu/arm926ejs/config.mk
Diff comments   View file @ 6f21347
  1 +#
  2 +# (C) Copyright 2002
  3 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
  25 + -mshort-load-bytes -msoft-float
  26 +
  27 +PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4 + * Marius Groeger <mgroeger@sysgo.de>
  5 + *
  6 + * (C) Copyright 2002
  7 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  8 + *
  9 + * See file CREDITS for list of people who contributed to this
  10 + * project.
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * You should have received a copy of the GNU General Public License
  23 + * along with this program; if not, write to the Free Software
  24 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 + * MA 02111-1307 USA
  26 + */
  27 +
  28 +/*
  29 + * CPU specific code
  30 + */
  31 +
  32 +#include <common.h>
  33 +#include <command.h>
  34 +#include <arm926ejs.h>
  35 +
  36 +/* read co-processor 15, register #1 (control register) */
  37 +static unsigned long read_p15_c1 (void)
  38 +{
  39 + unsigned long value;
  40 +
  41 + __asm__ __volatile__(
  42 + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
  43 + : "=r" (value)
  44 + :
  45 + : "memory");
  46 +
  47 +#ifdef MMU_DEBUG
  48 + printf ("p15/c1 is = %08lx\n", value);
  49 +#endif
  50 + return value;
  51 +}
  52 +
  53 +/* write to co-processor 15, register #1 (control register) */
  54 +static void write_p15_c1 (unsigned long value)
  55 +{
  56 +#ifdef MMU_DEBUG
  57 + printf ("write %08lx to p15/c1\n", value);
  58 +#endif
  59 + __asm__ __volatile__(
  60 + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
  61 + :
  62 + : "r" (value)
  63 + : "memory");
  64 +
  65 + read_p15_c1 ();
  66 +}
  67 +
  68 +static void cp_delay (void)
  69 +{
  70 + volatile int i;
  71 +
  72 + /* Many OMAP regs need at least 2 nops */
  73 + for (i = 0; i < 100; i++);
  74 +}
  75 +
  76 +/* See also ARM Ref. Man. */
  77 +#define C1_MMU (1<<0) /* mmu off/on */
  78 +#define C1_ALIGN (1<<1) /* alignment faults off/on */
  79 +#define C1_DC (1<<2) /* dcache off/on */
  80 +#define C1_WB (1<<3) /* merging write buffer on/off */
  81 +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
  82 +#define C1_SYS_PROT (1<<8) /* system protection */
  83 +#define C1_ROM_PROT (1<<9) /* ROM protection */
  84 +#define C1_IC (1<<12) /* icache off/on */
  85 +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
  86 +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
  87 +
  88 +int cpu_init (void)
  89 +{
  90 + /*
  91 + * setup up stack if necessary
  92 + */
  93 +#ifdef CONFIG_USE_IRQ
  94 + IRQ_STACK_START = _armboot_end +
  95 + CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
  96 + FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
  97 + _armboot_real_end = FIQ_STACK_START + 4;
  98 +#else
  99 + _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
  100 +#endif /* CONFIG_USE_IRQ */
  101 + return (0);
  102 +}
  103 +
  104 +int cleanup_before_linux (void)
  105 +{
  106 + /*
  107 + * this function is called just before we call linux
  108 + * it prepares the processor for linux
  109 + *
  110 + * we turn off caches etc ...
  111 + */
  112 +
  113 + unsigned long i;
  114 +
  115 + disable_interrupts ();
  116 +
  117 + /* turn off I/D-cache */
  118 + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  119 + i &= ~(C1_DC | C1_IC);
  120 + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  121 +
  122 + /* flush I/D-cache */
  123 + i = 0;
  124 + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
  125 + return (0);
  126 +}
  127 +
  128 +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  129 +{
  130 + extern void reset_cpu (ulong addr);
  131 +
  132 + disable_interrupts ();
  133 + reset_cpu (0);
  134 + /*NOTREACHED*/
  135 + return (0);
  136 +}
  137 +
  138 +void icache_enable (void)
  139 +{
  140 + ulong reg;
  141 +
  142 + reg = read_p15_c1 (); /* get control reg. */
  143 + cp_delay ();
  144 + write_p15_c1 (reg | C1_IC);
  145 +}
  146 +
  147 +void icache_disable (void)
  148 +{
  149 + ulong reg;
  150 +
  151 + reg = read_p15_c1 ();
  152 + cp_delay ();
  153 + write_p15_c1 (reg & ~C1_IC);
  154 +}
  155 +
  156 +int icache_status (void)
  157 +{
  158 + return (read_p15_c1 () & C1_IC) != 0;
  159 +}
cpu/arm926ejs/interrupts.c
Diff comments   View file @ 6f21347
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4 + * Marius Groeger <mgroeger@sysgo.de>
  5 + *
  6 + * (C) Copyright 2002
  7 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8 + * Alex Zuepke <azu@sysgo.de>
  9 + *
  10 + * (C) Copyright 2002
  11 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  12 + *
  13 + * See file CREDITS for list of people who contributed to this
  14 + * project.
  15 + *
  16 + * This program is free software; you can redistribute it and/or
  17 + * modify it under the terms of the GNU General Public License as
  18 + * published by the Free Software Foundation; either version 2 of
  19 + * the License, or (at your option) any later version.
  20 + *
  21 + * This program is distributed in the hope that it will be useful,
  22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24 + * GNU General Public License for more details.
  25 + *
  26 + * You should have received a copy of the GNU General Public License
  27 + * along with this program; if not, write to the Free Software
  28 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29 + * MA 02111-1307 USA
  30 + */
  31 +
  32 +#include <common.h>
  33 +#include <arm925t.h>
  34 +#include <configs/omap1510.h>
  35 +
  36 +#include <asm/proc-armv/ptrace.h>
  37 +
  38 +extern void reset_cpu(ulong addr);
  39 +#define TIMER_LOAD_VAL 0xffffffff
  40 +
  41 +/* macro to read the 32 bit timer */
  42 +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
  43 +
  44 +#ifdef CONFIG_USE_IRQ
  45 +/* enable IRQ interrupts */
  46 +void enable_interrupts (void)
  47 +{
  48 + unsigned long temp;
  49 + __asm__ __volatile__("mrs %0, cpsr\n"
  50 + "bic %0, %0, #0x80\n"
  51 + "msr cpsr_c, %0"
  52 + : "=r" (temp)
  53 + : "memory");
  54 +}
  55 +
  56 +/*
  57 + * disable IRQ/FIQ interrupts
  58 + * returns true if interrupts had been enabled before we disabled them
  59 + */
  60 +int disable_interrupts (void)
  61 +{
  62 + unsigned long old,temp;
  63 + __asm__ __volatile__("mrs %0, cpsr\n"
  64 + "orr %1, %0, #0xc0\n"
  65 + "msr cpsr_c, %1"
  66 + : "=r" (old), "=r" (temp)
  67 + : "memory");
  68 + return (old & 0x80) == 0;
  69 +}
  70 +#else
  71 +void enable_interrupts (void)
  72 +{
  73 + return;
  74 +}
  75 +int disable_interrupts (void)
  76 +{
  77 + return 0;
  78 +}
  79 +#endif
  80 +
  81 +
  82 +
  83 +void bad_mode (void)
  84 +{
  85 + panic ("Resetting CPU ...\n");
  86 + reset_cpu (0);
  87 +}
  88 +
  89 +void show_regs (struct pt_regs *regs)
  90 +{
  91 + unsigned long flags;
  92 + const char *processor_modes[] = {
  93 + "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
  94 + "UK4_26", "UK5_26", "UK6_26", "UK7_26",
  95 + "UK8_26", "UK9_26", "UK10_26", "UK11_26",
  96 + "UK12_26", "UK13_26", "UK14_26", "UK15_26",
  97 + "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
  98 + "UK4_32", "UK5_32", "UK6_32", "ABT_32",
  99 + "UK8_32", "UK9_32", "UK10_32", "UND_32",
  100 + "UK12_32", "UK13_32", "UK14_32", "SYS_32",
  101 + };
  102 +
  103 + flags = condition_codes (regs);
  104 +
  105 + printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
  106 + "sp : %08lx ip : %08lx fp : %08lx\n",
  107 + instruction_pointer (regs),
  108 + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
  109 + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
  110 + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
  111 + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
  112 + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
  113 + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
  114 + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
  115 + printf ("Flags: %c%c%c%c",
  116 + flags & CC_N_BIT ? 'N' : 'n',
  117 + flags & CC_Z_BIT ? 'Z' : 'z',
  118 + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
  119 + printf (" IRQs %s FIQs %s Mode %s%s\n",
  120 + interrupts_enabled (regs) ? "on" : "off",
  121 + fast_interrupts_enabled (regs) ? "on" : "off",
  122 + processor_modes[processor_mode (regs)],
  123 + thumb_mode (regs) ? " (T)" : "");
  124 +}
  125 +
  126 +void do_undefined_instruction (struct pt_regs *pt_regs)
  127 +{
  128 + printf ("undefined instruction\n");
  129 + show_regs (pt_regs);
  130 + bad_mode ();
  131 +}
  132 +
  133 +void do_software_interrupt (struct pt_regs *pt_regs)
  134 +{
  135 + printf ("software interrupt\n");
  136 + show_regs (pt_regs);
  137 + bad_mode ();
  138 +}
  139 +
  140 +void do_prefetch_abort (struct pt_regs *pt_regs)
  141 +{
  142 + printf ("prefetch abort\n");
  143 + show_regs (pt_regs);
  144 + bad_mode ();
  145 +}
  146 +
  147 +void do_data_abort (struct pt_regs *pt_regs)
  148 +{
  149 + printf ("data abort\n");
  150 + show_regs (pt_regs);
  151 + bad_mode ();
  152 +}
  153 +
  154 +void do_not_used (struct pt_regs *pt_regs)
  155 +{
  156 + printf ("not used\n");
  157 + show_regs (pt_regs);
  158 + bad_mode ();
  159 +}
  160 +
  161 +void do_fiq (struct pt_regs *pt_regs)
  162 +{
  163 + printf ("fast interrupt request\n");
  164 + show_regs (pt_regs);
  165 + bad_mode ();
  166 +}
  167 +
  168 +void do_irq (struct pt_regs *pt_regs)
  169 +{
  170 + printf ("interrupt request\n");
  171 + show_regs (pt_regs);
  172 + bad_mode ();
  173 +}
  174 +
  175 +static ulong timestamp;
  176 +static ulong lastdec;
  177 +
  178 +/* nothing really to do with interrupts, just starts up a counter. */
  179 +int interrupt_init (void)
  180 +{
  181 + int32_t val;
  182 +
  183 + *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
  184 + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
  185 + (CFG_PVT << MPUTIM_PTV_BIT);
  186 + *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
  187 + return (0);
  188 +}
  189 +
  190 +/*
  191 + * timer without interrupts
  192 + */
  193 +
  194 +void reset_timer (void)
  195 +{
  196 + reset_timer_masked ();
  197 +}
  198 +
  199 +ulong get_timer (ulong base)
  200 +{
  201 + return get_timer_masked () - base;
  202 +}
  203 +
  204 +void set_timer (ulong t)
  205 +{
  206 + timestamp = t;
  207 +}
  208 +
  209 +/* very rough timer... */
  210 +void udelay (unsigned long usec)
  211 +{
  212 +#ifdef CONFIG_INNOVATOROMAP1610
  213 +#define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
  214 + volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
  215 +
  216 + for (i = time_remaining; i > 0; i--) {
  217 + }
  218 +#else
  219 +
  220 + ulong tmo;
  221 + tmo = usec / 1000;
  222 + tmo *= CFG_HZ;
  223 + tmo /= 1000;
  224 + tmo += get_timer (0);
  225 + while (get_timer_masked () < tmo)
  226 + /*NOP*/;
  227 +#endif
  228 +}
  229 +
  230 +void reset_timer_masked (void)
  231 +{
  232 + /* reset time */
  233 + lastdec = READ_TIMER;
  234 + timestamp = 0;
  235 +}
  236 +
  237 +ulong get_timer_masked (void)
  238 +{
  239 + ulong now = READ_TIMER; /* current tick value */
  240 +
  241 + if (lastdec >= now) { /* did I roll (rem decrementer) */
  242 + /* normal mode */
  243 + /* record amount of time since last check */
  244 + timestamp += lastdec - now;
  245 + } else {
  246 + /* we have an overflow ... */
  247 + timestamp += lastdec + TIMER_LOAD_VAL - now;
  248 + }
  249 + lastdec = now;
  250 +
  251 + return timestamp;
  252 +}
  253 +
  254 +void udelay_masked (unsigned long usec)
  255 +{
  256 +#ifdef CONFIG_INNOVATOROMAP1610
  257 + #define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
  258 + volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
  259 + for (i=time_remaining; i>0; i--) { }
  260 +#else
  261 +
  262 + ulong tmo;
  263 +
  264 + tmo = usec / 1000;
  265 + tmo *= CFG_HZ;
  266 + tmo /= 1000;
  267 +
  268 + reset_timer_masked ();
  269 +
  270 + while (get_timer_masked () < tmo)
  271 + /*NOP*/;
  272 +#endif
  273 +}
  274 +
  275 +/*
  276 + * This function is derived from PowerPC code (read timebase as long long).
  277 + * On ARM it just returns the timer value.
  278 + */
  279 +unsigned long long get_ticks(void)
  280 +{
  281 + return get_timer(0);
  282 +}
  283 +
  284 +/*
  285 + * This function is derived from PowerPC code (timebase clock frequency).
  286 + * On ARM it returns the number of timer ticks per second.
  287 + */
  288 +ulong get_tbclk (void)
  289 +{
  290 + ulong tbclk;
  291 + tbclk = CFG_HZ;
  292 + return tbclk;
  293 +}
cpu/arm926ejs/start.S
Diff comments   View file @ 6f21347
  1 +/*
  2 + * armboot - Startup Code for ARM926EJS CPU-core
  3 + *
  4 + * Copyright (c) 2003 Texas Instruments
  5 + *
  6 + * ----- Adapted for OMAP1610 from ARM925t code ------
  7 + *
  8 + * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  9 + * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  10 + * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
  11 + * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  12 + * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  13 + *
  14 + * See file CREDITS for list of people who contributed to this
  15 + * project.
  16 + *
  17 + * This program is free software; you can redistribute it and/or
  18 + * modify it under the terms of the GNU General Public License as
  19 + * published by the Free Software Foundation; either version 2 of
  20 + * the License, or (at your option) any later version.
  21 + *
  22 + * This program is distributed in the hope that it will be useful,
  23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * GNU General Public License for more details.
  26 + *
  27 + * You should have received a copy of the GNU General Public License
  28 + * along with this program; if not, write to the Free Software
  29 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 + * MA 02111-1307 USA
  31 + */
  32 +
  33 +
  34 +
  35 +#include <config.h>
  36 +#include <version.h>
  37 +
  38 +#if defined(CONFIG_OMAP1610)
  39 +#include <./configs/omap1510.h>
  40 +#endif
  41 +
  42 +/*
  43 + *************************************************************************
  44 + *
  45 + * Jump vector table as in table 3.1 in [1]
  46 + *
  47 + *************************************************************************
  48 + */
  49 +
  50 +
  51 +.globl _start
  52 +_start:
  53 + b reset
  54 + ldr pc, _undefined_instruction
  55 + ldr pc, _software_interrupt
  56 + ldr pc, _prefetch_abort
  57 + ldr pc, _data_abort
  58 + ldr pc, _not_used
  59 + ldr pc, _irq
  60 + ldr pc, _fiq
  61 +
  62 +_undefined_instruction:
  63 + .word undefined_instruction
  64 +_software_interrupt:
  65 + .word software_interrupt
  66 +_prefetch_abort:
  67 + .word prefetch_abort
  68 +_data_abort:
  69 + .word data_abort
  70 +_not_used:
  71 + .word not_used
  72 +_irq:
  73 + .word irq
  74 +_fiq:
  75 + .word fiq
  76 +
  77 + .balignl 16,0xdeadbeef
  78 +
  79 +
  80 +/*
  81 + *************************************************************************
  82 + *
  83 + * Startup Code (reset vector)
  84 + *
  85 + * do important init only if we don't start from memory!
  86 + * setup Memory and board specific bits prior to relocation.
  87 + * relocate armboot to ram
  88 + * setup stack
  89 + *
  90 + *************************************************************************
  91 + */
  92 +
  93 +/*
  94 + * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
  95 + */
  96 +_TEXT_BASE:
  97 + .word TEXT_BASE
  98 +
  99 +.globl _armboot_start
  100 +_armboot_start:
  101 + .word _start
  102 +
  103 +/*
  104 + * Note: _armboot_end_data and _armboot_end are defined
  105 + * by the (board-dependent) linker script.
  106 + * _armboot_end_data is the first usable FLASH address after armboot
  107 + */
  108 +.globl _armboot_end_data
  109 +_armboot_end_data:
  110 + .word armboot_end_data
  111 +.globl _armboot_end
  112 +_armboot_end:
  113 + .word armboot_end
  114 +
  115 +/*
  116 + * _armboot_real_end is the first usable RAM address behind armboot
  117 + * and the various stacks
  118 + */
  119 +.globl _armboot_real_end
  120 +_armboot_real_end:
  121 + .word 0x0badc0de
  122 +
  123 +#ifdef CONFIG_USE_IRQ
  124 +/* IRQ stack memory (calculated at run-time) */
  125 +.globl IRQ_STACK_START
  126 +IRQ_STACK_START:
  127 + .word 0x0badc0de
  128 +
  129 +/* IRQ stack memory (calculated at run-time) */
  130 +.globl FIQ_STACK_START
  131 +FIQ_STACK_START:
  132 + .word 0x0badc0de
  133 +#endif
  134 +
  135 +
  136 +/*
  137 + * the actual reset code
  138 + */
  139 +
  140 +reset:
  141 + /*
  142 + * set the cpu to SVC32 mode
  143 + */
  144 + mrs r0,cpsr
  145 + bic r0,r0,#0x1f
  146 + orr r0,r0,#0xd3
  147 + msr cpsr,r0
  148 +
  149 +
  150 + /*
  151 + * turn off the watchdog, unlock/diable sequence
  152 + */
  153 + mov r1, #0xF5
  154 + ldr r0, =WDTIM_MODE
  155 + strh r1, [r0]
  156 + mov r1, #0xA0
  157 + strh r1, [r0]
  158 +
  159 +
  160 +
  161 +
  162 +
  163 + /*
  164 + * mask all IRQs by setting all bits in the INTMR - default
  165 + */
  166 +
  167 + mov r1, #0xffffffff
  168 + ldr r0, =REG_IHL1_MIR
  169 + str r1, [r0]
  170 + ldr r0, =REG_IHL2_MIR
  171 + str r1, [r0]
  172 + bl cpu_init_crit
  173 +
  174 +relocate:
  175 + /*
  176 + * relocate armboot to RAM
  177 + */
  178 + adr r0, _start /* r0 <- current position of code */
  179 + ldr r2, _armboot_start
  180 + ldr r3, _armboot_end
  181 + sub r2, r3, r2 /* r2 <- size of armboot */
  182 + ldr r1, _TEXT_BASE /* r1 <- destination address */
  183 + add r2, r0, r2 /* r2 <- source end address */
  184 +
  185 + /*
  186 + * r0 = source address
  187 + * r1 = target address
  188 + * r2 = source end address
  189 + */
  190 +copy_loop:
  191 + ldmia r0!, {r3-r10}
  192 + stmia r1!, {r3-r10}
  193 + cmp r0, r2
  194 + ble copy_loop
  195 +
  196 + /* set up the stack */
  197 + ldr r0, _armboot_end
  198 + add r0, r0, #CONFIG_STACKSIZE
  199 + sub sp, r0, #12 /* leave 3 words for abort-stack */
  200 +
  201 + ldr pc, _start_armboot
  202 +
  203 +_start_armboot:
  204 + .word start_armboot
  205 +
  206 +
  207 +/*
  208 + *************************************************************************
  209 + *
  210 + * CPU_init_critical registers
  211 + *
  212 + * setup important registers
  213 + * setup memory timing
  214 + *
  215 + *************************************************************************
  216 + */
  217 +
  218 +
  219 +cpu_init_crit:
  220 + /*
  221 + * flush v4 I/D caches
  222 + */
  223 + mov r0, #0
  224 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  225 + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  226 +
  227 + /*
  228 + * disable MMU stuff and caches
  229 + */
  230 + mrc p15, 0, r0, c1, c0, 0
  231 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
  232 + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
  233 + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
  234 + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  235 + mcr p15, 0, r0, c1, c0, 0
  236 +
  237 + /*
  238 + * Go setup Memory and board specific bits prior to relocation.
  239 + */
  240 + mov ip, lr /* perserve link reg across call */
  241 + bl platformsetup /* go setup pll,mux,memory */
  242 + mov lr, ip /* restore link */
  243 + mov pc, lr /* back to my caller */
  244 +/*
  245 + *************************************************************************
  246 + *
  247 + * Interrupt handling
  248 + *
  249 + *************************************************************************
  250 + */
  251 +
  252 +@
  253 +@ IRQ stack frame.
  254 +@
  255 +#define S_FRAME_SIZE 72
  256 +
  257 +#define S_OLD_R0 68
  258 +#define S_PSR 64
  259 +#define S_PC 60
  260 +#define S_LR 56
  261 +#define S_SP 52
  262 +
  263 +#define S_IP 48
  264 +#define S_FP 44
  265 +#define S_R10 40
  266 +#define S_R9 36
  267 +#define S_R8 32
  268 +#define S_R7 28
  269 +#define S_R6 24
  270 +#define S_R5 20
  271 +#define S_R4 16
  272 +#define S_R3 12
  273 +#define S_R2 8
  274 +#define S_R1 4
  275 +#define S_R0 0
  276 +
  277 +#define MODE_SVC 0x13
  278 +#define I_BIT 0x80
  279 +
  280 +/*
  281 + * use bad_save_user_regs for abort/prefetch/undef/swi ...
  282 + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  283 + */
  284 +
  285 + .macro bad_save_user_regs
  286 + @ carve out a frame on current user stack
  287 + sub sp, sp, #S_FRAME_SIZE
  288 + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
  289 + ldr r2, _armboot_end @ find top of stack
  290 + add r2, r2, #CONFIG_STACKSIZE @ find base of normal stack
  291 + sub r2, r2, #8 @ set base 2 words into abort stack
  292 + @ get values for "aborted" pc and cpsr (into parm regs)
  293 + ldmia r2, {r2 - r3}
  294 + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  295 + add r5, sp, #S_SP
  296 + mov r1, lr
  297 + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  298 + mov r0, sp @ save current stack into r0 (param register)
  299 + .endm
  300 +
  301 + .macro irq_save_user_regs
  302 + sub sp, sp, #S_FRAME_SIZE
  303 + stmia sp, {r0 - r12} @ Calling r0-r12
  304 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
  305 + add r8, sp, #S_PC
  306 + stmdb r8, {sp, lr}^ @ Calling SP, LR
  307 + str lr, [r8, #0] @ Save calling PC
  308 + mrs r6, spsr
  309 + str r6, [r8, #4] @ Save CPSR
  310 + str r0, [r8, #8] @ Save OLD_R0
  311 + mov r0, sp
  312 + .endm
  313 +
  314 + .macro irq_restore_user_regs
  315 + ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  316 + mov r0, r0
  317 + ldr lr, [sp, #S_PC] @ Get PC
  318 + add sp, sp, #S_FRAME_SIZE
  319 + subs pc, lr, #4 @ return & move spsr_svc into cpsr
  320 + .endm
  321 +
  322 + .macro get_bad_stack
  323 + @ get bottom of stack (into sp by by user stack pointer).
  324 + ldr r13, _armboot_end
  325 + @ head to reserved words at the top of the stack
  326 + add r13, r13, #CONFIG_STACKSIZE
  327 + sub r13, r13, #8 @ reserved a couple spots in abort stack
  328 +
  329 + str lr, [r13] @ save caller lr in position 0 of saved stack
  330 + mrs lr, spsr @ get the spsr
  331 + str lr, [r13, #4] @ save spsr in position 1 of saved stack
  332 + mov r13, #MODE_SVC @ prepare SVC-Mode
  333 + @ msr spsr_c, r13
  334 + msr spsr, r13 @ switch modes, make sure moves will execute
  335 + mov lr, pc @ capture return pc
  336 + movs pc, lr @ jump to next instruction & switch modes.
  337 + .endm
  338 +
  339 + .macro get_irq_stack @ setup IRQ stack
  340 + ldr sp, IRQ_STACK_START
  341 + .endm
  342 +
  343 + .macro get_fiq_stack @ setup FIQ stack
  344 + ldr sp, FIQ_STACK_START
  345 + .endm
  346 +
  347 +/*
  348 + * exception handlers
  349 + */
  350 + .align 5
  351 +undefined_instruction:
  352 + get_bad_stack
  353 + bad_save_user_regs
  354 + bl do_undefined_instruction
  355 +
  356 + .align 5
  357 +software_interrupt:
  358 + get_bad_stack
  359 + bad_save_user_regs
  360 + bl do_software_interrupt
  361 +
  362 + .align 5
  363 +prefetch_abort:
  364 + get_bad_stack
  365 + bad_save_user_regs
  366 + bl do_prefetch_abort
  367 +
  368 + .align 5
  369 +data_abort:
  370 + get_bad_stack
  371 + bad_save_user_regs
  372 + bl do_data_abort
  373 +
  374 + .align 5
  375 +not_used:
  376 + get_bad_stack
  377 + bad_save_user_regs
  378 + bl do_not_used
  379 +
  380 +#ifdef CONFIG_USE_IRQ
  381 +
  382 + .align 5
  383 +irq:
  384 + get_irq_stack
  385 + irq_save_user_regs
  386 + bl do_irq
  387 + irq_restore_user_regs
  388 +
  389 + .align 5
  390 +fiq:
  391 + get_fiq_stack
  392 + /* someone ought to write a more effiction fiq_save_user_regs */
  393 + irq_save_user_regs
  394 + bl do_fiq
  395 + irq_restore_user_regs
  396 +
  397 +#else
  398 +
  399 + .align 5
  400 +irq:
  401 + get_bad_stack
  402 + bad_save_user_regs
  403 + bl do_irq
  404 +
  405 + .align 5
  406 +fiq:
  407 + get_bad_stack
  408 + bad_save_user_regs
  409 + bl do_fiq
  410 +
  411 +#endif
  412 +
  413 + .align 5
  414 +.globl reset_cpu
  415 +reset_cpu:
  416 + ldr r1, rstctl1 /* get clkm1 reset ctl */
  417 + mov r3, #0x0
  418 + strh r3, [r1] /* clear it */
  419 + mov r3, #0x8
  420 + strh r3, [r1] /* force dsp+arm reset */
  421 +_loop_forever:
  422 + b _loop_forever
  423 +
  424 +
  425 +rstctl1:
  426 + .word 0xfffece10
... ... @@ -26,10 +26,9 @@
26 26 com_port->lcr = LCRVAL;
27 27 com_port->mcr = MCRVAL;
28 28 com_port->fcr = FCRVAL;
29   -#ifdef CONFIG_OMAP1510
30   - com_port->mdr1 = 0; /* select uart mode */
  29 +#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)
  30 + com_port->mdr1 = 0; /* select uart mode */
31 31 #endif
32   -
33 32 }
34 33  
35 34 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
... ... @@ -53,6 +53,12 @@
53 53 }
54 54 console->osc_12m_sel = 0; /* clear if previsouly set */
55 55 #endif
  56 +#ifdef CONFIG_OMAP1610
  57 + /* If can't cleanly clock 115200 set div to 1 */
  58 + if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
  59 + return (26); /* return 26 for base divisor */
  60 + }
  61 +#endif
56 62 return (CFG_NS16550_CLK / 16 / gd->baudrate);
57 63 }
58 64  
  1 +/************************************************
  2 + * NAME arm926ejs.h *
  3 + * Version : 23 June 2003 *
  4 + ************************************************/
  5 +/* Currently empty */
  6 +#ifndef __ARM926EJS_H__
  7 +#define __ARM926EJS_H__
  8 +#endif /*__ARM926EJS_H__*/
include/asm-arm/arch-arm926ejs/sizes.h
Diff comments   View file @ 6f21347
  1 +/*
  2 + * This program is free software; you can redistribute it and/or modify
  3 + * it under the terms of the GNU General Public License as published by
  4 + * the Free Software Foundation; either version 2 of the License, or
  5 + * (at your option) any later version.
  6 + *
  7 + * This program is distributed in the hope that it will be useful,
  8 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10 + * GNU General Public License for more details.
  11 + *
  12 + * You should have received a copy of the GNU General Public License
  13 + * along with this program; if not, write to the Free Software
  14 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
  15 + * USA
  16 + */
  17 +/* DO NOT EDIT!! - this file automatically generated
  18 + * from .s file by awk -f s2h.awk
  19 + */
  20 +/* Size defintions
  21 + * Copyright (C) ARM Limited 1998. All rights reserved.
  22 + */
  23 +
  24 +#ifndef __sizes_h
  25 +#define __sizes_h 1
  26 +
  27 +/* handy sizes */
  28 +#define SZ_1K 0x00000400
  29 +#define SZ_4K 0x00001000
  30 +#define SZ_8K 0x00002000
  31 +#define SZ_16K 0x00004000
  32 +#define SZ_64K 0x00010000
  33 +#define SZ_128K 0x00020000
  34 +#define SZ_256K 0x00040000
  35 +#define SZ_512K 0x00080000
  36 +
  37 +#define SZ_1M 0x00100000
  38 +#define SZ_2M 0x00200000
  39 +#define SZ_4M 0x00400000
  40 +#define SZ_8M 0x00800000
  41 +#define SZ_16M 0x01000000
  42 +#define SZ_32M 0x02000000
  43 +#define SZ_64M 0x04000000
  44 +#define SZ_128M 0x08000000
  45 +#define SZ_256M 0x10000000
  46 +#define SZ_512M 0x20000000
  47 +
  48 +#define SZ_1G 0x40000000
  49 +#define SZ_2G 0x80000000
  50 +
  51 +#endif /* __sizes_h */
include/configs/omap1510.h
Diff comments   View file @ 6f21347
... ... @@ -175,6 +175,18 @@
175 175  
176 176 #define MOD_CONF_CTRL_0 0xfffe1080
177 177  
  178 +#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */
  179 +
  180 +#define USB_OTG_CTRL 0xFFFB040C
  181 +#define USB_TRANSCEIVER_CTRL 0xFFFE1064
  182 +#define PULL_DWN_CTRL_4 0xFFFE10AC
  183 +#define PU_PD_SEL_0 0xFFFE10B4
  184 +#define PU_PD_SEL_1 0xFFFE10B8
  185 +#define PU_PD_SEL_2 0xFFFE10BC
  186 +#define PU_PD_SEL_3 0xFFFE10C0
  187 +#define PU_PD_SEL_4 0xFFFE10C4
  188 +
  189 +#endif
178 190 /*
179 191 * Traffic Controller Memory Interface Registers
180 192 */
... ... @@ -519,6 +531,7 @@
519 531  
520 532 /* WDTIM_CONTROL bit definitions. */
521 533 #define WDTIM_CONTROL_ST BIT7
  534 +
522 535  
523 536  
524 537 /* ---------------------------------------------------------------------------
include/configs/omap1610inn.h
Diff comments   View file @ 6f21347
  1 +/*
  2 + * (C) Copyright 2003
  3 + * Texas Instruments.
  4 + * Kshitij Gupta <kshitij@ti.com>
  5 + * Configuation settings for the TI OMAP Innovator board.
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#ifndef __CONFIG_H
  27 +#define __CONFIG_H
  28 +
  29 +/*
  30 + * High Level Configuration Options
  31 + * (easy to change)
  32 + */
  33 +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
  34 +#define CONFIG_OMAP 1 /* in a TI OMAP core */
  35 +#define CONFIG_OMAP1610 1 /* which is in a 1610 */
  36 +#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */
  37 +
  38 +/* input clock of PLL */
  39 +/* the OMAP1610 Innovator has 12MHz input clock */
  40 +#define CONFIG_SYS_CLK_FREQ 12000000
  41 +
  42 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  43 +
  44 +#define CONFIG_MISC_INIT_R
  45 +
  46 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  47 +#define CONFIG_SETUP_MEMORY_TAGS 1
  48 +
  49 +/*
  50 + * Size of malloc() pool
  51 + */
  52 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
  53 +
  54 +/*
  55 + * Hardware drivers
  56 + */
  57 +/*
  58 +*/
  59 +#define CONFIG_DRIVER_LAN91C96
  60 +#define CONFIG_LAN91C96_BASE 0x04000300
  61 +#define CONFIG_LAN91C96_EXT_PHY
  62 +
  63 +/*
  64 + * NS16550 Configuration
  65 + */
  66 +#define CFG_NS16550
  67 +#define CFG_NS16550_SERIAL
  68 +#define CFG_NS16550_REG_SIZE (-4)
  69 +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
  70 +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
  71 + on helen */
  72 +
  73 +/*
  74 + * select serial console configuration
  75 + */
  76 +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */
  77 +
  78 +/* allow to overwrite serial and ethaddr */
  79 +#define CONFIG_ENV_OVERWRITE
  80 +#define CONFIG_CONS_INDEX 1
  81 +#define CONFIG_BAUDRATE 115200
  82 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  83 +
  84 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
  85 +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
  86 +
  87 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  88 +#include <cmd_confdefs.h>
  89 +#include <configs/omap1510.h>
  90 +
  91 +#define CONFIG_BOOTDELAY 3
  92 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
  93 + root=/dev/nfs rw nfsroot=157.87.82.48:\
  94 + /home/a0875451/mwd/myfs/target ip=dhcp"
  95 +#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
  96 +#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
  97 +#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
  98 +#define CONFIG_BOOTFILE "uImage" /* file to load */
  99 +
  100 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  101 +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
  102 +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
  103 +#endif
  104 +
  105 +/*
  106 + * Miscellaneous configurable options
  107 + */
  108 +#define CFG_LONGHELP /* undef to save memory */
  109 +#define CFG_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */
  110 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  111 +/* Print Buffer Size */
  112 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
  113 +#define CFG_MAXARGS 16 /* max number of command args */
  114 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  115 +
  116 +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
  117 +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
  118 +
  119 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  120 +
  121 +#define CFG_LOAD_ADDR 0x10000000 /* default load address */
  122 +
  123 +/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
  124 + * DPLL1. This time is further subdivided by a local divisor.
  125 + */
  126 +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
  127 +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
  128 +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
  129 +
  130 +/*-----------------------------------------------------------------------
  131 + * Stack sizes
  132 + *
  133 + * The stack sizes are set up in start.S using the settings below
  134 + */
  135 +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
  136 +#ifdef CONFIG_USE_IRQ
  137 +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  138 +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  139 +#endif
  140 +
  141 +/*-----------------------------------------------------------------------
  142 + * Physical Memory Map
  143 + */
  144 +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  145 +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
  146 +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
  147 +
  148 +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  149 +
  150 +#define CFG_FLASH_BASE PHYS_FLASH_1
  151 +
  152 +/*-----------------------------------------------------------------------
  153 + * FLASH and environment organization
  154 + */
  155 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  156 +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
  157 +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
  158 +/* addr of environment */
  159 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
  160 +
  161 +/* timeout values are in ticks */
  162 +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
  163 +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
  164 +
  165 +#define CFG_ENV_IS_IN_FLASH 1
  166 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
  167 +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
  168 +
  169 +#endif /* __CONFIG_H */
... ... @@ -213,6 +213,7 @@
213 213 #define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
214 214 #define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
215 215 #define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
  216 +#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
216 217  
217 218 #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
218 219 #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
... ... @@ -319,6 +320,8 @@
319 320 #define FLASH_AMLV320U 0x00A2 /* AMD 29LV128M ( 128M = 8M x 16 ) */
320 321 #define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
321 322 #define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
  323 +/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
  324 +#define FLASH_28F256L18T 0x00A8
322 325  
323 326 #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
324 327  
... ... @@ -60,8 +60,10 @@
60 60 int pad7:24;
61 61 unsigned char scr; /* 7 */
62 62 int pad8:24;
63   -#ifdef CONFIG_OMAP1510
  63 +#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)
64 64 unsigned char mdr1; /* mode select reset TL16C750*/
  65 +#endif
  66 +#ifdef CONFIG_OMAP1510
65 67 int pad9:24;
66 68 unsigned long pad[10];
67 69 unsigned char osc_12m_sel;