Commit 70311e69fa7f0b7c289eb6552ccc3f9fb7320c69

Authored by Marek Vasut
1 parent ef4b01b2f7

arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded data

This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>

Showing 4 changed files with 22 additions and 5 deletions Side-by-side Diff

arch/arm/dts/socfpga_arria5_socdk.dts
... ... @@ -25,6 +25,7 @@
25 25 * to be added to the gmac1 device tree blob.
26 26 */
27 27 ethernet0 = &gmac1;
  28 + udc0 = &usb1;
28 29 };
29 30  
30 31 regulator_3_3v: 3-3-v-regulator {
board/altera/arria5-socdk/socfpga.c
... ... @@ -5,12 +5,12 @@
5 5 */
6 6  
7 7 #include <common.h>
  8 +#include <errno.h>
8 9 #include <asm/arch/reset_manager.h>
9 10 #include <asm/io.h>
10 11  
11 12 #include <usb.h>
12 13 #include <usb/dwc2_udc.h>
13   -#include <usb_mass_storage.h>
14 14  
15 15 DECLARE_GLOBAL_DATA_PTR;
16 16  
17 17  
... ... @@ -29,12 +29,29 @@
29 29  
30 30 #ifdef CONFIG_USB_GADGET
31 31 struct dwc2_plat_otg_data socfpga_otg_data = {
32   - .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
33 32 .usb_gusbcfg = 0x1417,
34 33 };
35 34  
36 35 int board_usb_init(int index, enum usb_init_type init)
37 36 {
  37 + int node[2], count;
  38 + fdt_addr_t addr;
  39 +
  40 + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
  41 + COMPAT_ALTERA_SOCFPGA_DWC2USB,
  42 + node, 2);
  43 + if (count <= 0) /* No controller found. */
  44 + return 0;
  45 +
  46 + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
  47 + if (addr == FDT_ADDR_T_NONE) {
  48 + printf("UDC Controller has no 'reg' property!\n");
  49 + return -EINVAL;
  50 + }
  51 +
  52 + /* Patch the address from OF into the controller pdata. */
  53 + socfpga_otg_data.regs_otg = addr;
  54 +
38 55 return dwc2_udc_probe(&socfpga_otg_data);
39 56 }
40 57  
configs/socfpga_arria5_defconfig
... ... @@ -21,4 +21,6 @@
21 21 CONFIG_CADENCE_QSPI=y
22 22 CONFIG_DESIGNWARE_SPI=y
23 23 CONFIG_DM_MMC=y
  24 +CONFIG_USB=y
  25 +CONFIG_DM_USB=y
include/configs/socfpga_arria5_socdk.h
... ... @@ -56,9 +56,6 @@
56 56 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */
57 57  
58 58 /* USB */
59   -#ifdef CONFIG_CMD_USB
60   -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
61   -#endif
62 59 #define CONFIG_G_DNL_MANUFACTURER "Altera"
63 60  
64 61 /* Extra Environment */