Commit 7056efcc32081256af6172611874709c780f2007
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arm: socfpga: nic301: Add NIC-301 GPV register file
Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 195 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-socfpga/nic301.h
| 1 | +/* | |
| 2 | + * Copyright (C) 2014 Marek Vasut <marex@denx.de> | |
| 3 | + * | |
| 4 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef _NIC301_REGISTERS_H_ | |
| 8 | +#define _NIC301_REGISTERS_H_ | |
| 9 | + | |
| 10 | +struct nic301_registers { | |
| 11 | + u32 remap; /* 0x0 */ | |
| 12 | + /* Security Register Group */ | |
| 13 | + u32 _pad_0x4_0x8[1]; | |
| 14 | + u32 l4main; | |
| 15 | + u32 l4sp; | |
| 16 | + u32 l4mp; /* 0x10 */ | |
| 17 | + u32 l4osc1; | |
| 18 | + u32 l4spim; | |
| 19 | + u32 stm; | |
| 20 | + u32 lwhps2fpgaregs; /* 0x20 */ | |
| 21 | + u32 _pad_0x24_0x28[1]; | |
| 22 | + u32 usb1; | |
| 23 | + u32 nanddata; | |
| 24 | + u32 _pad_0x30_0x80[20]; | |
| 25 | + u32 usb0; /* 0x80 */ | |
| 26 | + u32 nandregs; | |
| 27 | + u32 qspidata; | |
| 28 | + u32 fpgamgrdata; | |
| 29 | + u32 hps2fpgaregs; /* 0x90 */ | |
| 30 | + u32 acp; | |
| 31 | + u32 rom; | |
| 32 | + u32 ocram; | |
| 33 | + u32 sdrdata; /* 0xA0 */ | |
| 34 | + u32 _pad_0xa4_0x1fd0[1995]; | |
| 35 | + /* ID Register Group */ | |
| 36 | + u32 periph_id_4; /* 0x1FD0 */ | |
| 37 | + u32 _pad_0x1fd4_0x1fe0[3]; | |
| 38 | + u32 periph_id_0; /* 0x1FE0 */ | |
| 39 | + u32 periph_id_1; | |
| 40 | + u32 periph_id_2; | |
| 41 | + u32 periph_id_3; | |
| 42 | + u32 comp_id_0; /* 0x1FF0 */ | |
| 43 | + u32 comp_id_1; | |
| 44 | + u32 comp_id_2; | |
| 45 | + u32 comp_id_3; | |
| 46 | + u32 _pad_0x2000_0x2008[2]; | |
| 47 | + /* L4 MAIN */ | |
| 48 | + u32 l4main_fn_mod_bm_iss; | |
| 49 | + u32 _pad_0x200c_0x3008[1023]; | |
| 50 | + /* L4 SP */ | |
| 51 | + u32 l4sp_fn_mod_bm_iss; | |
| 52 | + u32 _pad_0x300c_0x4008[1023]; | |
| 53 | + /* L4 MP */ | |
| 54 | + u32 l4mp_fn_mod_bm_iss; | |
| 55 | + u32 _pad_0x400c_0x5008[1023]; | |
| 56 | + /* L4 OSC1 */ | |
| 57 | + u32 l4osc_fn_mod_bm_iss; | |
| 58 | + u32 _pad_0x500c_0x6008[1023]; | |
| 59 | + /* L4 SPIM */ | |
| 60 | + u32 l4spim_fn_mod_bm_iss; | |
| 61 | + u32 _pad_0x600c_0x7008[1023]; | |
| 62 | + /* STM */ | |
| 63 | + u32 stm_fn_mod_bm_iss; | |
| 64 | + u32 _pad_0x700c_0x7108[63]; | |
| 65 | + u32 stm_fn_mod; | |
| 66 | + u32 _pad_0x710c_0x8008[959]; | |
| 67 | + /* LWHPS2FPGA */ | |
| 68 | + u32 lwhps2fpga_fn_mod_bm_iss; | |
| 69 | + u32 _pad_0x800c_0x8108[63]; | |
| 70 | + u32 lwhps2fpga_fn_mod; | |
| 71 | + u32 _pad_0x810c_0xa008[1983]; | |
| 72 | + /* USB1 */ | |
| 73 | + u32 usb1_fn_mod_bm_iss; | |
| 74 | + u32 _pad_0xa00c_0xa044[14]; | |
| 75 | + u32 usb1_ahb_cntl; | |
| 76 | + u32 _pad_0xa048_0xb008[1008]; | |
| 77 | + /* NANDDATA */ | |
| 78 | + u32 nanddata_fn_mod_bm_iss; | |
| 79 | + u32 _pad_0xb00c_0xb108[63]; | |
| 80 | + u32 nanddata_fn_mod; | |
| 81 | + u32 _pad_0xb10c_0x20008[21439]; | |
| 82 | + /* USB0 */ | |
| 83 | + u32 usb0_fn_mod_bm_iss; | |
| 84 | + u32 _pad_0x2000c_0x20044[14]; | |
| 85 | + u32 usb0_ahb_cntl; | |
| 86 | + u32 _pad_0x20048_0x21008[1008]; | |
| 87 | + /* NANDREGS */ | |
| 88 | + u32 nandregs_fn_mod_bm_iss; | |
| 89 | + u32 _pad_0x2100c_0x21108[63]; | |
| 90 | + u32 nandregs_fn_mod; | |
| 91 | + u32 _pad_0x2110c_0x22008[959]; | |
| 92 | + /* QSPIDATA */ | |
| 93 | + u32 qspidata_fn_mod_bm_iss; | |
| 94 | + u32 _pad_0x2200c_0x22044[14]; | |
| 95 | + u32 qspidata_ahb_cntl; | |
| 96 | + u32 _pad_0x22048_0x23008[1008]; | |
| 97 | + /* FPGAMGRDATA */ | |
| 98 | + u32 fpgamgrdata_fn_mod_bm_iss; | |
| 99 | + u32 _pad_0x2300c_0x23040[13]; | |
| 100 | + u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ | |
| 101 | + u32 _pad_0x23044_0x23108[49]; | |
| 102 | + u32 fn_mod; | |
| 103 | + u32 _pad_0x2310c_0x24008[959]; | |
| 104 | + /* HPS2FPGA */ | |
| 105 | + u32 hps2fpga_fn_mod_bm_iss; | |
| 106 | + u32 _pad_0x2400c_0x24040[13]; | |
| 107 | + u32 hps2fpga_wr_tidemark; /* 0x24040 */ | |
| 108 | + u32 _pad_0x24044_0x24108[49]; | |
| 109 | + u32 hps2fpga_fn_mod; | |
| 110 | + u32 _pad_0x2410c_0x25008[959]; | |
| 111 | + /* ACP */ | |
| 112 | + u32 acp_fn_mod_bm_iss; | |
| 113 | + u32 _pad_0x2500c_0x25108[63]; | |
| 114 | + u32 acp_fn_mod; | |
| 115 | + u32 _pad_0x2510c_0x26008[959]; | |
| 116 | + /* Boot ROM */ | |
| 117 | + u32 bootrom_fn_mod_bm_iss; | |
| 118 | + u32 _pad_0x2600c_0x26108[63]; | |
| 119 | + u32 bootrom_fn_mod; | |
| 120 | + u32 _pad_0x2610c_0x27008[959]; | |
| 121 | + /* On-chip RAM */ | |
| 122 | + u32 ocram_fn_mod_bm_iss; | |
| 123 | + u32 _pad_0x2700c_0x27040[13]; | |
| 124 | + u32 ocram_wr_tidemark; /* 0x27040 */ | |
| 125 | + u32 _pad_0x27044_0x27108[49]; | |
| 126 | + u32 ocram_fn_mod; | |
| 127 | + u32 _pad_0x2710c_0x42024[27590]; | |
| 128 | + /* DAP */ | |
| 129 | + u32 dap_fn_mod2; | |
| 130 | + u32 dap_fn_mod_ahb; | |
| 131 | + u32 _pad_0x4202c_0x42100[53]; | |
| 132 | + u32 dap_read_qos; /* 0x42100 */ | |
| 133 | + u32 dap_write_qos; | |
| 134 | + u32 dap_fn_mod; | |
| 135 | + u32 _pad_0x4210c_0x43100[1021]; | |
| 136 | + /* MPU */ | |
| 137 | + u32 mpu_read_qos; /* 0x43100 */ | |
| 138 | + u32 mpu_write_qos; | |
| 139 | + u32 mpu_fn_mod; | |
| 140 | + u32 _pad_0x4310c_0x44028[967]; | |
| 141 | + /* SDMMC */ | |
| 142 | + u32 sdmmc_fn_mod_ahb; | |
| 143 | + u32 _pad_0x4402c_0x44100[53]; | |
| 144 | + u32 sdmmc_read_qos; /* 0x44100 */ | |
| 145 | + u32 sdmmc_write_qos; | |
| 146 | + u32 sdmmc_fn_mod; | |
| 147 | + u32 _pad_0x4410c_0x45100[1021]; | |
| 148 | + /* DMA */ | |
| 149 | + u32 dma_read_qos; /* 0x45100 */ | |
| 150 | + u32 dma_write_qos; | |
| 151 | + u32 dma_fn_mod; | |
| 152 | + u32 _pad_0x4510c_0x46040[973]; | |
| 153 | + /* FPGA2HPS */ | |
| 154 | + u32 fpga2hps_wr_tidemark; /* 0x46040 */ | |
| 155 | + u32 _pad_0x46044_0x46100[47]; | |
| 156 | + u32 fpga2hps_read_qos; /* 0x46100 */ | |
| 157 | + u32 fpga2hps_write_qos; | |
| 158 | + u32 fpga2hps_fn_mod; | |
| 159 | + u32 _pad_0x4610c_0x47100[1021]; | |
| 160 | + /* ETR */ | |
| 161 | + u32 etr_read_qos; /* 0x47100 */ | |
| 162 | + u32 etr_write_qos; | |
| 163 | + u32 etr_fn_mod; | |
| 164 | + u32 _pad_0x4710c_0x48100[1021]; | |
| 165 | + /* EMAC0 */ | |
| 166 | + u32 emac0_read_qos; /* 0x48100 */ | |
| 167 | + u32 emac0_write_qos; | |
| 168 | + u32 emac0_fn_mod; | |
| 169 | + u32 _pad_0x4810c_0x49100[1021]; | |
| 170 | + /* EMAC1 */ | |
| 171 | + u32 emac1_read_qos; /* 0x49100 */ | |
| 172 | + u32 emac1_write_qos; | |
| 173 | + u32 emac1_fn_mod; | |
| 174 | + u32 _pad_0x4910c_0x4a028[967]; | |
| 175 | + /* USB0 */ | |
| 176 | + u32 usb0_fn_mod_ahb; | |
| 177 | + u32 _pad_0x4a02c_0x4a100[53]; | |
| 178 | + u32 usb0_read_qos; /* 0x4A100 */ | |
| 179 | + u32 usb0_write_qos; | |
| 180 | + u32 usb0_fn_mod; | |
| 181 | + u32 _pad_0x4a10c_0x4b100[1021]; | |
| 182 | + /* NAND */ | |
| 183 | + u32 nand_read_qos; /* 0x4B100 */ | |
| 184 | + u32 nand_write_qos; | |
| 185 | + u32 nand_fn_mod; | |
| 186 | + u32 _pad_0x4b10c_0x4c028[967]; | |
| 187 | + /* USB1 */ | |
| 188 | + u32 usb1_fn_mod_ahb; | |
| 189 | + u32 _pad_0x4c02c_0x4c100[53]; | |
| 190 | + u32 usb1_read_qos; /* 0x4C100 */ | |
| 191 | + u32 usb1_write_qos; | |
| 192 | + u32 usb1_fn_mod; | |
| 193 | +}; | |
| 194 | + | |
| 195 | +#endif /* _NIC301_REGISTERS_H_ */ |