Eric Lee / smarc-uboot

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Commit 7081a123c601496c5a469c2bc3e0d74f269e9b11

Authored by Ye Li
1 parent b531b8098c
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-21889-11 imx8mn_evk: Add board codes and defconfig for iMX8M Nano EVK 

Add board level codes, header file, and defconfig for iMX8M Nano EVK
board. The board has similar design as iMX8MM EVK.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 01aa313aeb8df58a58bd1c7481e25fa89b42da2a)

Showing 9 changed files with 2562 additions and 1 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 7081a12
... ... @@ -629,7 +629,7 @@
629 629 fsl-imx8mm-evk.dtb \
630 630 fsl-imx8mm-ddr3l-val.dtb \
631 631 fsl-imx8mm-ddr4-evk.dtb \
632   - fsl-imx8mm-ddr4-val.dtb
  632 + fsl-imx8mm-ddr4-val.dtb \
633 633 fsl-imx8mm-evk.dtb \
634 634 fsl-imx8mn-ddr4-evk.dtb
635 635  
arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ 7081a12
... ... @@ -60,12 +60,20 @@
60 60 bool "imx8mm DDR4 EVK board"
61 61 select IMX8MM
62 62 select IMX8M_DDR4
  63 +
  64 +config TARGET_IMX8MN_EVK
  65 + bool "imx8mn DDR4 EVK board"
  66 + select IMX8MN
  67 + select SUPPORT_SPL
  68 + select IMX8M_DDR4
  69 +
63 70 endchoice
64 71  
65 72 source "board/freescale/imx8mq_evk/Kconfig"
66 73 source "board/freescale/imx8mq_arm2/Kconfig"
67 74 source "board/freescale/imx8mm_evk/Kconfig"
68 75 source "board/freescale/imx8mm_val/Kconfig"
  76 +source "board/freescale/imx8mn_evk/Kconfig"
69 77  
70 78 endif
board/freescale/imx8mn_evk/Kconfig
Diff comments   View file @ 7081a12
  1 +if TARGET_IMX8MN_EVK
  2 +
  3 +config SYS_BOARD
  4 + default "imx8mn_evk"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx8mn_evk"
  11 +
  12 +source "board/freescale/common/Kconfig"
  13 +
  14 +endif
board/freescale/imx8mn_evk/Makefile
Diff comments   View file @ 7081a12
  1 +#
  2 +# Copyright 2018 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += imx8mn_evk.o
  8 +
  9 +ifdef CONFIG_SPL_BUILD
  10 +obj-y += spl.o
  11 +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
  12 +endif
board/freescale/imx8mn_evk/ddr4_timing.c
Diff comments   View file @ 7081a12
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2019 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Generated code from MX8M_DDR_tool
  7 + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
  8 + */
  9 +
  10 +#include <linux/kernel.h>
  11 +#include <asm/arch/ddr.h>
  12 +
  13 +struct dram_cfg_param ddr_ddrc_cfg[] = {
  14 + {0x3d400000,0x81040010},
  15 + {0x3d400030,0x00000020},
  16 + {0x3d400034,0x00221306},
  17 + {0x3d400050,0x00210070},
  18 + {0x3d400054,0x00010008},
  19 + {0x3d400060,0x00000000},
  20 + {0x3d400064,0x0092014a},
  21 + {0x3d4000c0,0x00000000},
  22 + {0x3d4000c4,0x00001000},
  23 + {0x3d4000d0,0xc0030126},
  24 + {0x3d4000d4,0x00770000},
  25 + {0x3d4000dc,0x08340105},
  26 + {0x3d4000e0,0x00180200},
  27 + {0x3d4000e4,0x00110000},
  28 + {0x3d4000e8,0x02000740},
  29 + {0x3d4000ec,0x00000850},
  30 + {0x3d4000f4,0x00000ec7},
  31 + {0x3d400100,0x11122914},
  32 + {0x3d400104,0x0004051c},
  33 + {0x3d400108,0x0608050d},
  34 + {0x3d40010c,0x0000400c},
  35 + {0x3d400110,0x08030409},
  36 + {0x3d400114,0x06060403},
  37 + {0x3d40011c,0x00000606},
  38 + {0x3d400120,0x07070d0c},
  39 + {0x3d400124,0x0002040a},
  40 + {0x3d40012c,0x1809010e},
  41 + {0x3d400130,0x00000008},
  42 + {0x3d40013c,0x00000000},
  43 + {0x3d400180,0x01000040},
  44 + {0x3d400184,0x0000493e},
  45 + {0x3d400190,0x038b8207},
  46 + {0x3d400194,0x02020303},
  47 + {0x3d400198,0x07f04011},
  48 + {0x3d40019c,0x000000b0},
  49 + {0x3d4001a0,0xe0400018},
  50 + {0x3d4001a4,0x0048005a},
  51 + {0x3d4001a8,0x80000000},
  52 + {0x3d4001b0,0x00000001},
  53 + {0x3d4001b4,0x00000b07},
  54 + {0x3d4001b8,0x00000004},
  55 + {0x3d4001c0,0x00000001},
  56 + {0x3d4001c4,0x00000000},
  57 + {0x3d400240,0x06000610},
  58 + {0x3d400244,0x00001323},
  59 + {0x3d400200,0x00003f1f},
  60 + {0x3d400204,0x003f0909},
  61 + {0x3d400208,0x01010100},
  62 + {0x3d40020c,0x01010101},
  63 + {0x3d400210,0x00001f1f},
  64 + {0x3d400214,0x07070707},
  65 + {0x3d400218,0x07070707},
  66 + {0x3d40021c,0x00000f07},
  67 + {0x3d400220,0x00003f01},
  68 + {0x3d402050,0x00210070},
  69 + {0x3d402064,0x00180037},
  70 + {0x3d4020dc,0x00000105},
  71 + {0x3d4020e0,0x00000000},
  72 + {0x3d4020e8,0x02000740},
  73 + {0x3d4020ec,0x00000050},
  74 + {0x3d402100,0x08030604},
  75 + {0x3d402104,0x00020205},
  76 + {0x3d402108,0x05050309},
  77 + {0x3d40210c,0x0000400c},
  78 + {0x3d402110,0x02030202},
  79 + {0x3d402114,0x03030202},
  80 + {0x3d402118,0x0a070008},
  81 + {0x3d40211c,0x00000d09},
  82 + {0x3d402120,0x08084b09},
  83 + {0x3d402124,0x00020308},
  84 + {0x3d402128,0x000f0d06},
  85 + {0x3d40212c,0x12060111},
  86 + {0x3d402130,0x00000008},
  87 + {0x3d40213c,0x00000000},
  88 + {0x3d402180,0x01000040},
  89 + {0x3d402190,0x03848204},
  90 + {0x3d402194,0x02020303},
  91 + {0x3d4021b4,0x00000404},
  92 + {0x3d4021b8,0x00000004},
  93 + {0x3d402240,0x07000600},
  94 + {0x3d403050,0x00210070},
  95 + {0x3d403064,0x0006000d},
  96 + {0x3d4030dc,0x00000105},
  97 + {0x3d4030e0,0x00000000},
  98 + {0x3d4030e8,0x02000740},
  99 + {0x3d4030ec,0x00000050},
  100 + {0x3d403100,0x07010101},
  101 + {0x3d403104,0x00020202},
  102 + {0x3d403108,0x05050309},
  103 + {0x3d40310c,0x0000400c},
  104 + {0x3d403110,0x01030201},
  105 + {0x3d403114,0x03030202},
  106 + {0x3d40311c,0x00000303},
  107 + {0x3d403120,0x02020d02},
  108 + {0x3d403124,0x00020208},
  109 + {0x3d403128,0x000f0d06},
  110 + {0x3d40312c,0x0e02010e},
  111 + {0x3d403130,0x00000008},
  112 + {0x3d40313c,0x00000000},
  113 + {0x3d403180,0x01000040},
  114 + {0x3d403190,0x03848204},
  115 + {0x3d403194,0x02020303},
  116 + {0x3d4031b4,0x00000404},
  117 + {0x3d4031b8,0x00000004},
  118 + {0x3d403240,0x07000600},
  119 + {0x3d400400,0x00000100},
  120 + {0x3d400250,0x317d1a07},
  121 + {0x3d400254,0x0000000f},
  122 + {0x3d40025c,0x2a001b76},
  123 + {0x3d400264,0x7300b473},
  124 + {0x3d40026c,0x30000e06},
  125 + {0x3d400300,0x00000014},
  126 + {0x3d40036c,0x00000010},
  127 + {0x3d400404,0x00013193},
  128 + {0x3d400408,0x00006096},
  129 + {0x3d400490,0x00000001},
  130 + {0x3d400494,0x02000c00},
  131 + {0x3d400498,0x003c00db},
  132 + {0x3d40049c,0x00100009},
  133 + {0x3d4004a0,0x00000002},
  134 +
  135 +};
  136 +
  137 +/* PHY Initialize Configuration */
  138 +struct dram_cfg_param ddr_ddrphy_cfg[] = {
  139 + {0x0001005f,0x000002fd},
  140 + {0x0001015f,0x000002fd},
  141 + {0x0001105f,0x000002fd},
  142 + {0x0001115f,0x000002fd},
  143 + {0x0011005f,0x000002fd},
  144 + {0x0011015f,0x000002fd},
  145 + {0x0011105f,0x000002fd},
  146 + {0x0011115f,0x000002fd},
  147 + {0x0021005f,0x000002fd},
  148 + {0x0021015f,0x000002fd},
  149 + {0x0021105f,0x000002fd},
  150 + {0x0021115f,0x000002fd},
  151 + {0x00000055,0x00000355},
  152 + {0x00001055,0x00000355},
  153 + {0x00002055,0x00000355},
  154 + {0x00003055,0x00000355},
  155 + {0x00004055,0x00000055},
  156 + {0x00005055,0x00000055},
  157 + {0x00006055,0x00000355},
  158 + {0x00007055,0x00000355},
  159 + {0x00008055,0x00000355},
  160 + {0x00009055,0x00000355},
  161 + {0x000200c5,0x0000000a},
  162 + {0x001200c5,0x00000007},
  163 + {0x002200c5,0x00000007},
  164 + {0x0002002e,0x00000002},
  165 + {0x0012002e,0x00000002},
  166 + {0x0022002e,0x00000002},
  167 + {0x00020024,0x00000008},
  168 + {0x0002003a,0x00000002},
  169 + {0x0002007d,0x00000212},
  170 + {0x0002007c,0x00000061},
  171 + {0x00120024,0x00000008},
  172 + {0x0002003a,0x00000002},
  173 + {0x0012007d,0x00000212},
  174 + {0x0012007c,0x00000061},
  175 + {0x00220024,0x00000008},
  176 + {0x0002003a,0x00000002},
  177 + {0x0022007d,0x00000212},
  178 + {0x0022007c,0x00000061},
  179 + {0x00020056,0x00000006},
  180 + {0x00120056,0x0000000a},
  181 + {0x00220056,0x0000000a},
  182 + {0x0001004d,0x0000001a},
  183 + {0x0001014d,0x0000001a},
  184 + {0x0001104d,0x0000001a},
  185 + {0x0001114d,0x0000001a},
  186 + {0x0011004d,0x0000001a},
  187 + {0x0011014d,0x0000001a},
  188 + {0x0011104d,0x0000001a},
  189 + {0x0011114d,0x0000001a},
  190 + {0x0021004d,0x0000001a},
  191 + {0x0021014d,0x0000001a},
  192 + {0x0021104d,0x0000001a},
  193 + {0x0021114d,0x0000001a},
  194 + {0x00010049,0x00000e38},
  195 + {0x00010149,0x00000e38},
  196 + {0x00011049,0x00000e38},
  197 + {0x00011149,0x00000e38},
  198 + {0x00110049,0x00000e38},
  199 + {0x00110149,0x00000e38},
  200 + {0x00111049,0x00000e38},
  201 + {0x00111149,0x00000e38},
  202 + {0x00210049,0x00000e38},
  203 + {0x00210149,0x00000e38},
  204 + {0x00211049,0x00000e38},
  205 + {0x00211149,0x00000e38},
  206 + {0x00000043,0x00000063},
  207 + {0x00001043,0x00000063},
  208 + {0x00002043,0x00000063},
  209 + {0x00003043,0x00000063},
  210 + {0x00004043,0x00000063},
  211 + {0x00005043,0x00000063},
  212 + {0x00006043,0x00000063},
  213 + {0x00007043,0x00000063},
  214 + {0x00008043,0x00000063},
  215 + {0x00009043,0x00000063},
  216 + {0x00020018,0x00000001},
  217 + {0x00020075,0x00000002},
  218 + {0x00020050,0x00000000},
  219 + {0x00020008,0x00000258},
  220 + {0x00120008,0x00000064},
  221 + {0x00220008,0x00000019},
  222 + {0x00020088,0x00000009},
  223 + {0x000200b2,0x00000268},
  224 + {0x00010043,0x000005b1},
  225 + {0x00010143,0x000005b1},
  226 + {0x00011043,0x000005b1},
  227 + {0x00011143,0x000005b1},
  228 + {0x001200b2,0x00000268},
  229 + {0x00110043,0x000005b1},
  230 + {0x00110143,0x000005b1},
  231 + {0x00111043,0x000005b1},
  232 + {0x00111143,0x000005b1},
  233 + {0x002200b2,0x00000268},
  234 + {0x00210043,0x000005b1},
  235 + {0x00210143,0x000005b1},
  236 + {0x00211043,0x000005b1},
  237 + {0x00211143,0x000005b1},
  238 + {0x0002005b,0x00007529},
  239 + {0x0002005c,0x00000000},
  240 + {0x000200fa,0x00000001},
  241 + {0x001200fa,0x00000001},
  242 + {0x002200fa,0x00000001},
  243 + {0x00020019,0x00000005},
  244 + {0x00120019,0x00000005},
  245 + {0x00220019,0x00000005},
  246 + {0x000200f0,0x00005665},
  247 + {0x000200f1,0x00005555},
  248 + {0x000200f2,0x00005555},
  249 + {0x000200f3,0x00005555},
  250 + {0x000200f4,0x00005555},
  251 + {0x000200f5,0x00005555},
  252 + {0x000200f6,0x00005555},
  253 + {0x000200f7,0x0000f000},
  254 + {0x0001004a,0x00000500},
  255 + {0x0001104a,0x00000500},
  256 + {0x00020025,0x00000000},
  257 + {0x0002002d,0x00000000},
  258 + {0x0012002d,0x00000000},
  259 + {0x0022002d,0x00000000},
  260 + {0x0002002c,0x00000000},
  261 + {0x000200c7,0x00000021},
  262 + {0x000200ca,0x00000024},
  263 + {0x000200cc,0x000001f7},
  264 + {0x001200c7,0x00000021},
  265 + {0x001200ca,0x00000024},
  266 + {0x001200cc,0x000001f7},
  267 + {0x002200c7,0x00000021},
  268 + {0x002200ca,0x00000024},
  269 + {0x002200cc,0x000001f7},
  270 +
  271 +};
  272 +
  273 +/* ddr phy trained csr */
  274 +struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
  275 + {0x0200b2,0x0},
  276 + {0x1200b2,0x0},
  277 + {0x2200b2,0x0},
  278 + {0x0200cb,0x0},
  279 + {0x010043,0x0},
  280 + {0x110043,0x0},
  281 + {0x210043,0x0},
  282 + {0x010143,0x0},
  283 + {0x110143,0x0},
  284 + {0x210143,0x0},
  285 + {0x011043,0x0},
  286 + {0x111043,0x0},
  287 + {0x211043,0x0},
  288 + {0x011143,0x0},
  289 + {0x111143,0x0},
  290 + {0x211143,0x0},
  291 + {0x000080,0x0},
  292 + {0x100080,0x0},
  293 + {0x200080,0x0},
  294 + {0x001080,0x0},
  295 + {0x101080,0x0},
  296 + {0x201080,0x0},
  297 + {0x002080,0x0},
  298 + {0x102080,0x0},
  299 + {0x202080,0x0},
  300 + {0x003080,0x0},
  301 + {0x103080,0x0},
  302 + {0x203080,0x0},
  303 + {0x004080,0x0},
  304 + {0x104080,0x0},
  305 + {0x204080,0x0},
  306 + {0x005080,0x0},
  307 + {0x105080,0x0},
  308 + {0x205080,0x0},
  309 + {0x006080,0x0},
  310 + {0x106080,0x0},
  311 + {0x206080,0x0},
  312 + {0x007080,0x0},
  313 + {0x107080,0x0},
  314 + {0x207080,0x0},
  315 + {0x008080,0x0},
  316 + {0x108080,0x0},
  317 + {0x208080,0x0},
  318 + {0x009080,0x0},
  319 + {0x109080,0x0},
  320 + {0x209080,0x0},
  321 + {0x010080,0x0},
  322 + {0x110080,0x0},
  323 + {0x210080,0x0},
  324 + {0x010180,0x0},
  325 + {0x110180,0x0},
  326 + {0x210180,0x0},
  327 + {0x010081,0x0},
  328 + {0x110081,0x0},
  329 + {0x210081,0x0},
  330 + {0x010181,0x0},
  331 + {0x110181,0x0},
  332 + {0x210181,0x0},
  333 + {0x010082,0x0},
  334 + {0x110082,0x0},
  335 + {0x210082,0x0},
  336 + {0x010182,0x0},
  337 + {0x110182,0x0},
  338 + {0x210182,0x0},
  339 + {0x010083,0x0},
  340 + {0x110083,0x0},
  341 + {0x210083,0x0},
  342 + {0x010183,0x0},
  343 + {0x110183,0x0},
  344 + {0x210183,0x0},
  345 + {0x011080,0x0},
  346 + {0x111080,0x0},
  347 + {0x211080,0x0},
  348 + {0x011180,0x0},
  349 + {0x111180,0x0},
  350 + {0x211180,0x0},
  351 + {0x011081,0x0},
  352 + {0x111081,0x0},
  353 + {0x211081,0x0},
  354 + {0x011181,0x0},
  355 + {0x111181,0x0},
  356 + {0x211181,0x0},
  357 + {0x011082,0x0},
  358 + {0x111082,0x0},
  359 + {0x211082,0x0},
  360 + {0x011182,0x0},
  361 + {0x111182,0x0},
  362 + {0x211182,0x0},
  363 + {0x011083,0x0},
  364 + {0x111083,0x0},
  365 + {0x211083,0x0},
  366 + {0x011183,0x0},
  367 + {0x111183,0x0},
  368 + {0x211183,0x0},
  369 + {0x0100d0,0x0},
  370 + {0x1100d0,0x0},
  371 + {0x2100d0,0x0},
  372 + {0x0101d0,0x0},
  373 + {0x1101d0,0x0},
  374 + {0x2101d0,0x0},
  375 + {0x0100d1,0x0},
  376 + {0x1100d1,0x0},
  377 + {0x2100d1,0x0},
  378 + {0x0101d1,0x0},
  379 + {0x1101d1,0x0},
  380 + {0x2101d1,0x0},
  381 + {0x0100d2,0x0},
  382 + {0x1100d2,0x0},
  383 + {0x2100d2,0x0},
  384 + {0x0101d2,0x0},
  385 + {0x1101d2,0x0},
  386 + {0x2101d2,0x0},
  387 + {0x0100d3,0x0},
  388 + {0x1100d3,0x0},
  389 + {0x2100d3,0x0},
  390 + {0x0101d3,0x0},
  391 + {0x1101d3,0x0},
  392 + {0x2101d3,0x0},
  393 + {0x0110d0,0x0},
  394 + {0x1110d0,0x0},
  395 + {0x2110d0,0x0},
  396 + {0x0111d0,0x0},
  397 + {0x1111d0,0x0},
  398 + {0x2111d0,0x0},
  399 + {0x0110d1,0x0},
  400 + {0x1110d1,0x0},
  401 + {0x2110d1,0x0},
  402 + {0x0111d1,0x0},
  403 + {0x1111d1,0x0},
  404 + {0x2111d1,0x0},
  405 + {0x0110d2,0x0},
  406 + {0x1110d2,0x0},
  407 + {0x2110d2,0x0},
  408 + {0x0111d2,0x0},
  409 + {0x1111d2,0x0},
  410 + {0x2111d2,0x0},
  411 + {0x0110d3,0x0},
  412 + {0x1110d3,0x0},
  413 + {0x2110d3,0x0},
  414 + {0x0111d3,0x0},
  415 + {0x1111d3,0x0},
  416 + {0x2111d3,0x0},
  417 + {0x010068,0x0},
  418 + {0x010168,0x0},
  419 + {0x010268,0x0},
  420 + {0x010368,0x0},
  421 + {0x010468,0x0},
  422 + {0x010568,0x0},
  423 + {0x010668,0x0},
  424 + {0x010768,0x0},
  425 + {0x010868,0x0},
  426 + {0x010069,0x0},
  427 + {0x010169,0x0},
  428 + {0x010269,0x0},
  429 + {0x010369,0x0},
  430 + {0x010469,0x0},
  431 + {0x010569,0x0},
  432 + {0x010669,0x0},
  433 + {0x010769,0x0},
  434 + {0x010869,0x0},
  435 + {0x01006a,0x0},
  436 + {0x01016a,0x0},
  437 + {0x01026a,0x0},
  438 + {0x01036a,0x0},
  439 + {0x01046a,0x0},
  440 + {0x01056a,0x0},
  441 + {0x01066a,0x0},
  442 + {0x01076a,0x0},
  443 + {0x01086a,0x0},
  444 + {0x01006b,0x0},
  445 + {0x01016b,0x0},
  446 + {0x01026b,0x0},
  447 + {0x01036b,0x0},
  448 + {0x01046b,0x0},
  449 + {0x01056b,0x0},
  450 + {0x01066b,0x0},
  451 + {0x01076b,0x0},
  452 + {0x01086b,0x0},
  453 + {0x011068,0x0},
  454 + {0x011168,0x0},
  455 + {0x011268,0x0},
  456 + {0x011368,0x0},
  457 + {0x011468,0x0},
  458 + {0x011568,0x0},
  459 + {0x011668,0x0},
  460 + {0x011768,0x0},
  461 + {0x011868,0x0},
  462 + {0x011069,0x0},
  463 + {0x011169,0x0},
  464 + {0x011269,0x0},
  465 + {0x011369,0x0},
  466 + {0x011469,0x0},
  467 + {0x011569,0x0},
  468 + {0x011669,0x0},
  469 + {0x011769,0x0},
  470 + {0x011869,0x0},
  471 + {0x01106a,0x0},
  472 + {0x01116a,0x0},
  473 + {0x01126a,0x0},
  474 + {0x01136a,0x0},
  475 + {0x01146a,0x0},
  476 + {0x01156a,0x0},
  477 + {0x01166a,0x0},
  478 + {0x01176a,0x0},
  479 + {0x01186a,0x0},
  480 + {0x01106b,0x0},
  481 + {0x01116b,0x0},
  482 + {0x01126b,0x0},
  483 + {0x01136b,0x0},
  484 + {0x01146b,0x0},
  485 + {0x01156b,0x0},
  486 + {0x01166b,0x0},
  487 + {0x01176b,0x0},
  488 + {0x01186b,0x0},
  489 + {0x01008c,0x0},
  490 + {0x11008c,0x0},
  491 + {0x21008c,0x0},
  492 + {0x01018c,0x0},
  493 + {0x11018c,0x0},
  494 + {0x21018c,0x0},
  495 + {0x01008d,0x0},
  496 + {0x11008d,0x0},
  497 + {0x21008d,0x0},
  498 + {0x01018d,0x0},
  499 + {0x11018d,0x0},
  500 + {0x21018d,0x0},
  501 + {0x01008e,0x0},
  502 + {0x11008e,0x0},
  503 + {0x21008e,0x0},
  504 + {0x01018e,0x0},
  505 + {0x11018e,0x0},
  506 + {0x21018e,0x0},
  507 + {0x01008f,0x0},
  508 + {0x11008f,0x0},
  509 + {0x21008f,0x0},
  510 + {0x01018f,0x0},
  511 + {0x11018f,0x0},
  512 + {0x21018f,0x0},
  513 + {0x01108c,0x0},
  514 + {0x11108c,0x0},
  515 + {0x21108c,0x0},
  516 + {0x01118c,0x0},
  517 + {0x11118c,0x0},
  518 + {0x21118c,0x0},
  519 + {0x01108d,0x0},
  520 + {0x11108d,0x0},
  521 + {0x21108d,0x0},
  522 + {0x01118d,0x0},
  523 + {0x11118d,0x0},
  524 + {0x21118d,0x0},
  525 + {0x01108e,0x0},
  526 + {0x11108e,0x0},
  527 + {0x21108e,0x0},
  528 + {0x01118e,0x0},
  529 + {0x11118e,0x0},
  530 + {0x21118e,0x0},
  531 + {0x01108f,0x0},
  532 + {0x11108f,0x0},
  533 + {0x21108f,0x0},
  534 + {0x01118f,0x0},
  535 + {0x11118f,0x0},
  536 + {0x21118f,0x0},
  537 + {0x0100c0,0x0},
  538 + {0x1100c0,0x0},
  539 + {0x2100c0,0x0},
  540 + {0x0101c0,0x0},
  541 + {0x1101c0,0x0},
  542 + {0x2101c0,0x0},
  543 + {0x0102c0,0x0},
  544 + {0x1102c0,0x0},
  545 + {0x2102c0,0x0},
  546 + {0x0103c0,0x0},
  547 + {0x1103c0,0x0},
  548 + {0x2103c0,0x0},
  549 + {0x0104c0,0x0},
  550 + {0x1104c0,0x0},
  551 + {0x2104c0,0x0},
  552 + {0x0105c0,0x0},
  553 + {0x1105c0,0x0},
  554 + {0x2105c0,0x0},
  555 + {0x0106c0,0x0},
  556 + {0x1106c0,0x0},
  557 + {0x2106c0,0x0},
  558 + {0x0107c0,0x0},
  559 + {0x1107c0,0x0},
  560 + {0x2107c0,0x0},
  561 + {0x0108c0,0x0},
  562 + {0x1108c0,0x0},
  563 + {0x2108c0,0x0},
  564 + {0x0100c1,0x0},
  565 + {0x1100c1,0x0},
  566 + {0x2100c1,0x0},
  567 + {0x0101c1,0x0},
  568 + {0x1101c1,0x0},
  569 + {0x2101c1,0x0},
  570 + {0x0102c1,0x0},
  571 + {0x1102c1,0x0},
  572 + {0x2102c1,0x0},
  573 + {0x0103c1,0x0},
  574 + {0x1103c1,0x0},
  575 + {0x2103c1,0x0},
  576 + {0x0104c1,0x0},
  577 + {0x1104c1,0x0},
  578 + {0x2104c1,0x0},
  579 + {0x0105c1,0x0},
  580 + {0x1105c1,0x0},
  581 + {0x2105c1,0x0},
  582 + {0x0106c1,0x0},
  583 + {0x1106c1,0x0},
  584 + {0x2106c1,0x0},
  585 + {0x0107c1,0x0},
  586 + {0x1107c1,0x0},
  587 + {0x2107c1,0x0},
  588 + {0x0108c1,0x0},
  589 + {0x1108c1,0x0},
  590 + {0x2108c1,0x0},
  591 + {0x0100c2,0x0},
  592 + {0x1100c2,0x0},
  593 + {0x2100c2,0x0},
  594 + {0x0101c2,0x0},
  595 + {0x1101c2,0x0},
  596 + {0x2101c2,0x0},
  597 + {0x0102c2,0x0},
  598 + {0x1102c2,0x0},
  599 + {0x2102c2,0x0},
  600 + {0x0103c2,0x0},
  601 + {0x1103c2,0x0},
  602 + {0x2103c2,0x0},
  603 + {0x0104c2,0x0},
  604 + {0x1104c2,0x0},
  605 + {0x2104c2,0x0},
  606 + {0x0105c2,0x0},
  607 + {0x1105c2,0x0},
  608 + {0x2105c2,0x0},
  609 + {0x0106c2,0x0},
  610 + {0x1106c2,0x0},
  611 + {0x2106c2,0x0},
  612 + {0x0107c2,0x0},
  613 + {0x1107c2,0x0},
  614 + {0x2107c2,0x0},
  615 + {0x0108c2,0x0},
  616 + {0x1108c2,0x0},
  617 + {0x2108c2,0x0},
  618 + {0x0100c3,0x0},
  619 + {0x1100c3,0x0},
  620 + {0x2100c3,0x0},
  621 + {0x0101c3,0x0},
  622 + {0x1101c3,0x0},
  623 + {0x2101c3,0x0},
  624 + {0x0102c3,0x0},
  625 + {0x1102c3,0x0},
  626 + {0x2102c3,0x0},
  627 + {0x0103c3,0x0},
  628 + {0x1103c3,0x0},
  629 + {0x2103c3,0x0},
  630 + {0x0104c3,0x0},
  631 + {0x1104c3,0x0},
  632 + {0x2104c3,0x0},
  633 + {0x0105c3,0x0},
  634 + {0x1105c3,0x0},
  635 + {0x2105c3,0x0},
  636 + {0x0106c3,0x0},
  637 + {0x1106c3,0x0},
  638 + {0x2106c3,0x0},
  639 + {0x0107c3,0x0},
  640 + {0x1107c3,0x0},
  641 + {0x2107c3,0x0},
  642 + {0x0108c3,0x0},
  643 + {0x1108c3,0x0},
  644 + {0x2108c3,0x0},
  645 + {0x0110c0,0x0},
  646 + {0x1110c0,0x0},
  647 + {0x2110c0,0x0},
  648 + {0x0111c0,0x0},
  649 + {0x1111c0,0x0},
  650 + {0x2111c0,0x0},
  651 + {0x0112c0,0x0},
  652 + {0x1112c0,0x0},
  653 + {0x2112c0,0x0},
  654 + {0x0113c0,0x0},
  655 + {0x1113c0,0x0},
  656 + {0x2113c0,0x0},
  657 + {0x0114c0,0x0},
  658 + {0x1114c0,0x0},
  659 + {0x2114c0,0x0},
  660 + {0x0115c0,0x0},
  661 + {0x1115c0,0x0},
  662 + {0x2115c0,0x0},
  663 + {0x0116c0,0x0},
  664 + {0x1116c0,0x0},
  665 + {0x2116c0,0x0},
  666 + {0x0117c0,0x0},
  667 + {0x1117c0,0x0},
  668 + {0x2117c0,0x0},
  669 + {0x0118c0,0x0},
  670 + {0x1118c0,0x0},
  671 + {0x2118c0,0x0},
  672 + {0x0110c1,0x0},
  673 + {0x1110c1,0x0},
  674 + {0x2110c1,0x0},
  675 + {0x0111c1,0x0},
  676 + {0x1111c1,0x0},
  677 + {0x2111c1,0x0},
  678 + {0x0112c1,0x0},
  679 + {0x1112c1,0x0},
  680 + {0x2112c1,0x0},
  681 + {0x0113c1,0x0},
  682 + {0x1113c1,0x0},
  683 + {0x2113c1,0x0},
  684 + {0x0114c1,0x0},
  685 + {0x1114c1,0x0},
  686 + {0x2114c1,0x0},
  687 + {0x0115c1,0x0},
  688 + {0x1115c1,0x0},
  689 + {0x2115c1,0x0},
  690 + {0x0116c1,0x0},
  691 + {0x1116c1,0x0},
  692 + {0x2116c1,0x0},
  693 + {0x0117c1,0x0},
  694 + {0x1117c1,0x0},
  695 + {0x2117c1,0x0},
  696 + {0x0118c1,0x0},
  697 + {0x1118c1,0x0},
  698 + {0x2118c1,0x0},
  699 + {0x0110c2,0x0},
  700 + {0x1110c2,0x0},
  701 + {0x2110c2,0x0},
  702 + {0x0111c2,0x0},
  703 + {0x1111c2,0x0},
  704 + {0x2111c2,0x0},
  705 + {0x0112c2,0x0},
  706 + {0x1112c2,0x0},
  707 + {0x2112c2,0x0},
  708 + {0x0113c2,0x0},
  709 + {0x1113c2,0x0},
  710 + {0x2113c2,0x0},
  711 + {0x0114c2,0x0},
  712 + {0x1114c2,0x0},
  713 + {0x2114c2,0x0},
  714 + {0x0115c2,0x0},
  715 + {0x1115c2,0x0},
  716 + {0x2115c2,0x0},
  717 + {0x0116c2,0x0},
  718 + {0x1116c2,0x0},
  719 + {0x2116c2,0x0},
  720 + {0x0117c2,0x0},
  721 + {0x1117c2,0x0},
  722 + {0x2117c2,0x0},
  723 + {0x0118c2,0x0},
  724 + {0x1118c2,0x0},
  725 + {0x2118c2,0x0},
  726 + {0x0110c3,0x0},
  727 + {0x1110c3,0x0},
  728 + {0x2110c3,0x0},
  729 + {0x0111c3,0x0},
  730 + {0x1111c3,0x0},
  731 + {0x2111c3,0x0},
  732 + {0x0112c3,0x0},
  733 + {0x1112c3,0x0},
  734 + {0x2112c3,0x0},
  735 + {0x0113c3,0x0},
  736 + {0x1113c3,0x0},
  737 + {0x2113c3,0x0},
  738 + {0x0114c3,0x0},
  739 + {0x1114c3,0x0},
  740 + {0x2114c3,0x0},
  741 + {0x0115c3,0x0},
  742 + {0x1115c3,0x0},
  743 + {0x2115c3,0x0},
  744 + {0x0116c3,0x0},
  745 + {0x1116c3,0x0},
  746 + {0x2116c3,0x0},
  747 + {0x0117c3,0x0},
  748 + {0x1117c3,0x0},
  749 + {0x2117c3,0x0},
  750 + {0x0118c3,0x0},
  751 + {0x1118c3,0x0},
  752 + {0x2118c3,0x0},
  753 + {0x010020,0x0},
  754 + {0x110020,0x0},
  755 + {0x210020,0x0},
  756 + {0x011020,0x0},
  757 + {0x111020,0x0},
  758 + {0x211020,0x0},
  759 + {0x02007d,0x0},
  760 + {0x12007d,0x0},
  761 + {0x22007d,0x0},
  762 + {0x010040,0x0},
  763 + {0x010140,0x0},
  764 + {0x010240,0x0},
  765 + {0x010340,0x0},
  766 + {0x010440,0x0},
  767 + {0x010540,0x0},
  768 + {0x010640,0x0},
  769 + {0x010740,0x0},
  770 + {0x010840,0x0},
  771 + {0x010030,0x0},
  772 + {0x010130,0x0},
  773 + {0x010230,0x0},
  774 + {0x010330,0x0},
  775 + {0x010430,0x0},
  776 + {0x010530,0x0},
  777 + {0x010630,0x0},
  778 + {0x010730,0x0},
  779 + {0x010830,0x0},
  780 + {0x011040,0x0},
  781 + {0x011140,0x0},
  782 + {0x011240,0x0},
  783 + {0x011340,0x0},
  784 + {0x011440,0x0},
  785 + {0x011540,0x0},
  786 + {0x011640,0x0},
  787 + {0x011740,0x0},
  788 + {0x011840,0x0},
  789 + {0x011030,0x0},
  790 + {0x011130,0x0},
  791 + {0x011230,0x0},
  792 + {0x011330,0x0},
  793 + {0x011430,0x0},
  794 + {0x011530,0x0},
  795 + {0x011630,0x0},
  796 + {0x011730,0x0},
  797 + {0x011830,0x0},
  798 +
  799 +};
  800 +
  801 +/* P0 message block paremeter for training firmware */
  802 +struct dram_cfg_param ddr_fsp0_cfg[] = {
  803 + {0x000d0000,0x00000000},
  804 + {0x00020060,0x00000002},
  805 + {0x00054000,0x00000000},
  806 + {0x00054001,0x00000000},
  807 + {0x00054002,0x00000000},
  808 + {0x00054003,0x00000960},
  809 + {0x00054004,0x00000002},
  810 + {0x00054005,0x00000000},
  811 + {0x00054006,0x0000025e},
  812 + {0x00054007,0x00001000},
  813 + {0x00054008,0x00000101},
  814 + {0x00054009,0x00000000},
  815 + {0x0005400a,0x00000000},
  816 + {0x0005400b,0x0000031f},
  817 + {0x0005400c,0x000000c8},
  818 + {0x0005400d,0x00000100},
  819 + {0x0005400e,0x00000000},
  820 + {0x0005400f,0x00000000},
  821 + {0x00054010,0x00000000},
  822 + {0x00054011,0x00000000},
  823 + {0x00054012,0x00000001},
  824 + {0x0005402f,0x00000834},
  825 + {0x00054030,0x00000105},
  826 + {0x00054031,0x00000018},
  827 + {0x00054032,0x00000200},
  828 + {0x00054033,0x00000200},
  829 + {0x00054034,0x00000740},
  830 + {0x00054035,0x00000850},
  831 + {0x00054036,0x00000103},
  832 + {0x00054037,0x00000000},
  833 + {0x00054038,0x00000000},
  834 + {0x00054039,0x00000000},
  835 + {0x0005403a,0x00000000},
  836 + {0x0005403b,0x00000000},
  837 + {0x0005403c,0x00000000},
  838 + {0x0005403d,0x00000000},
  839 + {0x0005403e,0x00000000},
  840 + {0x0005403f,0x00001221},
  841 + {0x000541fc,0x00000100},
  842 + {0x000d0000,0x00000001},
  843 +};
  844 +
  845 +
  846 +/* P1 message block paremeter for training firmware */
  847 +struct dram_cfg_param ddr_fsp1_cfg[] = {
  848 + {0x000d0000,0x00000000},
  849 + {0x00054000,0x00000000},
  850 + {0x00054001,0x00000000},
  851 + {0x00054002,0x00000101},
  852 + {0x00054003,0x00000190},
  853 + {0x00054004,0x00000002},
  854 + {0x00054005,0x00000000},
  855 + {0x00054006,0x0000025e},
  856 + {0x00054007,0x00001000},
  857 + {0x00054008,0x00000101},
  858 + {0x00054009,0x00000000},
  859 + {0x0005400a,0x00000000},
  860 + {0x0005400b,0x0000021f},
  861 + {0x0005400c,0x000000c8},
  862 + {0x0005400d,0x00000100},
  863 + {0x0005400e,0x00000000},
  864 + {0x0005400f,0x00000000},
  865 + {0x00054010,0x00000000},
  866 + {0x00054011,0x00000000},
  867 + {0x00054012,0x00000001},
  868 + {0x0005402f,0x00000000},
  869 + {0x00054030,0x00000105},
  870 + {0x00054031,0x00000000},
  871 + {0x00054032,0x00000000},
  872 + {0x00054033,0x00000200},
  873 + {0x00054034,0x00000740},
  874 + {0x00054035,0x00000050},
  875 + {0x00054036,0x00000103},
  876 + {0x00054037,0x00000000},
  877 + {0x00054038,0x00000000},
  878 + {0x00054039,0x00000000},
  879 + {0x0005403a,0x00000000},
  880 + {0x0005403b,0x00000000},
  881 + {0x0005403c,0x00000000},
  882 + {0x0005403d,0x00000000},
  883 + {0x0005403e,0x00000000},
  884 + {0x0005403f,0x00001221},
  885 + {0x000541fc,0x00000100},
  886 + {0x000d0000,0x00000001},
  887 +};
  888 +
  889 +
  890 +/* P2 message block paremeter for training firmware */
  891 +struct dram_cfg_param ddr_fsp2_cfg[] = {
  892 + {0x000d0000,0x00000000},
  893 + {0x00054000,0x00000000},
  894 + {0x00054001,0x00000000},
  895 + {0x00054002,0x00000102},
  896 + {0x00054003,0x00000064},
  897 + {0x00054004,0x00000002},
  898 + {0x00054005,0x00000000},
  899 + {0x00054006,0x0000025e},
  900 + {0x00054007,0x00001000},
  901 + {0x00054008,0x00000101},
  902 + {0x00054009,0x00000000},
  903 + {0x0005400a,0x00000000},
  904 + {0x0005400b,0x0000021f},
  905 + {0x0005400c,0x000000c8},
  906 + {0x0005400d,0x00000100},
  907 + {0x0005400e,0x00000000},
  908 + {0x0005400f,0x00000000},
  909 + {0x00054010,0x00000000},
  910 + {0x00054011,0x00000000},
  911 + {0x00054012,0x00000001},
  912 + {0x0005402f,0x00000000},
  913 + {0x00054030,0x00000105},
  914 + {0x00054031,0x00000000},
  915 + {0x00054032,0x00000000},
  916 + {0x00054033,0x00000200},
  917 + {0x00054034,0x00000740},
  918 + {0x00054035,0x00000050},
  919 + {0x00054036,0x00000103},
  920 + {0x00054037,0x00000000},
  921 + {0x00054038,0x00000000},
  922 + {0x00054039,0x00000000},
  923 + {0x0005403a,0x00000000},
  924 + {0x0005403b,0x00000000},
  925 + {0x0005403c,0x00000000},
  926 + {0x0005403d,0x00000000},
  927 + {0x0005403e,0x00000000},
  928 + {0x0005403f,0x00001221},
  929 + {0x000541fc,0x00000100},
  930 + {0x000d0000,0x00000001},
  931 +};
  932 +
  933 +/* P0 2D message block paremeter for training firmware */
  934 +struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
  935 + {0x000d0000,0x00000000},
  936 + {0x00054000,0x00000000},
  937 + {0x00054001,0x00000000},
  938 + {0x00054002,0x00000000},
  939 + {0x00054003,0x00000960},
  940 + {0x00054004,0x00000002},
  941 + {0x00054005,0x00000000},
  942 + {0x00054006,0x0000025e},
  943 + {0x00054007,0x00001000},
  944 + {0x00054008,0x00000101},
  945 + {0x00054009,0x00000000},
  946 + {0x0005400a,0x00000000},
  947 + {0x0005400b,0x00000061},
  948 + {0x0005400c,0x000000c8},
  949 + {0x0005400d,0x00000100},
  950 + {0x0005400e,0x00001f7f},
  951 + {0x0005400f,0x00000000},
  952 + {0x00054010,0x00000000},
  953 + {0x00054011,0x00000000},
  954 + {0x00054012,0x00000001},
  955 + {0x0005402f,0x00000834},
  956 + {0x00054030,0x00000105},
  957 + {0x00054031,0x00000018},
  958 + {0x00054032,0x00000200},
  959 + {0x00054033,0x00000200},
  960 + {0x00054034,0x00000740},
  961 + {0x00054035,0x00000850},
  962 + {0x00054036,0x00000103},
  963 + {0x00054037,0x00000000},
  964 + {0x00054038,0x00000000},
  965 + {0x00054039,0x00000000},
  966 + {0x0005403a,0x00000000},
  967 + {0x0005403b,0x00000000},
  968 + {0x0005403c,0x00000000},
  969 + {0x0005403d,0x00000000},
  970 + {0x0005403e,0x00000000},
  971 + {0x0005403f,0x00001221},
  972 + {0x000541fc,0x00000100},
  973 + {0x000d0000,0x00000001},
  974 +};
  975 +
  976 +/* DRAM PHY init engine image */
  977 +struct dram_cfg_param ddr_phy_pie[] = {
  978 + {0xd0000,0x0},
  979 + {0x90000,0x10},
  980 + {0x90001,0x400},
  981 + {0x90002,0x10e},
  982 + {0x90003,0x0},
  983 + {0x90004,0x0},
  984 + {0x90005,0x8},
  985 + {0x90029,0xb},
  986 + {0x9002a,0x480},
  987 + {0x9002b,0x109},
  988 + {0x9002c,0x8},
  989 + {0x9002d,0x448},
  990 + {0x9002e,0x139},
  991 + {0x9002f,0x8},
  992 + {0x90030,0x478},
  993 + {0x90031,0x109},
  994 + {0x90032,0x2},
  995 + {0x90033,0x10},
  996 + {0x90034,0x139},
  997 + {0x90035,0xb},
  998 + {0x90036,0x7c0},
  999 + {0x90037,0x139},
  1000 + {0x90038,0x44},
  1001 + {0x90039,0x633},
  1002 + {0x9003a,0x159},
  1003 + {0x9003b,0x14f},
  1004 + {0x9003c,0x630},
  1005 + {0x9003d,0x159},
  1006 + {0x9003e,0x47},
  1007 + {0x9003f,0x633},
  1008 + {0x90040,0x149},
  1009 + {0x90041,0x4f},
  1010 + {0x90042,0x633},
  1011 + {0x90043,0x179},
  1012 + {0x90044,0x8},
  1013 + {0x90045,0xe0},
  1014 + {0x90046,0x109},
  1015 + {0x90047,0x0},
  1016 + {0x90048,0x7c8},
  1017 + {0x90049,0x109},
  1018 + {0x9004a,0x0},
  1019 + {0x9004b,0x1},
  1020 + {0x9004c,0x8},
  1021 + {0x9004d,0x0},
  1022 + {0x9004e,0x45a},
  1023 + {0x9004f,0x9},
  1024 + {0x90050,0x0},
  1025 + {0x90051,0x448},
  1026 + {0x90052,0x109},
  1027 + {0x90053,0x40},
  1028 + {0x90054,0x633},
  1029 + {0x90055,0x179},
  1030 + {0x90056,0x1},
  1031 + {0x90057,0x618},
  1032 + {0x90058,0x109},
  1033 + {0x90059,0x40c0},
  1034 + {0x9005a,0x633},
  1035 + {0x9005b,0x149},
  1036 + {0x9005c,0x8},
  1037 + {0x9005d,0x4},
  1038 + {0x9005e,0x48},
  1039 + {0x9005f,0x4040},
  1040 + {0x90060,0x633},
  1041 + {0x90061,0x149},
  1042 + {0x90062,0x0},
  1043 + {0x90063,0x4},
  1044 + {0x90064,0x48},
  1045 + {0x90065,0x40},
  1046 + {0x90066,0x633},
  1047 + {0x90067,0x149},
  1048 + {0x90068,0x10},
  1049 + {0x90069,0x4},
  1050 + {0x9006a,0x18},
  1051 + {0x9006b,0x0},
  1052 + {0x9006c,0x4},
  1053 + {0x9006d,0x78},
  1054 + {0x9006e,0x549},
  1055 + {0x9006f,0x633},
  1056 + {0x90070,0x159},
  1057 + {0x90071,0xd49},
  1058 + {0x90072,0x633},
  1059 + {0x90073,0x159},
  1060 + {0x90074,0x94a},
  1061 + {0x90075,0x633},
  1062 + {0x90076,0x159},
  1063 + {0x90077,0x441},
  1064 + {0x90078,0x633},
  1065 + {0x90079,0x149},
  1066 + {0x9007a,0x42},
  1067 + {0x9007b,0x633},
  1068 + {0x9007c,0x149},
  1069 + {0x9007d,0x1},
  1070 + {0x9007e,0x633},
  1071 + {0x9007f,0x149},
  1072 + {0x90080,0x0},
  1073 + {0x90081,0xe0},
  1074 + {0x90082,0x109},
  1075 + {0x90083,0xa},
  1076 + {0x90084,0x10},
  1077 + {0x90085,0x109},
  1078 + {0x90086,0x9},
  1079 + {0x90087,0x3c0},
  1080 + {0x90088,0x149},
  1081 + {0x90089,0x9},
  1082 + {0x9008a,0x3c0},
  1083 + {0x9008b,0x159},
  1084 + {0x9008c,0x18},
  1085 + {0x9008d,0x10},
  1086 + {0x9008e,0x109},
  1087 + {0x9008f,0x0},
  1088 + {0x90090,0x3c0},
  1089 + {0x90091,0x109},
  1090 + {0x90092,0x18},
  1091 + {0x90093,0x4},
  1092 + {0x90094,0x48},
  1093 + {0x90095,0x18},
  1094 + {0x90096,0x4},
  1095 + {0x90097,0x58},
  1096 + {0x90098,0xb},
  1097 + {0x90099,0x10},
  1098 + {0x9009a,0x109},
  1099 + {0x9009b,0x1},
  1100 + {0x9009c,0x10},
  1101 + {0x9009d,0x109},
  1102 + {0x9009e,0x5},
  1103 + {0x9009f,0x7c0},
  1104 + {0x900a0,0x109},
  1105 + {0x900a1,0x0},
  1106 + {0x900a2,0x8140},
  1107 + {0x900a3,0x10c},
  1108 + {0x900a4,0x10},
  1109 + {0x900a5,0x8138},
  1110 + {0x900a6,0x10c},
  1111 + {0x900a7,0x8},
  1112 + {0x900a8,0x7c8},
  1113 + {0x900a9,0x101},
  1114 + {0x900aa,0x8},
  1115 + {0x900ab,0x448},
  1116 + {0x900ac,0x109},
  1117 + {0x900ad,0xf},
  1118 + {0x900ae,0x7c0},
  1119 + {0x900af,0x109},
  1120 + {0x900b0,0x47},
  1121 + {0x900b1,0x630},
  1122 + {0x900b2,0x109},
  1123 + {0x900b3,0x8},
  1124 + {0x900b4,0x618},
  1125 + {0x900b5,0x109},
  1126 + {0x900b6,0x8},
  1127 + {0x900b7,0xe0},
  1128 + {0x900b8,0x109},
  1129 + {0x900b9,0x0},
  1130 + {0x900ba,0x7c8},
  1131 + {0x900bb,0x109},
  1132 + {0x900bc,0x8},
  1133 + {0x900bd,0x8140},
  1134 + {0x900be,0x10c},
  1135 + {0x900bf,0x0},
  1136 + {0x900c0,0x1},
  1137 + {0x900c1,0x8},
  1138 + {0x900c2,0x8},
  1139 + {0x900c3,0x4},
  1140 + {0x900c4,0x8},
  1141 + {0x900c5,0x8},
  1142 + {0x900c6,0x7c8},
  1143 + {0x900c7,0x101},
  1144 + {0x90006,0x0},
  1145 + {0x90007,0x0},
  1146 + {0x90008,0x8},
  1147 + {0x90009,0x0},
  1148 + {0x9000a,0x0},
  1149 + {0x9000b,0x0},
  1150 + {0xd00e7,0x400},
  1151 + {0x90017,0x0},
  1152 + {0x90026,0x2b},
  1153 + {0x2000b,0x4b},
  1154 + {0x2000c,0x96},
  1155 + {0x2000d,0x5dc},
  1156 + {0x2000e,0x2c},
  1157 + {0x12000b,0xc},
  1158 + {0x12000c,0x16},
  1159 + {0x12000d,0xfa},
  1160 + {0x12000e,0x10},
  1161 + {0x22000b,0x3},
  1162 + {0x22000c,0x3},
  1163 + {0x22000d,0x3e},
  1164 + {0x22000e,0x10},
  1165 + {0x9000c,0x0},
  1166 + {0x9000d,0x173},
  1167 + {0x9000e,0x60},
  1168 + {0x9000f,0x6110},
  1169 + {0x90010,0x2152},
  1170 + {0x90011,0xdfbd},
  1171 + {0x90012,0xffff},
  1172 + {0x90013,0x6152},
  1173 + {0x20089,0x1},
  1174 + {0x20088,0x19},
  1175 + {0xc0080,0x0},
  1176 + {0xd0000,0x1},
  1177 +};
  1178 +
  1179 +struct dram_fsp_msg ddr_dram_fsp_msg[] = {
  1180 + {
  1181 + /* P0 2400mts 1D */
  1182 + .drate = 2400,
  1183 + .fw_type = FW_1D_IMAGE,
  1184 + .fsp_cfg = ddr_fsp0_cfg,
  1185 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
  1186 + },
  1187 + {
  1188 + /* P1 400mts 1D */
  1189 + .drate = 400,
  1190 + .fw_type = FW_1D_IMAGE,
  1191 + .fsp_cfg = ddr_fsp1_cfg,
  1192 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
  1193 + },
  1194 + {
  1195 + /* P2 100mts 1D */
  1196 + .drate = 100,
  1197 + .fw_type = FW_1D_IMAGE,
  1198 + .fsp_cfg = ddr_fsp2_cfg,
  1199 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
  1200 + },
  1201 + {
  1202 + /* P0 2400mts 2D */
  1203 + .drate = 2400,
  1204 + .fw_type = FW_2D_IMAGE,
  1205 + .fsp_cfg = ddr_fsp0_2d_cfg,
  1206 + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
  1207 + },
  1208 +};
  1209 +
  1210 +/* ddr timing config params */
  1211 +struct dram_timing_info dram_timing = {
  1212 + .ddrc_cfg = ddr_ddrc_cfg,
  1213 + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
  1214 + .ddrphy_cfg = ddr_ddrphy_cfg,
  1215 + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
  1216 + .fsp_msg = ddr_dram_fsp_msg,
  1217 + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
  1218 + .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
  1219 + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
  1220 + .ddrphy_pie = ddr_phy_pie,
  1221 + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
  1222 + .fsp_table = { 2400, 400, 100,},
  1223 +};
board/freescale/imx8mn_evk/imx8mn_evk.c
Diff comments   View file @ 7081a12
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <errno.h>
  10 +#include <asm/io.h>
  11 +#include <miiphy.h>
  12 +#include <netdev.h>
  13 +#include <asm/mach-imx/iomux-v3.h>
  14 +#include <asm-generic/gpio.h>
  15 +#include <fsl_esdhc.h>
  16 +#include <mmc.h>
  17 +#include <asm/arch/imx8mn_pins.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/mach-imx/gpio.h>
  20 +#include <asm/mach-imx/mxc_i2c.h>
  21 +#include <asm/arch/clock.h>
  22 +#include <spl.h>
  23 +#include <asm/mach-imx/dma.h>
  24 +#include <power/pmic.h>
  25 +#include <power/bd71837.h>
  26 +#include "../common/tcpc.h"
  27 +#include <usb.h>
  28 +#include <sec_mipi_dsim.h>
  29 +#include <imx_mipi_dsi_bridge.h>
  30 +#include <mipi_dsi_panel.h>
  31 +#include <asm/mach-imx/video.h>
  32 +
  33 +DECLARE_GLOBAL_DATA_PTR;
  34 +
  35 +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  36 +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  37 +
  38 +static iomux_v3_cfg_t const uart_pads[] = {
  39 + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  40 + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  41 +};
  42 +
  43 +static iomux_v3_cfg_t const wdog_pads[] = {
  44 + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  45 +};
  46 +
  47 +#ifdef CONFIG_FSL_FSPI
  48 +int board_qspi_init(void)
  49 +{
  50 + set_clk_qspi();
  51 +
  52 + return 0;
  53 +}
  54 +#endif
  55 +
  56 +#ifdef CONFIG_NAND_MXS
  57 +#ifdef CONFIG_SPL_BUILD
  58 +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
  59 +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
  60 +static iomux_v3_cfg_t const gpmi_pads[] = {
  61 + IMX8MN_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  62 + IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  63 + IMX8MN_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  64 + IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  65 + IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  66 + IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67 + IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68 + IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69 + IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70 + IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71 + IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72 + IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73 + IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  74 + IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75 + IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76 +};
  77 +#endif
  78 +
  79 +static void setup_gpmi_nand(void)
  80 +{
  81 +#ifdef CONFIG_SPL_BUILD
  82 + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  83 +#endif
  84 +
  85 + init_nand_clk();
  86 +}
  87 +#endif
  88 +
  89 +int board_early_init_f(void)
  90 +{
  91 + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  92 +
  93 + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  94 +
  95 + set_wdog_reset(wdog);
  96 +
  97 + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  98 +
  99 + init_uart_clk(1);
  100 +
  101 +#ifdef CONFIG_NAND_MXS
  102 + setup_gpmi_nand(); /* SPL will call the board_early_init_f */
  103 +#endif
  104 +
  105 + return 0;
  106 +}
  107 +
  108 +int dram_init(void)
  109 +{
  110 + /* rom_pointer[1] contains the size of TEE occupies */
  111 + if (rom_pointer[1])
  112 + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  113 + else
  114 + gd->ram_size = PHYS_SDRAM_SIZE;
  115 +
  116 + return 0;
  117 +}
  118 +
  119 +#ifdef CONFIG_FEC_MXC
  120 +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
  121 +static iomux_v3_cfg_t const fec1_rst_pads[] = {
  122 + IMX8MN_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  123 +};
  124 +
  125 +static void setup_iomux_fec(void)
  126 +{
  127 + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  128 + ARRAY_SIZE(fec1_rst_pads));
  129 +
  130 + gpio_request(FEC_RST_PAD, "fec1_rst");
  131 + gpio_direction_output(FEC_RST_PAD, 0);
  132 + udelay(500);
  133 + gpio_direction_output(FEC_RST_PAD, 1);
  134 +}
  135 +
  136 +static int setup_fec(void)
  137 +{
  138 + struct iomuxc_gpr_base_regs *gpr =
  139 + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  140 +
  141 + setup_iomux_fec();
  142 +
  143 + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  144 + clrsetbits_le32(&gpr->gpr[1],
  145 + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
  146 + return set_clk_enet(ENET_125MHZ);
  147 +}
  148 +
  149 +int board_phy_config(struct phy_device *phydev)
  150 +{
  151 + /* enable rgmii rxc skew and phy mode select to RGMII copper */
  152 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  153 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  154 +
  155 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  156 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  157 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  158 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  159 +
  160 + if (phydev->drv->config)
  161 + phydev->drv->config(phydev);
  162 + return 0;
  163 +}
  164 +#endif
  165 +
  166 +#ifdef CONFIG_USB_TCPC
  167 +struct tcpc_port port1;
  168 +struct tcpc_port port2;
  169 +
  170 +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
  171 +{
  172 + struct udevice *bus;
  173 + struct udevice *i2c_dev = NULL;
  174 + int ret;
  175 + uint8_t valb;
  176 +
  177 + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
  178 + if (ret) {
  179 + printf("%s: Can't find bus\n", __func__);
  180 + return -EINVAL;
  181 + }
  182 +
  183 + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
  184 + if (ret) {
  185 + printf("%s: Can't find device id=0x%x\n",
  186 + __func__, addr);
  187 + return -ENODEV;
  188 + }
  189 +
  190 + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
  191 + if (ret) {
  192 + printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
  193 + return -EIO;
  194 + }
  195 + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
  196 + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
  197 + if (ret) {
  198 + printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
  199 + return -EIO;
  200 + }
  201 +
  202 + /* Set OVP threshold to 23V */
  203 + valb = 0x6;
  204 + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
  205 + if (ret) {
  206 + printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
  207 + return -EIO;
  208 + }
  209 +
  210 + return 0;
  211 +}
  212 +
  213 +int pd_switch_snk_enable(struct tcpc_port *port)
  214 +{
  215 + if (port == &port1) {
  216 + debug("Setup pd switch on port 1\n");
  217 + return setup_pd_switch(1, 0x72);
  218 + } else if (port == &port2) {
  219 + debug("Setup pd switch on port 2\n");
  220 + return setup_pd_switch(1, 0x73);
  221 + } else
  222 + return -EINVAL;
  223 +}
  224 +
  225 +struct tcpc_port_config port1_config = {
  226 + .i2c_bus = 1, /*i2c2*/
  227 + .addr = 0x50,
  228 + .port_type = TYPEC_PORT_UFP,
  229 + .max_snk_mv = 5000,
  230 + .max_snk_ma = 3000,
  231 + .max_snk_mw = 40000,
  232 + .op_snk_mv = 9000,
  233 + .switch_setup_func = &pd_switch_snk_enable,
  234 +};
  235 +
  236 +struct tcpc_port_config port2_config = {
  237 + .i2c_bus = 1, /*i2c2*/
  238 + .addr = 0x52,
  239 + .port_type = TYPEC_PORT_UFP,
  240 + .max_snk_mv = 5000,
  241 + .max_snk_ma = 3000,
  242 + .max_snk_mw = 40000,
  243 + .op_snk_mv = 9000,
  244 + .switch_setup_func = &pd_switch_snk_enable,
  245 +};
  246 +
  247 +static int setup_typec(void)
  248 +{
  249 + int ret;
  250 +
  251 + debug("tcpc_init port 2\n");
  252 + ret = tcpc_init(&port2, port2_config, NULL);
  253 + if (ret) {
  254 + printf("%s: tcpc port2 init failed, err=%d\n",
  255 + __func__, ret);
  256 + } else if (tcpc_pd_sink_check_charging(&port2)) {
  257 + /* Disable PD for USB1, since USB2 has priority */
  258 + port1_config.disable_pd = true;
  259 + printf("Power supply on USB2\n");
  260 + }
  261 +
  262 + debug("tcpc_init port 1\n");
  263 + ret = tcpc_init(&port1, port1_config, NULL);
  264 + if (ret) {
  265 + printf("%s: tcpc port1 init failed, err=%d\n",
  266 + __func__, ret);
  267 + } else {
  268 + if (!port1_config.disable_pd)
  269 + printf("Power supply on USB1\n");
  270 + return ret;
  271 + }
  272 +
  273 + return ret;
  274 +}
  275 +
  276 +int board_usb_init(int index, enum usb_init_type init)
  277 +{
  278 + int ret = 0;
  279 + struct tcpc_port *port_ptr;
  280 +
  281 + debug("board_usb_init %d, type %d\n", index, init);
  282 +
  283 + if (index == 0)
  284 + port_ptr = &port1;
  285 + else
  286 + port_ptr = &port2;
  287 +
  288 + imx8m_usb_power(index, true);
  289 +
  290 + if (init == USB_INIT_HOST)
  291 + tcpc_setup_dfp_mode(port_ptr);
  292 + else
  293 + tcpc_setup_ufp_mode(port_ptr);
  294 +
  295 + return ret;
  296 +}
  297 +
  298 +int board_usb_cleanup(int index, enum usb_init_type init)
  299 +{
  300 + int ret = 0;
  301 +
  302 + debug("board_usb_cleanup %d, type %d\n", index, init);
  303 +
  304 + if (init == USB_INIT_HOST) {
  305 + if (index == 0)
  306 + ret = tcpc_disable_src_vbus(&port1);
  307 + else
  308 + ret = tcpc_disable_src_vbus(&port2);
  309 + }
  310 +
  311 + imx8m_usb_power(index, false);
  312 + return ret;
  313 +}
  314 +
  315 +int board_ehci_usb_phy_mode(struct udevice *dev)
  316 +{
  317 + int ret = 0;
  318 + enum typec_cc_polarity pol;
  319 + enum typec_cc_state state;
  320 + struct tcpc_port *port_ptr;
  321 +
  322 + if (dev->seq == 0)
  323 + port_ptr = &port1;
  324 + else
  325 + port_ptr = &port2;
  326 +
  327 + tcpc_setup_ufp_mode(port_ptr);
  328 +
  329 + ret = tcpc_get_cc_status(port_ptr, &pol, &state);
  330 + if (!ret) {
  331 + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
  332 + return USB_INIT_HOST;
  333 + }
  334 +
  335 + return USB_INIT_DEVICE;
  336 +}
  337 +
  338 +#endif
  339 +
  340 +int board_init(void)
  341 +{
  342 +#ifdef CONFIG_USB_TCPC
  343 + setup_typec();
  344 +#endif
  345 +
  346 +#ifdef CONFIG_FEC_MXC
  347 + setup_fec();
  348 +#endif
  349 +
  350 +#ifdef CONFIG_FSL_FSPI
  351 + board_qspi_init();
  352 +#endif
  353 +
  354 + return 0;
  355 +}
  356 +
  357 +#ifdef CONFIG_VIDEO_MXS
  358 +
  359 +#define ADV7535_MAIN 0x3d
  360 +#define ADV7535_DSI_CEC 0x3c
  361 +
  362 +static const struct sec_mipi_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
  363 + .version = 0x1060200,
  364 + .max_data_lanes = 4,
  365 + .max_data_rate = 1500000000ULL,
  366 + .reg_base = MIPI_DSI_BASE_ADDR,
  367 + .gpr_base = CSI_BASE_ADDR + 0x8000,
  368 +};
  369 +
  370 +static int adv7535_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data)
  371 +{
  372 + uint8_t valb;
  373 + int err;
  374 +
  375 + if (mask != 0xff) {
  376 + err = dm_i2c_read(dev, addr, &valb, 1);
  377 + if (err)
  378 + return err;
  379 +
  380 + valb &= ~mask;
  381 + valb |= data;
  382 + } else {
  383 + valb = data;
  384 + }
  385 +
  386 + err = dm_i2c_write(dev, addr, &valb, 1);
  387 + return err;
  388 +}
  389 +
  390 +static int adv7535_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data)
  391 +{
  392 + uint8_t valb;
  393 + int err;
  394 +
  395 + err = dm_i2c_read(dev, addr, &valb, 1);
  396 + if (err)
  397 + return err;
  398 +
  399 + *data = (int)valb;
  400 + return 0;
  401 +}
  402 +
  403 +static void adv7535_init(void)
  404 +{
  405 + struct udevice *bus, *main_dev, *cec_dev;
  406 + int i2c_bus = 1;
  407 + int ret;
  408 + uint8_t val;
  409 +
  410 + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
  411 + if (ret) {
  412 + printf("%s: No bus %d\n", __func__, i2c_bus);
  413 + return;
  414 + }
  415 +
  416 + ret = dm_i2c_probe(bus, ADV7535_MAIN, 0, &main_dev);
  417 + if (ret) {
  418 + printf("%s: Can't find device id=0x%x, on bus %d\n",
  419 + __func__, ADV7535_MAIN, i2c_bus);
  420 + return;
  421 + }
  422 +
  423 + ret = dm_i2c_probe(bus, ADV7535_DSI_CEC, 0, &cec_dev);
  424 + if (ret) {
  425 + printf("%s: Can't find device id=0x%x, on bus %d\n",
  426 + __func__, ADV7535_MAIN, i2c_bus);
  427 + return;
  428 + }
  429 +
  430 + adv7535_i2c_reg_read(main_dev, 0x00, &val);
  431 + debug("Chip revision: 0x%x (expected: 0x14)\n", val);
  432 + adv7535_i2c_reg_read(cec_dev, 0x00, &val);
  433 + debug("Chip ID MSB: 0x%x (expected: 0x75)\n", val);
  434 + adv7535_i2c_reg_read(cec_dev, 0x01, &val);
  435 + debug("Chip ID LSB: 0x%x (expected: 0x33)\n", val);
  436 +
  437 + /* Power */
  438 + adv7535_i2c_reg_write(main_dev, 0x41, 0xff, 0x10);
  439 + /* Initialisation (Fixed) Registers */
  440 + adv7535_i2c_reg_write(main_dev, 0x16, 0xff, 0x20);
  441 + adv7535_i2c_reg_write(main_dev, 0x9A, 0xff, 0xE0);
  442 + adv7535_i2c_reg_write(main_dev, 0xBA, 0xff, 0x70);
  443 + adv7535_i2c_reg_write(main_dev, 0xDE, 0xff, 0x82);
  444 + adv7535_i2c_reg_write(main_dev, 0xE4, 0xff, 0x40);
  445 + adv7535_i2c_reg_write(main_dev, 0xE5, 0xff, 0x80);
  446 + adv7535_i2c_reg_write(cec_dev, 0x15, 0xff, 0xD0);
  447 + adv7535_i2c_reg_write(cec_dev, 0x17, 0xff, 0xD0);
  448 + adv7535_i2c_reg_write(cec_dev, 0x24, 0xff, 0x20);
  449 + adv7535_i2c_reg_write(cec_dev, 0x57, 0xff, 0x11);
  450 + /* 4 x DSI Lanes */
  451 + adv7535_i2c_reg_write(cec_dev, 0x1C, 0xff, 0x40);
  452 +
  453 + /* DSI Pixel Clock Divider */
  454 + adv7535_i2c_reg_write(cec_dev, 0x16, 0xff, 0x18);
  455 +
  456 + /* Enable Internal Timing Generator */
  457 + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
  458 + /* 1920 x 1080p 60Hz */
  459 + adv7535_i2c_reg_write(cec_dev, 0x28, 0xff, 0x89); /* total width */
  460 + adv7535_i2c_reg_write(cec_dev, 0x29, 0xff, 0x80); /* total width */
  461 + adv7535_i2c_reg_write(cec_dev, 0x2A, 0xff, 0x02); /* hsync */
  462 + adv7535_i2c_reg_write(cec_dev, 0x2B, 0xff, 0xC0); /* hsync */
  463 + adv7535_i2c_reg_write(cec_dev, 0x2C, 0xff, 0x05); /* hfp */
  464 + adv7535_i2c_reg_write(cec_dev, 0x2D, 0xff, 0x80); /* hfp */
  465 + adv7535_i2c_reg_write(cec_dev, 0x2E, 0xff, 0x09); /* hbp */
  466 + adv7535_i2c_reg_write(cec_dev, 0x2F, 0xff, 0x40); /* hbp */
  467 +
  468 + adv7535_i2c_reg_write(cec_dev, 0x30, 0xff, 0x46); /* total height */
  469 + adv7535_i2c_reg_write(cec_dev, 0x31, 0xff, 0x50); /* total height */
  470 + adv7535_i2c_reg_write(cec_dev, 0x32, 0xff, 0x00); /* vsync */
  471 + adv7535_i2c_reg_write(cec_dev, 0x33, 0xff, 0x50); /* vsync */
  472 + adv7535_i2c_reg_write(cec_dev, 0x34, 0xff, 0x00); /* vfp */
  473 + adv7535_i2c_reg_write(cec_dev, 0x35, 0xff, 0x40); /* vfp */
  474 + adv7535_i2c_reg_write(cec_dev, 0x36, 0xff, 0x02); /* vbp */
  475 + adv7535_i2c_reg_write(cec_dev, 0x37, 0xff, 0x40); /* vbp */
  476 +
  477 + /* Reset Internal Timing Generator */
  478 + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
  479 + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0x8B);
  480 + adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
  481 +
  482 + /* HDMI Output */
  483 + adv7535_i2c_reg_write(main_dev, 0xAF, 0xff, 0x16);
  484 + /* AVI Infoframe - RGB - 16-9 Aspect Ratio */
  485 + adv7535_i2c_reg_write(main_dev, 0x55, 0xff, 0x02);
  486 + adv7535_i2c_reg_write(main_dev, 0x56, 0xff, 0x0);
  487 +
  488 + /* GC Packet Enable */
  489 + adv7535_i2c_reg_write(main_dev, 0x40, 0xff, 0x0);
  490 + /* GC Colour Depth - 24 Bit */
  491 + adv7535_i2c_reg_write(main_dev, 0x4C, 0xff, 0x0);
  492 + /* Down Dither Output Colour Depth - 8 Bit (default) */
  493 + adv7535_i2c_reg_write(main_dev, 0x49, 0xff, 0x00);
  494 +
  495 + /* set low refresh 1080p30 */
  496 + adv7535_i2c_reg_write(main_dev, 0x4A, 0xff, 0x80); /*should be 0x80 for 1080p60 and 0x8c for 1080p30*/
  497 +
  498 + /* HDMI Output Enable */
  499 + adv7535_i2c_reg_write(cec_dev, 0xbe, 0xff, 0x3c);
  500 + adv7535_i2c_reg_write(cec_dev, 0x03, 0xff, 0x89);
  501 +}
  502 +
  503 +#define DISPLAY_MIX_SFT_RSTN_CSR 0x00
  504 +#define DISPLAY_MIX_CLK_EN_CSR 0x04
  505 +
  506 + /* 'DISP_MIX_SFT_RSTN_CSR' bit fields */
  507 +#define BUS_RSTN_BLK_SYNC_SFT_EN BIT(8)
  508 +#define LCDIF_APB_CLK_RSTN BIT(5)
  509 +#define LCDIF_PIXEL_CLK_RSTN BIT(4)
  510 +
  511 + /* 'DISP_MIX_CLK_EN_CSR' bit fields */
  512 +#define BUS_BLK_CLK_SFT_EN BIT(8)
  513 +#define LCDIF_PIXEL_CLK_SFT_EN BIT(5)
  514 +#define LCDIF_APB_CLK_SFT_EN BIT(4)
  515 +
  516 +void disp_mix_bus_rstn_reset(ulong gpr_base, bool reset)
  517 +{
  518 + if (!reset)
  519 + /* release reset */
  520 + setbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN | LCDIF_APB_CLK_RSTN |LCDIF_PIXEL_CLK_RSTN);
  521 + else
  522 + /* hold reset */
  523 + clrbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN | LCDIF_APB_CLK_RSTN |LCDIF_PIXEL_CLK_RSTN);
  524 +}
  525 +
  526 +void disp_mix_lcdif_clks_enable(ulong gpr_base, bool enable)
  527 +{
  528 + if (enable)
  529 + /* enable lcdif clks */
  530 + setbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, BUS_BLK_CLK_SFT_EN | LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
  531 + else
  532 + /* disable lcdif clks */
  533 + clrbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, BUS_BLK_CLK_SFT_EN | LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
  534 +}
  535 +
  536 +struct mipi_dsi_client_dev adv7535_dev = {
  537 + .channel = 0,
  538 + .lanes = 4,
  539 + .format = MIPI_DSI_FMT_RGB888,
  540 + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  541 + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
  542 + .name = "ADV7535",
  543 +};
  544 +
  545 +struct mipi_dsi_client_dev rm67191_dev = {
  546 + .channel = 0,
  547 + .lanes = 4,
  548 + .format = MIPI_DSI_FMT_RGB888,
  549 + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  550 + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
  551 +};
  552 +
  553 +#define FSL_SIP_GPC 0xC2000000
  554 +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3
  555 +#define DISPMIX 9
  556 +#define MIPI 10
  557 +
  558 +void do_enable_mipi2hdmi(struct display_info_t const *dev)
  559 +{
  560 + gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
  561 + gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
  562 +
  563 + /* ADV7353 initialization */
  564 + adv7535_init();
  565 +
  566 + /* enable the dispmix & mipi phy power domain */
  567 + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
  568 + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
  569 +
  570 + /* Put lcdif out of reset */
  571 + disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
  572 + disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
  573 +
  574 + /* Setup mipi dsim */
  575 + sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
  576 + imx_mipi_dsi_bridge_attach(&adv7535_dev); /* attach adv7535 device */
  577 +}
  578 +
  579 +void do_enable_mipi_led(struct display_info_t const *dev)
  580 +{
  581 + gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
  582 + gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
  583 + mdelay(100);
  584 + gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
  585 +
  586 + /* enable the dispmix & mipi phy power domain */
  587 + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
  588 + call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
  589 +
  590 + /* Put lcdif out of reset */
  591 + disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
  592 + disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
  593 +
  594 + /* Setup mipi dsim */
  595 + sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
  596 +
  597 + rm67191_init();
  598 + rm67191_dev.name = displays[1].mode.name;
  599 + imx_mipi_dsi_bridge_attach(&rm67191_dev); /* attach rm67191 device */
  600 +}
  601 +
  602 +void board_quiesce_devices(void)
  603 +{
  604 + gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
  605 + gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
  606 +}
  607 +
  608 +struct display_info_t const displays[] = {{
  609 + .bus = LCDIF_BASE_ADDR,
  610 + .addr = 0,
  611 + .pixfmt = 24,
  612 + .detect = NULL,
  613 + .enable = do_enable_mipi2hdmi,
  614 + .mode = {
  615 + .name = "MIPI2HDMI",
  616 + .refresh = 60,
  617 + .xres = 1920,
  618 + .yres = 1080,
  619 + .pixclock = 6734, /* 148500000 */
  620 + .left_margin = 148,
  621 + .right_margin = 88,
  622 + .upper_margin = 36,
  623 + .lower_margin = 4,
  624 + .hsync_len = 44,
  625 + .vsync_len = 5,
  626 + .sync = FB_SYNC_EXT,
  627 + .vmode = FB_VMODE_NONINTERLACED
  628 +
  629 +} }, {
  630 + .bus = LCDIF_BASE_ADDR,
  631 + .addr = 0,
  632 + .pixfmt = 24,
  633 + .detect = NULL,
  634 + .enable = do_enable_mipi_led,
  635 + .mode = {
  636 + .name = "RM67191_OLED",
  637 + .refresh = 60,
  638 + .xres = 1080,
  639 + .yres = 1920,
  640 + .pixclock = 7575, /* 132000000 */
  641 + .left_margin = 34,
  642 + .right_margin = 20,
  643 + .upper_margin = 4,
  644 + .lower_margin = 10,
  645 + .hsync_len = 2,
  646 + .vsync_len = 2,
  647 + .sync = FB_SYNC_EXT,
  648 + .vmode = FB_VMODE_NONINTERLACED
  649 +
  650 +} } };
  651 +size_t display_count = ARRAY_SIZE(displays);
  652 +#endif
  653 +
  654 +int board_late_init(void)
  655 +{
  656 +#ifdef CONFIG_ENV_IS_IN_MMC
  657 + board_late_mmc_env_init();
  658 +#endif
  659 +
  660 + return 0;
  661 +}
board/freescale/imx8mn_evk/spl.c
Diff comments   View file @ 7081a12
  1 +/*
  2 + * Copyright 2018-2019 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +#include <asm/io.h>
  10 +#include <errno.h>
  11 +#include <asm/io.h>
  12 +#include <asm/mach-imx/iomux-v3.h>
  13 +#include <asm/arch/imx8mn_pins.h>
  14 +#include <asm/arch/sys_proto.h>
  15 +#include <power/pmic.h>
  16 +#include <power/bd71837.h>
  17 +#include <asm/arch/clock.h>
  18 +#include <asm/mach-imx/gpio.h>
  19 +#include <asm/mach-imx/mxc_i2c.h>
  20 +#include <fsl_esdhc.h>
  21 +#include <mmc.h>
  22 +#include <asm/arch/ddr.h>
  23 +
  24 +DECLARE_GLOBAL_DATA_PTR;
  25 +
  26 +void spl_dram_init(void)
  27 +{
  28 + ddr_init(&dram_timing);
  29 +}
  30 +
  31 +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  32 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  33 +struct i2c_pads_info i2c_pad_info1 = {
  34 + .scl = {
  35 + .i2c_mode = IMX8MN_PAD_I2C1_SCL__I2C1_SCL | PC,
  36 + .gpio_mode = IMX8MN_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  37 + .gp = IMX_GPIO_NR(5, 14),
  38 + },
  39 + .sda = {
  40 + .i2c_mode = IMX8MN_PAD_I2C1_SDA__I2C1_SDA | PC,
  41 + .gpio_mode = IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  42 + .gp = IMX_GPIO_NR(5, 15),
  43 + },
  44 +};
  45 +
  46 +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 15)
  47 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  48 +
  49 +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
  50 + PAD_CTL_FSEL2)
  51 +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
  52 +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4)
  53 +
  54 +
  55 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  56 + IMX8MN_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57 + IMX8MN_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58 + IMX8MN_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59 + IMX8MN_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60 + IMX8MN_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61 + IMX8MN_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62 + IMX8MN_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63 + IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64 + IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65 + IMX8MN_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66 +};
  67 +
  68 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  69 + IMX8MN_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70 + IMX8MN_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71 + IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72 + IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73 + IMX8MN_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74 + IMX8MN_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75 + IMX8MN_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  76 + IMX8MN_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
  77 +};
  78 +
  79 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  80 + {USDHC2_BASE_ADDR, 0, 1},
  81 + {USDHC3_BASE_ADDR, 0, 1},
  82 +};
  83 +
  84 +int board_mmc_init(bd_t *bis)
  85 +{
  86 + int i, ret;
  87 + /*
  88 + * According to the board_mmc_init() the following map is done:
  89 + * (U-Boot device node) (Physical Port)
  90 + * mmc0 USDHC1
  91 + * mmc1 USDHC2
  92 + */
  93 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  94 + switch (i) {
  95 + case 0:
  96 + init_clk_usdhc(1);
  97 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  98 + imx_iomux_v3_setup_multiple_pads(
  99 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  100 + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
  101 + gpio_direction_output(USDHC2_PWR_GPIO, 0);
  102 + udelay(500);
  103 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  104 + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
  105 + gpio_direction_input(USDHC2_CD_GPIO);
  106 + break;
  107 + case 1:
  108 + init_clk_usdhc(2);
  109 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  110 + imx_iomux_v3_setup_multiple_pads(
  111 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  112 + break;
  113 + default:
  114 + printf("Warning: you configured more USDHC controllers"
  115 + "(%d) than supported by the board\n", i + 1);
  116 + return -EINVAL;
  117 + }
  118 +
  119 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  120 + if (ret)
  121 + return ret;
  122 + }
  123 +
  124 + return 0;
  125 +}
  126 +
  127 +int board_mmc_getcd(struct mmc *mmc)
  128 +{
  129 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  130 + int ret = 0;
  131 +
  132 + switch (cfg->esdhc_base) {
  133 + case USDHC3_BASE_ADDR:
  134 + ret = 1;
  135 + break;
  136 + case USDHC2_BASE_ADDR:
  137 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  138 + return ret;
  139 + }
  140 +
  141 + return 1;
  142 +}
  143 +
  144 +#ifdef CONFIG_POWER
  145 +#define I2C_PMIC 0
  146 +int power_init_board(void)
  147 +{
  148 + struct pmic *p;
  149 + int ret;
  150 +
  151 + ret = power_bd71837_init(I2C_PMIC);
  152 + if (ret)
  153 + printf("power init failed");
  154 +
  155 + p = pmic_get("BD71837");
  156 + pmic_probe(p);
  157 +
  158 +
  159 + /* decrease RESET key long push time from the default 10s to 10ms */
  160 + pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
  161 +
  162 + /* unlock the PMIC regs */
  163 + pmic_reg_write(p, BD71837_REGLOCK, 0x1);
  164 +
  165 + /* increase VDD_SOC/VDD_DRAM to typical value 0.95v for 3Ghz DDRs */
  166 + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x19);
  167 +
  168 +#ifdef CONFIG_IMX8M_DDR4
  169 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
  170 + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
  171 +#endif
  172 +
  173 + /* lock the PMIC regs */
  174 + pmic_reg_write(p, BD71837_REGLOCK, 0x11);
  175 +
  176 + return 0;
  177 +}
  178 +#endif
  179 +
  180 +void spl_board_init(void)
  181 +{
  182 + puts("Normal Boot\n");
  183 +}
  184 +
  185 +#ifdef CONFIG_SPL_LOAD_FIT
  186 +int board_fit_config_name_match(const char *name)
  187 +{
  188 + /* Just empty function now - can't decide what to choose */
  189 + debug("%s: %s\n", __func__, name);
  190 +
  191 + return 0;
  192 +}
  193 +#endif
  194 +
  195 +void board_init_f(ulong dummy)
  196 +{
  197 + int ret;
  198 +
  199 + /* Clear the BSS. */
  200 + memset(__bss_start, 0, __bss_end - __bss_start);
  201 +
  202 + arch_cpu_init();
  203 +
  204 + board_early_init_f();
  205 +
  206 + timer_init();
  207 +
  208 + preloader_console_init();
  209 +
  210 + ret = spl_init();
  211 + if (ret) {
  212 + debug("spl_init() failed: %d\n", ret);
  213 + hang();
  214 + }
  215 +
  216 + enable_tzc380();
  217 +
  218 + /* Adjust pmic voltage to 1.0V for 800M */
  219 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  220 +
  221 + power_init_board();
  222 +
  223 + /* DDR initialization */
  224 + spl_dram_init();
  225 +
  226 + board_init_r(NULL, 0);
  227 +}
configs/imx8mn_ddr4_evk_defconfig
Diff comments   View file @ 7081a12
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_IMX8M=y
  3 +CONFIG_SYS_TEXT_BASE=0x40200000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  5 +CONFIG_USB_TCPC=y
  6 +CONFIG_TARGET_IMX8MN_EVK=y
  7 +CONFIG_ARCH_MISC_INIT=y
  8 +CONFIG_SPL=y
  9 +CONFIG_FIT=y
  10 +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
  11 +CONFIG_SPL_LOAD_FIT=y
  12 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
  13 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,SPL_TEXT_BASE=0x912000"
  14 +CONFIG_SPL_BOARD_INIT=y
  15 +CONFIG_SPL_MMC_SUPPORT=y
  16 +CONFIG_SPL_SERIAL_SUPPORT=y
  17 +CONFIG_NR_DRAM_BANKS=1
  18 +CONFIG_HUSH_PARSER=y
  19 +CONFIG_OF_LIBFDT=y
  20 +CONFIG_FS_FAT=y
  21 +CONFIG_CMD_EXT2=y
  22 +CONFIG_CMD_EXT4=y
  23 +CONFIG_CMD_EXT4_WRITE=y
  24 +CONFIG_CMD_FAT=y
  25 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mn-ddr4-evk"
  26 +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb"
  27 +CONFIG_ENV_IS_IN_MMC=y
  28 +CONFIG_CMD_SF=y
  29 +CONFIG_CMD_I2C=y
  30 +CONFIG_CMD_GPIO=y
  31 +CONFIG_CMD_CACHE=y
  32 +CONFIG_CMD_REGULATOR=y
  33 +CONFIG_CMD_MEMTEST=y
  34 +CONFIG_OF_CONTROL=y
  35 +CONFIG_FASTBOOT=y
  36 +CONFIG_USB_FUNCTION_FASTBOOT=y
  37 +CONFIG_CMD_FASTBOOT=y
  38 +CONFIG_ANDROID_BOOT_IMAGE=y
  39 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  40 +CONFIG_FASTBOOT_BUF_ADDR=0x42800000
  41 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  42 +CONFIG_FASTBOOT_FLASH=y
  43 +
  44 +CONFIG_DM_GPIO=y
  45 +CONFIG_DM_I2C=y
  46 +CONFIG_SYS_I2C_MXC=y
  47 +CONFIG_DM_MMC=y
  48 +# CONFIG_DM_PMIC=y
  49 +CONFIG_EFI_PARTITION=y
  50 +CONFIG_DM_SPI_FLASH=y
  51 +CONFIG_DM_SPI=y
  52 +CONFIG_FSL_FSPI=y
  53 +CONFIG_SPI=y
  54 +CONFIG_SPI_FLASH=y
  55 +CONFIG_SPI_FLASH_BAR=y
  56 +CONFIG_SPI_FLASH_STMICRO=y
  57 +CONFIG_SF_DEFAULT_BUS=0
  58 +CONFIG_SF_DEFAULT_CS=0
  59 +CONFIG_SF_DEFAULT_SPEED=40000000
  60 +CONFIG_SF_DEFAULT_MODE=0
  61 +
  62 +CONFIG_DM_ETH=y
  63 +CONFIG_PINCTRL=y
  64 +CONFIG_PINCTRL_IMX8M=y
  65 +CONFIG_DM_REGULATOR=y
  66 +CONFIG_DM_REGULATOR_FIXED=y
  67 +CONFIG_DM_REGULATOR_GPIO=y
  68 +CONFIG_NXP_TMU=y
  69 +CONFIG_DM_THERMAL=y
  70 +CONFIG_USB=y
  71 +CONFIG_USB_GADGET=y
  72 +CONFIG_DM_USB=y
  73 +CONFIG_USB_EHCI_HCD=y
  74 +
  75 +CONFIG_SPL_USB_HOST_SUPPORT=y
  76 +CONFIG_SPL_USB_GADGET_SUPPORT=y
  77 +CONFIG_SPL_USB_SDP_SUPPORT=y
  78 +CONFIG_SDP_LOADADDR=0x40400000
  79 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  80 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  81 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  82 +
  83 +CONFIG_VIDEO=y
  84 +CONFIG_IMX_SEC_MIPI_DSI=y
  85 +
  86 +CONFIG_SPL_IMX_ROMAPI_SUPPORT=y
  87 +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
include/configs/imx8mn_evk.h
Diff comments   View file @ 7081a12
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __IMX8MN_EVK_H
  8 +#define __IMX8MN_EVK_H
  9 +
  10 +#include <linux/sizes.h>
  11 +#include <asm/arch/imx-regs.h>
  12 +
  13 +#include "imx_env.h"
  14 +
  15 +#ifdef CONFIG_SECURE_BOOT
  16 +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
  17 +#endif
  18 +
  19 +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
  20 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  21 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  22 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  23 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  24 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  25 +
  26 +#ifdef CONFIG_SPL_BUILD
  27 +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  28 +#define CONFIG_SPL_WATCHDOG_SUPPORT
  29 +#define CONFIG_SPL_POWER_SUPPORT
  30 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  31 +#define CONFIG_SPL_I2C_SUPPORT
  32 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  33 +#define CONFIG_SPL_STACK 0x95fff0
  34 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  35 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  36 +#define CONFIG_SPL_GPIO_SUPPORT
  37 +#define CONFIG_SPL_BSS_START_ADDR 0x00950000
  38 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
  39 +#define CONFIG_SYS_SPL_MALLOC_START 0x00940000
  40 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 /* 64 KB */
  41 +#define CONFIG_SYS_ICACHE_OFF
  42 +#define CONFIG_SYS_DCACHE_OFF
  43 +
  44 +#define CONFIG_MALLOC_F_ADDR 0x00940000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  45 +
  46 +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
  47 +
  48 +#undef CONFIG_DM_MMC
  49 +#undef CONFIG_DM_PMIC
  50 +#undef CONFIG_DM_PMIC_PFUZE100
  51 +
  52 +#define CONFIG_POWER
  53 +#define CONFIG_POWER_I2C
  54 +#define CONFIG_POWER_BD71837
  55 +
  56 +#define CONFIG_SYS_I2C
  57 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  58 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  59 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  60 +
  61 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  62 +
  63 +#if defined(CONFIG_NAND_BOOT)
  64 +#define CONFIG_SPL_NAND_SUPPORT
  65 +#define CONFIG_SPL_DMA_SUPPORT
  66 +#define CONFIG_SPL_NAND_MXS
  67 +#define CONFIG_SPL_NAND_BASE
  68 +#define CONFIG_SPL_NAND_IDENT
  69 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
  70 +
  71 +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
  72 +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
  73 + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
  74 +#endif
  75 +
  76 +#endif
  77 +
  78 +#define CONFIG_CMD_READ
  79 +#define CONFIG_SERIAL_TAG
  80 +#define CONFIG_FASTBOOT_USB_DEV 0
  81 +
  82 +#define CONFIG_REMAKE_ELF
  83 +
  84 +#define CONFIG_BOARD_EARLY_INIT_F
  85 +#define CONFIG_BOARD_LATE_INIT
  86 +
  87 +#undef CONFIG_CMD_EXPORTENV
  88 +#undef CONFIG_CMD_IMPORTENV
  89 +#undef CONFIG_CMD_IMLS
  90 +
  91 +#undef CONFIG_CMD_CRC32
  92 +#undef CONFIG_BOOTM_NETBSD
  93 +
  94 +/* ENET Config */
  95 +/* ENET1 */
  96 +#if defined(CONFIG_CMD_NET)
  97 +#define CONFIG_CMD_PING
  98 +#define CONFIG_CMD_DHCP
  99 +#define CONFIG_CMD_MII
  100 +#define CONFIG_MII
  101 +#define CONFIG_ETHPRIME "FEC"
  102 +
  103 +#define CONFIG_FEC_MXC
  104 +#define CONFIG_FEC_XCV_TYPE RGMII
  105 +#define CONFIG_FEC_MXC_PHYADDR 0
  106 +#define FEC_QUIRK_ENET_MAC
  107 +
  108 +#define CONFIG_PHY_GIGE
  109 +#define IMX_FEC_BASE 0x30BE0000
  110 +
  111 +#define CONFIG_PHYLIB
  112 +#define CONFIG_PHY_ATHEROS
  113 +#endif
  114 +
  115 +#define CONFIG_MFG_ENV_SETTINGS \
  116 + CONFIG_MFG_ENV_SETTINGS_DEFAULT \
  117 + "initrd_addr=0x43800000\0" \
  118 + "initrd_high=0xffffffffffffffff\0" \
  119 + "emmc_dev=2\0"\
  120 + "sd_dev=1\0" \
  121 +
  122 +/* Initial environment variables */
  123 +#define CONFIG_EXTRA_ENV_SETTINGS \
  124 + CONFIG_MFG_ENV_SETTINGS \
  125 + "script=boot.scr\0" \
  126 + "image=Image\0" \
  127 + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  128 + "fdt_addr=0x43000000\0" \
  129 + "fdt_high=0xffffffffffffffff\0" \
  130 + "boot_fdt=try\0" \
  131 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  132 + "initrd_addr=0x43800000\0" \
  133 + "initrd_high=0xffffffffffffffff\0" \
  134 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  135 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  136 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  137 + "mmcautodetect=yes\0" \
  138 + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
  139 + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  140 + "bootscript=echo Running bootscript from mmc ...; " \
  141 + "source\0" \
  142 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  143 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  144 + "mmcboot=echo Booting from mmc ...; " \
  145 + "run mmcargs; " \
  146 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  147 + "if run loadfdt; then " \
  148 + "booti ${loadaddr} - ${fdt_addr}; " \
  149 + "else " \
  150 + "echo WARN: Cannot load the DT; " \
  151 + "fi; " \
  152 + "else " \
  153 + "echo wait for boot; " \
  154 + "fi;\0" \
  155 + "netargs=setenv bootargs console=${console} " \
  156 + "root=/dev/nfs " \
  157 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  158 + "netboot=echo Booting from net ...; " \
  159 + "run netargs; " \
  160 + "if test ${ip_dyn} = yes; then " \
  161 + "setenv get_cmd dhcp; " \
  162 + "else " \
  163 + "setenv get_cmd tftp; " \
  164 + "fi; " \
  165 + "${get_cmd} ${loadaddr} ${image}; " \
  166 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  167 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  168 + "booti ${loadaddr} - ${fdt_addr}; " \
  169 + "else " \
  170 + "echo WARN: Cannot load the DT; " \
  171 + "fi; " \
  172 + "else " \
  173 + "booti; " \
  174 + "fi;\0"
  175 +
  176 +#define CONFIG_BOOTCOMMAND \
  177 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  178 + "if run loadbootscript; then " \
  179 + "run bootscript; " \
  180 + "else " \
  181 + "if run loadimage; then " \
  182 + "run mmcboot; " \
  183 + "else run netboot; " \
  184 + "fi; " \
  185 + "fi; " \
  186 + "else booti ${loadaddr} - ${fdt_addr}; fi"
  187 +
  188 +/* Link Definitions */
  189 +#define CONFIG_LOADADDR 0x40480000
  190 +
  191 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  192 +
  193 +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  194 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
  195 +#define CONFIG_SYS_INIT_SP_OFFSET \
  196 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  197 +#define CONFIG_SYS_INIT_SP_ADDR \
  198 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  199 +
  200 +#define CONFIG_ENV_OVERWRITE
  201 +#if defined(CONFIG_ENV_IS_IN_MMC)
  202 +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
  203 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  204 +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
  205 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  206 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  207 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  208 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  209 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  210 +#elif defined(CONFIG_ENV_IS_IN_NAND)
  211 +#define CONFIG_ENV_OFFSET (60 << 20)
  212 +#endif
  213 +#define CONFIG_ENV_SIZE 0x1000
  214 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  215 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  216 +
  217 +/* Size of malloc() pool */
  218 +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
  219 +
  220 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  221 +#define PHYS_SDRAM 0x40000000
  222 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
  223 +
  224 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  225 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  226 + (PHYS_SDRAM_SIZE >> 1))
  227 +
  228 +#define CONFIG_BAUDRATE 115200
  229 +
  230 +#define CONFIG_MXC_UART
  231 +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  232 +
  233 +/* Monitor Command Prompt */
  234 +#undef CONFIG_SYS_PROMPT
  235 +#define CONFIG_SYS_PROMPT "u-boot=> "
  236 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  237 +#define CONFIG_SYS_CBSIZE 2048
  238 +#define CONFIG_SYS_MAXARGS 64
  239 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  240 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  241 + sizeof(CONFIG_SYS_PROMPT) + 16)
  242 +
  243 +#define CONFIG_IMX_BOOTAUX
  244 +
  245 +/* USDHC */
  246 +#define CONFIG_CMD_MMC
  247 +#define CONFIG_FSL_ESDHC
  248 +#define CONFIG_FSL_USDHC
  249 +
  250 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  251 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  252 +
  253 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  254 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  255 +
  256 +#ifdef CONFIG_FSL_FSPI
  257 +#define FSL_FSPI_FLASH_SIZE SZ_32M
  258 +#define FSL_FSPI_FLASH_NUM 1
  259 +#define FSPI0_BASE_ADDR 0x30bb0000
  260 +#define FSPI0_AMBA_BASE 0x0
  261 +#define CONFIG_FSPI_QUAD_SUPPORT
  262 +
  263 +#define CONFIG_SYS_FSL_FSPI_AHB
  264 +#endif
  265 +
  266 +#ifdef CONFIG_NAND_MXS
  267 +#define CONFIG_CMD_NAND_TRIMFFS
  268 +
  269 +/* NAND stuff */
  270 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  271 +#define CONFIG_SYS_NAND_BASE 0x20000000
  272 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  273 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  274 +
  275 +#ifdef CONFIG_CMD_UBI
  276 +#define CONFIG_MTD_DEVICE
  277 +#endif
  278 +#endif /* CONFIG_NAND_MXS */
  279 +
  280 +
  281 +#define CONFIG_MXC_GPIO
  282 +
  283 +#define CONFIG_MXC_OCOTP
  284 +#define CONFIG_CMD_FUSE
  285 +
  286 +#ifndef CONFIG_DM_I2C
  287 +#define CONFIG_SYS_I2C
  288 +#endif
  289 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  290 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  291 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  292 +#define CONFIG_SYS_I2C_SPEED 100000
  293 +
  294 +/* USB configs */
  295 +#ifndef CONFIG_SPL_BUILD
  296 +#define CONFIG_CMD_USB
  297 +#define CONFIG_USB_STORAGE
  298 +#define CONFIG_USBD_HS
  299 +
  300 +#define CONFIG_CMD_USB_MASS_STORAGE
  301 +#define CONFIG_USB_GADGET_MASS_STORAGE
  302 +#define CONFIG_USB_FUNCTION_MASS_STORAGE
  303 +
  304 +#endif
  305 +
  306 +#define CONFIG_USB_GADGET_DUALSPEED
  307 +#define CONFIG_USB_GADGET_VBUS_DRAW 2
  308 +
  309 +#define CONFIG_CI_UDC
  310 +
  311 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  312 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  313 +
  314 +#ifdef CONFIG_VIDEO
  315 +#define CONFIG_VIDEO_MXS
  316 +#define CONFIG_VIDEO_LOGO
  317 +#define CONFIG_SPLASH_SCREEN
  318 +#define CONFIG_SPLASH_SCREEN_ALIGN
  319 +#define CONFIG_CMD_BMP
  320 +#define CONFIG_BMP_16BPP
  321 +#define CONFIG_VIDEO_BMP_RLE8
  322 +#define CONFIG_VIDEO_BMP_LOGO
  323 +#define CONFIG_IMX_VIDEO_SKIP
  324 +#define CONFIG_RM67191
  325 +#endif
  326 +
  327 +#define CONFIG_OF_SYSTEM_SETUP
  328 +#endif