Eric Lee / smarc-uboot

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Commit 70fa29c71663e1c0882c263c6fd5c089d4d90e0b

Authored by Ye Li
1 parent c882f43aef
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-20886-7 DTS: imx8qm/qxp: Add MU8 and MU9 nodes 

We use MU8 and MU9 to communicate with M4_0 and M4_1 in u-boot. Add
relevant nodes for the MU driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b06674a91991fe3bfe5a2f6000195cb8546c72a6)

Showing 3 changed files with 41 additions and 0 deletions Inline Diff

arch/arm/dts/fsl-imx8qm.dtsi
Diff comments   View file @ 70fa29c
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "fsl-imx8-ca53.dtsi" 17 #include "fsl-imx8-ca53.dtsi"
18 #include "fsl-imx8-ca72.dtsi" 18 #include "fsl-imx8-ca72.dtsi"
19 #include <dt-bindings/clock/imx8qm-clock.h> 19 #include <dt-bindings/clock/imx8qm-clock.h>
20 #include <dt-bindings/soc/imx_rsrc.h> 20 #include <dt-bindings/soc/imx_rsrc.h>
21 #include <dt-bindings/soc/imx8_hsio.h> 21 #include <dt-bindings/soc/imx8_hsio.h>
22 #include <dt-bindings/soc/imx8_pd.h> 22 #include <dt-bindings/soc/imx8_pd.h>
23 #include <dt-bindings/pinctrl/pads-imx8qm.h> 23 #include <dt-bindings/pinctrl/pads-imx8qm.h>
24 #include <dt-bindings/gpio/gpio.h> 24 #include <dt-bindings/gpio/gpio.h>
25 25
26 / { 26 / {
27 compatible = "fsl,imx8qm"; 27 compatible = "fsl,imx8qm";
28 interrupt-parent = <&gic>; 28 interrupt-parent = <&gic>;
29 #address-cells = <2>; 29 #address-cells = <2>;
30 #size-cells = <2>; 30 #size-cells = <2>;
31 31
32 aliases { 32 aliases {
33 csi0 = &mipi_csi_0; 33 csi0 = &mipi_csi_0;
34 csi1 = &mipi_csi_1; 34 csi1 = &mipi_csi_1;
35 dpu0 = &dpu1; 35 dpu0 = &dpu1;
36 dpu1 = &dpu2; 36 dpu1 = &dpu2;
37 ethernet0 = &fec1; 37 ethernet0 = &fec1;
38 ethernet1 = &fec2; 38 ethernet1 = &fec2;
39 ldb0 = &ldb1; 39 ldb0 = &ldb1;
40 ldb1 = &ldb2; 40 ldb1 = &ldb2;
41 isi0 = &isi_0; 41 isi0 = &isi_0;
42 isi1 = &isi_1; 42 isi1 = &isi_1;
43 isi2 = &isi_2; 43 isi2 = &isi_2;
44 isi3 = &isi_3; 44 isi3 = &isi_3;
45 isi4 = &isi_4; 45 isi4 = &isi_4;
46 isi5 = &isi_5; 46 isi5 = &isi_5;
47 isi6 = &isi_6; 47 isi6 = &isi_6;
48 isi7 = &isi_7; 48 isi7 = &isi_7;
49 serial0 = &lpuart0; 49 serial0 = &lpuart0;
50 serial1 = &lpuart1; 50 serial1 = &lpuart1;
51 serial2 = &lpuart2; 51 serial2 = &lpuart2;
52 serial3 = &lpuart3; 52 serial3 = &lpuart3;
53 serial4 = &lpuart4; 53 serial4 = &lpuart4;
54 gpio0 = &gpio0; 54 gpio0 = &gpio0;
55 gpio1 = &gpio1; 55 gpio1 = &gpio1;
56 gpio2 = &gpio2; 56 gpio2 = &gpio2;
57 gpio3 = &gpio3; 57 gpio3 = &gpio3;
58 gpio4 = &gpio4; 58 gpio4 = &gpio4;
59 gpio5 = &gpio5; 59 gpio5 = &gpio5;
60 gpio6 = &gpio6; 60 gpio6 = &gpio6;
61 gpio7 = &gpio7; 61 gpio7 = &gpio7;
62 i2c0 = &i2c0; 62 i2c0 = &i2c0;
63 i2c1 = &i2c1; 63 i2c1 = &i2c1;
64 i2c2 = &i2c2; 64 i2c2 = &i2c2;
65 i2c3 = &i2c3; 65 i2c3 = &i2c3;
66 i2c4 = &i2c4; 66 i2c4 = &i2c4;
67 i2c6 = &i2c1_lvds0; 67 i2c6 = &i2c1_lvds0;
68 i2c8 = &i2c1_lvds1; 68 i2c8 = &i2c1_lvds1;
69 usb0 = &usbotg1; 69 usb0 = &usbotg1;
70 usbphy0 = &usbphy1; 70 usbphy0 = &usbphy1;
71 usb1 = &usb2; 71 usb1 = &usb2;
72 usbphy1 = &usb2_phy; 72 usbphy1 = &usb2_phy;
73 spi0 = &flexspi0; 73 spi0 = &flexspi0;
74 }; 74 };
75 75
76 memory@80000000 { 76 memory@80000000 {
77 device_type = "memory"; 77 device_type = "memory";
78 reg = <0x00000000 0x80000000 0 0x40000000>; 78 reg = <0x00000000 0x80000000 0 0x40000000>;
79 /* DRAM space - 1, size : 1 GB DRAM */ 79 /* DRAM space - 1, size : 1 GB DRAM */
80 }; 80 };
81 81
82 reserved-memory { 82 reserved-memory {
83 #address-cells = <2>; 83 #address-cells = <2>;
84 #size-cells = <2>; 84 #size-cells = <2>;
85 ranges; 85 ranges;
86 86
87 /* global autoconfigured region for contiguous allocations */ 87 /* global autoconfigured region for contiguous allocations */
88 linux,cma { 88 linux,cma {
89 compatible = "shared-dma-pool"; 89 compatible = "shared-dma-pool";
90 reusable; 90 reusable;
91 size = <0 0x28000000>; 91 size = <0 0x28000000>;
92 alloc-ranges = <0 0x80000000 0 0x80000000>; 92 alloc-ranges = <0 0x80000000 0 0x80000000>;
93 linux,cma-default; 93 linux,cma-default;
94 }; 94 };
95 }; 95 };
96 96
97 gic: interrupt-controller@51a00000 { 97 gic: interrupt-controller@51a00000 {
98 compatible = "arm,gic-v3"; 98 compatible = "arm,gic-v3";
99 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 99 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
100 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 100 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
101 #interrupt-cells = <3>; 101 #interrupt-cells = <3>;
102 interrupt-controller; 102 interrupt-controller;
103 interrupts = <GIC_PPI 9 103 interrupts = <GIC_PPI 9
104 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 104 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
105 }; 105 };
106 106
107 mu8: mu@5d230000 {
108 compatible = "fsl,imx-m4-mu";
109 reg = <0x0 0x5d230000 0x0 0x10000>;
110 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
111 power-domains = <&pd_lsio_mu8a>;
112 status = "okay";
113 };
114
115 mu9: mu@5d240000 {
116 compatible = "fsl,imx-m4-mu";
117 reg = <0x0 0x5d240000 0x0 0x10000>;
118 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
119 power-domains = <&pd_lsio_mu9a>;
120 status = "okay";
121 };
122
107 mu: mu@5d1b0000 { 123 mu: mu@5d1b0000 {
108 compatible = "fsl,imx8-mu"; 124 compatible = "fsl,imx8-mu";
109 reg = <0x0 0x5d1b0000 0x0 0x10000>; 125 reg = <0x0 0x5d1b0000 0x0 0x10000>;
110 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 126 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
111 fsl,scu_ap_mu_id = <0>; 127 fsl,scu_ap_mu_id = <0>;
112 #mbox-cells = <4>; 128 #mbox-cells = <4>;
113 status = "okay"; 129 status = "okay";
114 }; 130 };
115 131
116 clk: clk { 132 clk: clk {
117 compatible = "fsl,imx8qm-clk"; 133 compatible = "fsl,imx8qm-clk";
118 #clock-cells = <1>; 134 #clock-cells = <1>;
119 }; 135 };
120 136
121 iomuxc: iomuxc { 137 iomuxc: iomuxc {
122 compatible = "fsl,imx8qm-iomuxc"; 138 compatible = "fsl,imx8qm-iomuxc";
123 }; 139 };
124 140
125 timer { 141 timer {
126 compatible = "arm,armv8-timer"; 142 compatible = "arm,armv8-timer";
127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 143 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 144 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 145 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 146 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
131 clock-frequency = <8000000>; 147 clock-frequency = <8000000>;
132 }; 148 };
133 149
134 smmu: iommu@51400000 { 150 smmu: iommu@51400000 {
135 compatible = "arm,mmu-500"; 151 compatible = "arm,mmu-500";
136 interrupt-parent = <&gic>; 152 interrupt-parent = <&gic>;
137 reg = <0 0x51400000 0 0x40000>; 153 reg = <0 0x51400000 0 0x40000>;
138 #global-interrupts = <1>; 154 #global-interrupts = <1>;
139 #iommu-cells = <2>; 155 #iommu-cells = <2>;
140 interrupts = <0 32 4>, 156 interrupts = <0 32 4>,
141 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 157 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
142 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 158 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
143 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 159 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
144 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 160 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
145 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 161 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
146 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 162 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
147 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, 163 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
148 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; 164 <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
149 }; 165 };
150 166
151 imx8qm-pm { 167 imx8qm-pm {
152 compatible = "simple-bus"; 168 compatible = "simple-bus";
153 #address-cells = <1>; 169 #address-cells = <1>;
154 #size-cells = <0>; 170 #size-cells = <0>;
155 171
156 pd_dc0: PD_DC_0 { 172 pd_dc0: PD_DC_0 {
157 compatible = "nxp,imx8-pd"; 173 compatible = "nxp,imx8-pd";
158 reg = <SC_R_DC_0>; 174 reg = <SC_R_DC_0>;
159 #power-domain-cells = <0>; 175 #power-domain-cells = <0>;
160 #address-cells = <1>; 176 #address-cells = <1>;
161 #size-cells = <0>; 177 #size-cells = <0>;
162 178
163 pd_dc0_pll0: PD_DC_0_PLL_0{ 179 pd_dc0_pll0: PD_DC_0_PLL_0{
164 reg = <SC_R_DC_0_PLL_0>; 180 reg = <SC_R_DC_0_PLL_0>;
165 #power-domain-cells = <0>; 181 #power-domain-cells = <0>;
166 power-domains =<&pd_dc0>; 182 power-domains =<&pd_dc0>;
167 #address-cells = <1>; 183 #address-cells = <1>;
168 #size-cells = <0>; 184 #size-cells = <0>;
169 185
170 pd_dc0_pll1: PD_DC_0_PLL_1{ 186 pd_dc0_pll1: PD_DC_0_PLL_1{
171 reg = <SC_R_DC_0_PLL_1>; 187 reg = <SC_R_DC_0_PLL_1>;
172 #power-domain-cells = <0>; 188 #power-domain-cells = <0>;
173 power-domains =<&pd_dc0_pll0>; 189 power-domains =<&pd_dc0_pll0>;
174 }; 190 };
175 }; 191 };
176 192
177 pd_mipi0: PD_MIPI_0_DSI { 193 pd_mipi0: PD_MIPI_0_DSI {
178 reg = <SC_R_MIPI_0>; 194 reg = <SC_R_MIPI_0>;
179 #power-domain-cells = <0>; 195 #power-domain-cells = <0>;
180 power-domains =<&pd_dc0>; 196 power-domains =<&pd_dc0>;
181 #address-cells = <1>; 197 #address-cells = <1>;
182 #size-cells = <0>; 198 #size-cells = <0>;
183 199
184 pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 { 200 pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 {
185 reg = <SC_R_MIPI_0_I2C_0>; 201 reg = <SC_R_MIPI_0_I2C_0>;
186 #power-domain-cells = <0>; 202 #power-domain-cells = <0>;
187 power-domains =<&pd_mipi0>; 203 power-domains =<&pd_mipi0>;
188 }; 204 };
189 205
190 pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 { 206 pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 {
191 reg = <SC_R_MIPI_0_I2C_1>; 207 reg = <SC_R_MIPI_0_I2C_1>;
192 #power-domain-cells = <0>; 208 #power-domain-cells = <0>;
193 power-domains =<&pd_mipi0>; 209 power-domains =<&pd_mipi0>;
194 }; 210 };
195 211
196 pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 { 212 pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 {
197 reg = <SC_R_MIPI_0_PWM_0>; 213 reg = <SC_R_MIPI_0_PWM_0>;
198 #power-domain-cells = <0>; 214 #power-domain-cells = <0>;
199 power-domains =<&pd_mipi0>; 215 power-domains =<&pd_mipi0>;
200 }; 216 };
201 }; 217 };
202 218
203 pd_lvds0: PD_LVDS0 { 219 pd_lvds0: PD_LVDS0 {
204 reg = <SC_R_LVDS_0>; 220 reg = <SC_R_LVDS_0>;
205 #power-domain-cells = <0>; 221 #power-domain-cells = <0>;
206 power-domains =<&pd_dc0>; 222 power-domains =<&pd_dc0>;
207 #address-cells = <1>; 223 #address-cells = <1>;
208 #size-cells = <0>; 224 #size-cells = <0>;
209 225
210 pd_lvds0_i2c0: PD_LVDS0_I2C0 { 226 pd_lvds0_i2c0: PD_LVDS0_I2C0 {
211 reg = <SC_R_LVDS_0_I2C_0>; 227 reg = <SC_R_LVDS_0_I2C_0>;
212 #power-domain-cells = <0>; 228 #power-domain-cells = <0>;
213 power-domains =<&pd_lvds0>; 229 power-domains =<&pd_lvds0>;
214 }; 230 };
215 231
216 pd_lvds0_pwm: PD_LVDS0_PWM { 232 pd_lvds0_pwm: PD_LVDS0_PWM {
217 reg = <SC_R_LVDS_0_PWM_0>; 233 reg = <SC_R_LVDS_0_PWM_0>;
218 #power-domain-cells = <0>; 234 #power-domain-cells = <0>;
219 power-domains =<&pd_lvds0>; 235 power-domains =<&pd_lvds0>;
220 }; 236 };
221 }; 237 };
222 238
223 pd_hdmi: PD_HDMI { 239 pd_hdmi: PD_HDMI {
224 reg = <SC_R_HDMI>; 240 reg = <SC_R_HDMI>;
225 #power-domain-cells = <0>; 241 #power-domain-cells = <0>;
226 power-domains =<&pd_dc0>; 242 power-domains =<&pd_dc0>;
227 #address-cells = <1>; 243 #address-cells = <1>;
228 #size-cells = <0>; 244 #size-cells = <0>;
229 245
230 pd_hdmi_pll0: PD_HDMI_PLL_0{ 246 pd_hdmi_pll0: PD_HDMI_PLL_0{
231 reg = <SC_R_HDMI_PLL_0>; 247 reg = <SC_R_HDMI_PLL_0>;
232 #power-domain-cells = <0>; 248 #power-domain-cells = <0>;
233 power-domains =<&pd_hdmi>; 249 power-domains =<&pd_hdmi>;
234 #address-cells = <1>; 250 #address-cells = <1>;
235 #size-cells = <0>; 251 #size-cells = <0>;
236 252
237 pd_hdmi_pll1: PD_HDMI_PLL_1{ 253 pd_hdmi_pll1: PD_HDMI_PLL_1{
238 reg = <SC_R_HDMI_PLL_1>; 254 reg = <SC_R_HDMI_PLL_1>;
239 #power-domain-cells = <0>; 255 #power-domain-cells = <0>;
240 power-domains =<&pd_hdmi_pll0>; 256 power-domains =<&pd_hdmi_pll0>;
241 #address-cells = <1>; 257 #address-cells = <1>;
242 #size-cells = <0>; 258 #size-cells = <0>;
243 259
244 pd_hdmi_i2c0: PD_HDMI_I2C_0 { 260 pd_hdmi_i2c0: PD_HDMI_I2C_0 {
245 reg = <SC_R_HDMI_I2C_0>; 261 reg = <SC_R_HDMI_I2C_0>;
246 #power-domain-cells = <0>; 262 #power-domain-cells = <0>;
247 power-domains =<&pd_hdmi_pll1>; 263 power-domains =<&pd_hdmi_pll1>;
248 }; 264 };
249 265
250 pd_hdmi_i2s: PD_HDMI_I2S { 266 pd_hdmi_i2s: PD_HDMI_I2S {
251 reg = <SC_R_HDMI_I2S>; 267 reg = <SC_R_HDMI_I2S>;
252 #power-domain-cells = <0>; 268 #power-domain-cells = <0>;
253 power-domains =<&pd_hdmi_pll1>; 269 power-domains =<&pd_hdmi_pll1>;
254 }; 270 };
255 }; 271 };
256 }; 272 };
257 }; 273 };
258 274
259 }; 275 };
260 276
261 pd_dc1: PD_DC_1 { 277 pd_dc1: PD_DC_1 {
262 compatible = "nxp,imx8-pd"; 278 compatible = "nxp,imx8-pd";
263 reg = <SC_R_DC_1>; 279 reg = <SC_R_DC_1>;
264 #power-domain-cells = <0>; 280 #power-domain-cells = <0>;
265 #address-cells = <1>; 281 #address-cells = <1>;
266 #size-cells = <0>; 282 #size-cells = <0>;
267 283
268 pd_dc1_pll0: PD_DC_1_PLL_0{ 284 pd_dc1_pll0: PD_DC_1_PLL_0{
269 reg = <SC_R_DC_1_PLL_0>; 285 reg = <SC_R_DC_1_PLL_0>;
270 #power-domain-cells = <0>; 286 #power-domain-cells = <0>;
271 power-domains =<&pd_dc1>; 287 power-domains =<&pd_dc1>;
272 #address-cells = <1>; 288 #address-cells = <1>;
273 #size-cells = <0>; 289 #size-cells = <0>;
274 290
275 pd_dc1_pll1: PD_DC_1_PLL_1{ 291 pd_dc1_pll1: PD_DC_1_PLL_1{
276 reg = <SC_R_DC_1_PLL_1>; 292 reg = <SC_R_DC_1_PLL_1>;
277 #power-domain-cells = <0>; 293 #power-domain-cells = <0>;
278 power-domains =<&pd_dc1_pll0>; 294 power-domains =<&pd_dc1_pll0>;
279 }; 295 };
280 }; 296 };
281 297
282 pd_mipi1: PD_MIPI_1_DSI { 298 pd_mipi1: PD_MIPI_1_DSI {
283 reg = <SC_R_MIPI_1>; 299 reg = <SC_R_MIPI_1>;
284 #power-domain-cells = <0>; 300 #power-domain-cells = <0>;
285 power-domains =<&pd_dc1>; 301 power-domains =<&pd_dc1>;
286 #address-cells = <1>; 302 #address-cells = <1>;
287 #size-cells = <0>; 303 #size-cells = <0>;
288 304
289 pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 { 305 pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 {
290 reg = <SC_R_MIPI_1_I2C_0>; 306 reg = <SC_R_MIPI_1_I2C_0>;
291 #power-domain-cells = <0>; 307 #power-domain-cells = <0>;
292 power-domains =<&pd_mipi1>; 308 power-domains =<&pd_mipi1>;
293 }; 309 };
294 310
295 pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 { 311 pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 {
296 reg = <SC_R_MIPI_1_I2C_1>; 312 reg = <SC_R_MIPI_1_I2C_1>;
297 #power-domain-cells = <0>; 313 #power-domain-cells = <0>;
298 power-domains =<&pd_mipi1>; 314 power-domains =<&pd_mipi1>;
299 }; 315 };
300 316
301 pd_mipi1_pwm: PD_MIPI_1_DSI_PWM { 317 pd_mipi1_pwm: PD_MIPI_1_DSI_PWM {
302 reg = <SC_R_MIPI_1_PWM_0>; 318 reg = <SC_R_MIPI_1_PWM_0>;
303 #power-domain-cells = <0>; 319 #power-domain-cells = <0>;
304 power-domains =<&pd_mipi1>; 320 power-domains =<&pd_mipi1>;
305 }; 321 };
306 }; 322 };
307 323
308 pd_lvds1: PD_LVDS1 { 324 pd_lvds1: PD_LVDS1 {
309 reg = <SC_R_LVDS_1>; 325 reg = <SC_R_LVDS_1>;
310 #power-domain-cells = <0>; 326 #power-domain-cells = <0>;
311 power-domains =<&pd_dc1>; 327 power-domains =<&pd_dc1>;
312 #address-cells = <1>; 328 #address-cells = <1>;
313 #size-cells = <0>; 329 #size-cells = <0>;
314 330
315 pd_lvds1_i2c0: PD_LVDS1_I2C0 { 331 pd_lvds1_i2c0: PD_LVDS1_I2C0 {
316 reg = <SC_R_LVDS_1_I2C_0>; 332 reg = <SC_R_LVDS_1_I2C_0>;
317 #power-domain-cells = <0>; 333 #power-domain-cells = <0>;
318 power-domains =<&pd_lvds1>; 334 power-domains =<&pd_lvds1>;
319 }; 335 };
320 336
321 pd_lvds1_pwm: PD_LVDS1_PWM { 337 pd_lvds1_pwm: PD_LVDS1_PWM {
322 reg = <SC_R_LVDS_1_PWM_0>; 338 reg = <SC_R_LVDS_1_PWM_0>;
323 #power-domain-cells = <0>; 339 #power-domain-cells = <0>;
324 power-domains =<&pd_lvds1>; 340 power-domains =<&pd_lvds1>;
325 }; 341 };
326 }; 342 };
327 }; 343 };
328 344
329 pd_lsio: PD_LSIO { 345 pd_lsio: PD_LSIO {
330 compatible = "nxp,imx8-pd"; 346 compatible = "nxp,imx8-pd";
331 reg = <SC_R_LAST>; 347 reg = <SC_R_LAST>;
332 #power-domain-cells = <0>; 348 #power-domain-cells = <0>;
333 #address-cells = <1>; 349 #address-cells = <1>;
334 #size-cells = <0>; 350 #size-cells = <0>;
335 351
336 pd_lsio_pwm0: PD_LSIO_PWM_0 { 352 pd_lsio_pwm0: PD_LSIO_PWM_0 {
337 reg = <SC_R_PWM_0>; 353 reg = <SC_R_PWM_0>;
338 #power-domain-cells = <0>; 354 #power-domain-cells = <0>;
339 power-domains = <&pd_lsio>; 355 power-domains = <&pd_lsio>;
340 }; 356 };
341 pd_lsio_pwm1: PD_LSIO_PWM_1 { 357 pd_lsio_pwm1: PD_LSIO_PWM_1 {
342 reg = <SC_R_PWM_1>; 358 reg = <SC_R_PWM_1>;
343 #power-domain-cells = <0>; 359 #power-domain-cells = <0>;
344 power-domains = <&pd_lsio>; 360 power-domains = <&pd_lsio>;
345 }; 361 };
346 pd_lsio_pwm2: PD_LSIO_PWM_2 { 362 pd_lsio_pwm2: PD_LSIO_PWM_2 {
347 reg = <SC_R_PWM_2>; 363 reg = <SC_R_PWM_2>;
348 #power-domain-cells = <0>; 364 #power-domain-cells = <0>;
349 power-domains = <&pd_lsio>; 365 power-domains = <&pd_lsio>;
350 }; 366 };
351 pd_lsio_pwm3: PD_LSIO_PWM_3 { 367 pd_lsio_pwm3: PD_LSIO_PWM_3 {
352 reg = <SC_R_PWM_3>; 368 reg = <SC_R_PWM_3>;
353 #power-domain-cells = <0>; 369 #power-domain-cells = <0>;
354 power-domains = <&pd_lsio>; 370 power-domains = <&pd_lsio>;
355 }; 371 };
356 pd_lsio_pwm4: PD_LSIO_PWM_4 { 372 pd_lsio_pwm4: PD_LSIO_PWM_4 {
357 reg = <SC_R_PWM_4>; 373 reg = <SC_R_PWM_4>;
358 #power-domain-cells = <0>; 374 #power-domain-cells = <0>;
359 power-domains = <&pd_lsio>; 375 power-domains = <&pd_lsio>;
360 }; 376 };
361 pd_lsio_pwm5: PD_LSIO_PWM_5 { 377 pd_lsio_pwm5: PD_LSIO_PWM_5 {
362 reg = <SC_R_PWM_5>; 378 reg = <SC_R_PWM_5>;
363 #power-domain-cells = <0>; 379 #power-domain-cells = <0>;
364 power-domains = <&pd_lsio>; 380 power-domains = <&pd_lsio>;
365 }; 381 };
366 pd_lsio_pwm6: PD_LSIO_PWM_6 { 382 pd_lsio_pwm6: PD_LSIO_PWM_6 {
367 reg = <SC_R_PWM_6>; 383 reg = <SC_R_PWM_6>;
368 #power-domain-cells = <0>; 384 #power-domain-cells = <0>;
369 power-domains = <&pd_lsio>; 385 power-domains = <&pd_lsio>;
370 }; 386 };
371 pd_lsio_pwm7: PD_LSIO_PWM_7 { 387 pd_lsio_pwm7: PD_LSIO_PWM_7 {
372 reg = <SC_R_PWM_7>; 388 reg = <SC_R_PWM_7>;
373 #power-domain-cells = <0>; 389 #power-domain-cells = <0>;
374 power-domains = <&pd_lsio>; 390 power-domains = <&pd_lsio>;
375 }; 391 };
376 pd_lsio_kpp: PD_LSIO_KPP { 392 pd_lsio_kpp: PD_LSIO_KPP {
377 reg = <SC_R_KPP>; 393 reg = <SC_R_KPP>;
378 #power-domain-cells = <0>; 394 #power-domain-cells = <0>;
379 power-domains = <&pd_lsio>; 395 power-domains = <&pd_lsio>;
380 }; 396 };
381 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 397 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
382 reg = <SC_R_GPIO_0>; 398 reg = <SC_R_GPIO_0>;
383 #power-domain-cells = <0>; 399 #power-domain-cells = <0>;
384 power-domains = <&pd_lsio>; 400 power-domains = <&pd_lsio>;
385 }; 401 };
386 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 402 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
387 reg = <SC_R_GPIO_1>; 403 reg = <SC_R_GPIO_1>;
388 #power-domain-cells = <0>; 404 #power-domain-cells = <0>;
389 power-domains = <&pd_lsio>; 405 power-domains = <&pd_lsio>;
390 }; 406 };
391 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 407 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
392 reg = <SC_R_GPIO_2>; 408 reg = <SC_R_GPIO_2>;
393 #power-domain-cells = <0>; 409 #power-domain-cells = <0>;
394 power-domains = <&pd_lsio>; 410 power-domains = <&pd_lsio>;
395 }; 411 };
396 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 412 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
397 reg = <SC_R_GPIO_3>; 413 reg = <SC_R_GPIO_3>;
398 #power-domain-cells = <0>; 414 #power-domain-cells = <0>;
399 power-domains = <&pd_lsio>; 415 power-domains = <&pd_lsio>;
400 }; 416 };
401 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 417 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
402 reg = <SC_R_GPIO_4>; 418 reg = <SC_R_GPIO_4>;
403 #power-domain-cells = <0>; 419 #power-domain-cells = <0>;
404 power-domains = <&pd_lsio>; 420 power-domains = <&pd_lsio>;
405 }; 421 };
406 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 422 pd_lsio_gpio5: PD_LSIO_GPIO_5{
407 reg = <SC_R_GPIO_5>; 423 reg = <SC_R_GPIO_5>;
408 #power-domain-cells = <0>; 424 #power-domain-cells = <0>;
409 power-domains = <&pd_lsio>; 425 power-domains = <&pd_lsio>;
410 }; 426 };
411 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 427 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
412 reg = <SC_R_GPIO_6>; 428 reg = <SC_R_GPIO_6>;
413 #power-domain-cells = <0>; 429 #power-domain-cells = <0>;
414 power-domains = <&pd_lsio>; 430 power-domains = <&pd_lsio>;
415 }; 431 };
416 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 432 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
417 reg = <SC_R_GPIO_7>; 433 reg = <SC_R_GPIO_7>;
418 #power-domain-cells = <0>; 434 #power-domain-cells = <0>;
419 power-domains = <&pd_lsio>; 435 power-domains = <&pd_lsio>;
420 }; 436 };
421 pd_lsio_gpt0: PD_LSIO_GPT_0 { 437 pd_lsio_gpt0: PD_LSIO_GPT_0 {
422 reg = <SC_R_GPT_0>; 438 reg = <SC_R_GPT_0>;
423 #power-domain-cells = <0>; 439 #power-domain-cells = <0>;
424 power-domains = <&pd_lsio>; 440 power-domains = <&pd_lsio>;
425 }; 441 };
426 pd_lsio_gpt1: PD_LSIO_GPT_1 { 442 pd_lsio_gpt1: PD_LSIO_GPT_1 {
427 reg = <SC_R_GPT_1>; 443 reg = <SC_R_GPT_1>;
428 #power-domain-cells = <0>; 444 #power-domain-cells = <0>;
429 power-domains = <&pd_lsio>; 445 power-domains = <&pd_lsio>;
430 }; 446 };
431 pd_lsio_gpt2: PD_LSIO_GPT_2 { 447 pd_lsio_gpt2: PD_LSIO_GPT_2 {
432 reg = <SC_R_GPT_2>; 448 reg = <SC_R_GPT_2>;
433 #power-domain-cells = <0>; 449 #power-domain-cells = <0>;
434 power-domains = <&pd_lsio>; 450 power-domains = <&pd_lsio>;
435 }; 451 };
436 pd_lsio_gpt3: PD_LSIO_GPT_3 { 452 pd_lsio_gpt3: PD_LSIO_GPT_3 {
437 reg = <SC_R_GPT_3>; 453 reg = <SC_R_GPT_3>;
438 #power-domain-cells = <0>; 454 #power-domain-cells = <0>;
439 power-domains = <&pd_lsio>; 455 power-domains = <&pd_lsio>;
440 }; 456 };
441 pd_lsio_gpt4: PD_LSIO_GPT_4 { 457 pd_lsio_gpt4: PD_LSIO_GPT_4 {
442 reg = <SC_R_GPT_4>; 458 reg = <SC_R_GPT_4>;
443 #power-domain-cells = <0>; 459 #power-domain-cells = <0>;
444 power-domains = <&pd_lsio>; 460 power-domains = <&pd_lsio>;
445 }; 461 };
446 pd_lsio_flexspi0: PD_LSIO_FSPI_0 { 462 pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
447 reg = <SC_R_FSPI_0>; 463 reg = <SC_R_FSPI_0>;
448 #power-domain-cells = <0>; 464 #power-domain-cells = <0>;
449 power-domains = <&pd_lsio>; 465 power-domains = <&pd_lsio>;
450 }; 466 };
451 pd_lsio_flexspi1: PD_LSIO_FSPI_1{ 467 pd_lsio_flexspi1: PD_LSIO_FSPI_1{
452 reg = <SC_R_FSPI_1>; 468 reg = <SC_R_FSPI_1>;
469 #power-domain-cells = <0>;
470 power-domains = <&pd_lsio>;
471 };
472 pd_lsio_mu8a: PD_LSIO_MU8A {
473 reg = <SC_R_MU_8A>;
474 #power-domain-cells = <0>;
475 power-domains = <&pd_lsio>;
476 };
477 pd_lsio_mu9a: PD_LSIO_MU9A {
478 reg = <SC_R_MU_9A>;
453 #power-domain-cells = <0>; 479 #power-domain-cells = <0>;
454 power-domains = <&pd_lsio>; 480 power-domains = <&pd_lsio>;
455 }; 481 };
456 }; 482 };
457 483
458 pd_conn: PD_CONN { 484 pd_conn: PD_CONN {
459 compatible = "nxp,imx8-pd"; 485 compatible = "nxp,imx8-pd";
460 reg = <SC_R_LAST>; 486 reg = <SC_R_LAST>;
461 #power-domain-cells = <0>; 487 #power-domain-cells = <0>;
462 #address-cells = <1>; 488 #address-cells = <1>;
463 #size-cells = <0>; 489 #size-cells = <0>;
464 490
465 pd_conn_usbotg0: PD_CONN_USB_0 { 491 pd_conn_usbotg0: PD_CONN_USB_0 {
466 reg = <SC_R_USB_0>; 492 reg = <SC_R_USB_0>;
467 #power-domain-cells = <0>; 493 #power-domain-cells = <0>;
468 power-domains = <&pd_conn>; 494 power-domains = <&pd_conn>;
469 }; 495 };
470 496
471 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { 497 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
472 reg = <SC_R_USB_0_PHY>; 498 reg = <SC_R_USB_0_PHY>;
473 #power-domain-cells = <0>; 499 #power-domain-cells = <0>;
474 power-domains = <&pd_conn>; 500 power-domains = <&pd_conn>;
475 }; 501 };
476 502
477 pd_conn_usbotg1: PD_CONN_USB_1 { 503 pd_conn_usbotg1: PD_CONN_USB_1 {
478 reg = <SC_R_USB_1>; 504 reg = <SC_R_USB_1>;
479 #power-domain-cells = <0>; 505 #power-domain-cells = <0>;
480 power-domains = <&pd_conn>; 506 power-domains = <&pd_conn>;
481 }; 507 };
482 pd_conn_usb2: PD_CONN_USB_2 { 508 pd_conn_usb2: PD_CONN_USB_2 {
483 reg = <SC_R_USB_2>; 509 reg = <SC_R_USB_2>;
484 #power-domain-cells = <0>; 510 #power-domain-cells = <0>;
485 power-domains = <&pd_conn>; 511 power-domains = <&pd_conn>;
486 }; 512 };
487 pd_conn_usb2_phy: PD_CONN_USB_2_PHY { 513 pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
488 reg = <SC_R_USB_2_PHY>; 514 reg = <SC_R_USB_2_PHY>;
489 #power-domain-cells = <0>; 515 #power-domain-cells = <0>;
490 power-domains = <&pd_conn>; 516 power-domains = <&pd_conn>;
491 }; 517 };
492 pd_conn_sdch0: PD_CONN_SDHC_0 { 518 pd_conn_sdch0: PD_CONN_SDHC_0 {
493 reg = <SC_R_SDHC_0>; 519 reg = <SC_R_SDHC_0>;
494 #power-domain-cells = <0>; 520 #power-domain-cells = <0>;
495 power-domains = <&pd_conn>; 521 power-domains = <&pd_conn>;
496 }; 522 };
497 pd_conn_sdch1: PD_CONN_SDHC_1 { 523 pd_conn_sdch1: PD_CONN_SDHC_1 {
498 reg = <SC_R_SDHC_1>; 524 reg = <SC_R_SDHC_1>;
499 #power-domain-cells = <0>; 525 #power-domain-cells = <0>;
500 power-domains = <&pd_conn>; 526 power-domains = <&pd_conn>;
501 }; 527 };
502 pd_conn_sdch2: PD_CONN_SDHC_2 { 528 pd_conn_sdch2: PD_CONN_SDHC_2 {
503 reg = <SC_R_SDHC_2>; 529 reg = <SC_R_SDHC_2>;
504 #power-domain-cells = <0>; 530 #power-domain-cells = <0>;
505 power-domains = <&pd_conn>; 531 power-domains = <&pd_conn>;
506 }; 532 };
507 pd_conn_enet0: PD_CONN_ENET_0 { 533 pd_conn_enet0: PD_CONN_ENET_0 {
508 reg = <SC_R_ENET_0>; 534 reg = <SC_R_ENET_0>;
509 #power-domain-cells = <0>; 535 #power-domain-cells = <0>;
510 power-domains = <&pd_conn>; 536 power-domains = <&pd_conn>;
511 }; 537 };
512 pd_conn_enet1: PD_CONN_ENET_1 { 538 pd_conn_enet1: PD_CONN_ENET_1 {
513 reg = <SC_R_ENET_1>; 539 reg = <SC_R_ENET_1>;
514 #power-domain-cells = <0>; 540 #power-domain-cells = <0>;
515 power-domains = <&pd_conn>; 541 power-domains = <&pd_conn>;
516 }; 542 };
517 pd_conn_nand: PD_CONN_NAND { 543 pd_conn_nand: PD_CONN_NAND {
518 reg = <SC_R_NAND>; 544 reg = <SC_R_NAND>;
519 #power-domain-cells = <0>; 545 #power-domain-cells = <0>;
520 power-domains = <&pd_conn>; 546 power-domains = <&pd_conn>;
521 }; 547 };
522 pd_conn_mlb0: PD_CONN_MLB_0 { 548 pd_conn_mlb0: PD_CONN_MLB_0 {
523 reg = <SC_R_MLB_0>; 549 reg = <SC_R_MLB_0>;
524 #power-domain-cells = <0>; 550 #power-domain-cells = <0>;
525 power-domains = <&pd_conn>; 551 power-domains = <&pd_conn>;
526 }; 552 };
527 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { 553 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
528 reg = <SC_R_DMA_4_CH0>; 554 reg = <SC_R_DMA_4_CH0>;
529 #power-domain-cells = <0>; 555 #power-domain-cells = <0>;
530 power-domains =<&pd_conn>; 556 power-domains =<&pd_conn>;
531 }; 557 };
532 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { 558 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
533 reg = <SC_R_DMA_4_CH1>; 559 reg = <SC_R_DMA_4_CH1>;
534 #power-domain-cells = <0>; 560 #power-domain-cells = <0>;
535 power-domains =<&pd_conn>; 561 power-domains =<&pd_conn>;
536 }; 562 };
537 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { 563 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
538 reg = <SC_R_DMA_4_CH2>; 564 reg = <SC_R_DMA_4_CH2>;
539 #power-domain-cells = <0>; 565 #power-domain-cells = <0>;
540 power-domains =<&pd_conn>; 566 power-domains =<&pd_conn>;
541 }; 567 };
542 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { 568 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
543 reg = <SC_R_DMA_4_CH3>; 569 reg = <SC_R_DMA_4_CH3>;
544 #power-domain-cells = <0>; 570 #power-domain-cells = <0>;
545 power-domains =<&pd_conn>; 571 power-domains =<&pd_conn>;
546 }; 572 };
547 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { 573 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
548 reg = <SC_R_DMA_4_CH4>; 574 reg = <SC_R_DMA_4_CH4>;
549 #power-domain-cells = <0>; 575 #power-domain-cells = <0>;
550 power-domains =<&pd_conn>; 576 power-domains =<&pd_conn>;
551 }; 577 };
552 }; 578 };
553 579
554 pd_hsio: PD_HSIO { 580 pd_hsio: PD_HSIO {
555 compatible = "nxp,imx8-pd"; 581 compatible = "nxp,imx8-pd";
556 reg = <SC_R_LAST>; 582 reg = <SC_R_LAST>;
557 #power-domain-cells = <0>; 583 #power-domain-cells = <0>;
558 #address-cells = <1>; 584 #address-cells = <1>;
559 #size-cells = <0>; 585 #size-cells = <0>;
560 586
561 pd_serdes0: PD_HSIO_SERDES_0 { 587 pd_serdes0: PD_HSIO_SERDES_0 {
562 reg = <SC_R_SERDES_0>; 588 reg = <SC_R_SERDES_0>;
563 #power-domain-cells = <0>; 589 #power-domain-cells = <0>;
564 power-domains =<&pd_hsio>; 590 power-domains =<&pd_hsio>;
565 #address-cells = <1>; 591 #address-cells = <1>;
566 #size-cells = <0>; 592 #size-cells = <0>;
567 593
568 pd_pcie0: PD_HSIO_PCIE_A { 594 pd_pcie0: PD_HSIO_PCIE_A {
569 reg = <SC_R_PCIE_A>; 595 reg = <SC_R_PCIE_A>;
570 #power-domain-cells = <0>; 596 #power-domain-cells = <0>;
571 power-domains =<&pd_serdes0>; 597 power-domains =<&pd_serdes0>;
572 }; 598 };
573 pd_pcie1: PD_HSIO_PCIE_B { 599 pd_pcie1: PD_HSIO_PCIE_B {
574 reg = <SC_R_PCIE_B>; 600 reg = <SC_R_PCIE_B>;
575 #power-domain-cells = <0>; 601 #power-domain-cells = <0>;
576 power-domains =<&pd_serdes0>; 602 power-domains =<&pd_serdes0>;
577 }; 603 };
578 }; 604 };
579 pd_serdes1: PD_HSIO_SERDES_1 { 605 pd_serdes1: PD_HSIO_SERDES_1 {
580 reg = <SC_R_SERDES_1>; 606 reg = <SC_R_SERDES_1>;
581 #power-domain-cells = <0>; 607 #power-domain-cells = <0>;
582 power-domains =<&pd_hsio>; 608 power-domains =<&pd_hsio>;
583 #address-cells = <1>; 609 #address-cells = <1>;
584 #size-cells = <0>; 610 #size-cells = <0>;
585 611
586 pd_sata0: PD_HSIO_SATA_0 { 612 pd_sata0: PD_HSIO_SATA_0 {
587 reg = <SC_R_SATA_0>; 613 reg = <SC_R_SATA_0>;
588 #power-domain-cells = <0>; 614 #power-domain-cells = <0>;
589 power-domains =<&pd_serdes1>; 615 power-domains =<&pd_serdes1>;
590 }; 616 };
591 }; 617 };
592 pd_gpio: PD_HSIO_GPIO { 618 pd_gpio: PD_HSIO_GPIO {
593 reg = <SC_R_HSIO_GPIO>; 619 reg = <SC_R_HSIO_GPIO>;
594 #power-domain-cells = <0>; 620 #power-domain-cells = <0>;
595 power-domains =<&pd_hsio>; 621 power-domains =<&pd_hsio>;
596 }; 622 };
597 }; 623 };
598 624
599 pd_audio: PD_AUDIO { 625 pd_audio: PD_AUDIO {
600 compatible = "nxp,imx8-pd"; 626 compatible = "nxp,imx8-pd";
601 reg = <SC_R_LAST>; 627 reg = <SC_R_LAST>;
602 #power-domain-cells = <0>; 628 #power-domain-cells = <0>;
603 #address-cells = <1>; 629 #address-cells = <1>;
604 #size-cells = <0>; 630 #size-cells = <0>;
605 631
606 pd_asrc0:PD_AUD_ASRC_0 { 632 pd_asrc0:PD_AUD_ASRC_0 {
607 reg = <SC_R_ASRC_0>; 633 reg = <SC_R_ASRC_0>;
608 #power-domain-cells = <0>; 634 #power-domain-cells = <0>;
609 power-domains =<&pd_audio>; 635 power-domains =<&pd_audio>;
610 }; 636 };
611 pd_asrc1: PD_AUD_ASRC_1 { 637 pd_asrc1: PD_AUD_ASRC_1 {
612 reg = <SC_R_ASRC_1>; 638 reg = <SC_R_ASRC_1>;
613 #power-domain-cells = <0>; 639 #power-domain-cells = <0>;
614 power-domains =<&pd_audio>; 640 power-domains =<&pd_audio>;
615 }; 641 };
616 pd_esai0: PD_AUD_ESAI_0 { 642 pd_esai0: PD_AUD_ESAI_0 {
617 reg = <SC_R_ESAI_0>; 643 reg = <SC_R_ESAI_0>;
618 #power-domain-cells = <0>; 644 #power-domain-cells = <0>;
619 power-domains =<&pd_audio>; 645 power-domains =<&pd_audio>;
620 }; 646 };
621 pd_esai1: PD_AUD_ESAI_1 { 647 pd_esai1: PD_AUD_ESAI_1 {
622 reg = <SC_R_ESAI_1>; 648 reg = <SC_R_ESAI_1>;
623 #power-domain-cells = <0>; 649 #power-domain-cells = <0>;
624 power-domains =<&pd_audio>; 650 power-domains =<&pd_audio>;
625 }; 651 };
626 pd_spdif0: PD_AUD_SPDIF_0 { 652 pd_spdif0: PD_AUD_SPDIF_0 {
627 reg = <SC_R_SPDIF_0>; 653 reg = <SC_R_SPDIF_0>;
628 #power-domain-cells = <0>; 654 #power-domain-cells = <0>;
629 power-domains =<&pd_audio>; 655 power-domains =<&pd_audio>;
630 }; 656 };
631 pd_spdif1: PD_AUD_SPDIF_1 { 657 pd_spdif1: PD_AUD_SPDIF_1 {
632 reg = <SC_R_SPDIF_1>; 658 reg = <SC_R_SPDIF_1>;
633 #power-domain-cells = <0>; 659 #power-domain-cells = <0>;
634 power-domains =<&pd_audio>; 660 power-domains =<&pd_audio>;
635 }; 661 };
636 pd_sai0:PD_AUD_SAI_0 { 662 pd_sai0:PD_AUD_SAI_0 {
637 reg = <SC_R_SAI_0>; 663 reg = <SC_R_SAI_0>;
638 #power-domain-cells = <0>; 664 #power-domain-cells = <0>;
639 power-domains =<&pd_audio>; 665 power-domains =<&pd_audio>;
640 }; 666 };
641 pd_sai1: PD_AUD_SAI_1 { 667 pd_sai1: PD_AUD_SAI_1 {
642 reg = <SC_R_SAI_1>; 668 reg = <SC_R_SAI_1>;
643 #power-domain-cells = <0>; 669 #power-domain-cells = <0>;
644 power-domains =<&pd_audio>; 670 power-domains =<&pd_audio>;
645 }; 671 };
646 pd_sai2: PD_AUD_SAI_2 { 672 pd_sai2: PD_AUD_SAI_2 {
647 reg = <SC_R_SAI_2>; 673 reg = <SC_R_SAI_2>;
648 #power-domain-cells = <0>; 674 #power-domain-cells = <0>;
649 power-domains =<&pd_audio>; 675 power-domains =<&pd_audio>;
650 }; 676 };
651 pd_sai3: PD_AUD_SAI_3 { 677 pd_sai3: PD_AUD_SAI_3 {
652 reg = <SC_R_SAI_3>; 678 reg = <SC_R_SAI_3>;
653 #power-domain-cells = <0>; 679 #power-domain-cells = <0>;
654 power-domains =<&pd_audio>; 680 power-domains =<&pd_audio>;
655 }; 681 };
656 pd_sai4: PD_AUD_SAI_4 { 682 pd_sai4: PD_AUD_SAI_4 {
657 reg = <SC_R_SAI_4>; 683 reg = <SC_R_SAI_4>;
658 #power-domain-cells = <0>; 684 #power-domain-cells = <0>;
659 power-domains =<&pd_audio>; 685 power-domains =<&pd_audio>;
660 }; 686 };
661 pd_sai5: PD_AUD_SAI_5 { 687 pd_sai5: PD_AUD_SAI_5 {
662 reg = <SC_R_SAI_5>; 688 reg = <SC_R_SAI_5>;
663 #power-domain-cells = <0>; 689 #power-domain-cells = <0>;
664 power-domains =<&pd_audio>; 690 power-domains =<&pd_audio>;
665 }; 691 };
666 pd_sai6: PD_AUD_SAI_6 { 692 pd_sai6: PD_AUD_SAI_6 {
667 reg = <SC_R_SAI_6>; 693 reg = <SC_R_SAI_6>;
668 #power-domain-cells = <0>; 694 #power-domain-cells = <0>;
669 power-domains =<&pd_audio>; 695 power-domains =<&pd_audio>;
670 }; 696 };
671 pd_sai7: PD_AUD_SAI_7 { 697 pd_sai7: PD_AUD_SAI_7 {
672 reg = <SC_R_SAI_7>; 698 reg = <SC_R_SAI_7>;
673 #power-domain-cells = <0>; 699 #power-domain-cells = <0>;
674 power-domains =<&pd_audio>; 700 power-domains =<&pd_audio>;
675 }; 701 };
676 pd_gpt5: PD_AUD_GPT_5 { 702 pd_gpt5: PD_AUD_GPT_5 {
677 reg = <SC_R_GPT_5>; 703 reg = <SC_R_GPT_5>;
678 #power-domain-cells = <0>; 704 #power-domain-cells = <0>;
679 power-domains =<&pd_audio>; 705 power-domains =<&pd_audio>;
680 }; 706 };
681 pd_gpt6: PD_AUD_GPT_6 { 707 pd_gpt6: PD_AUD_GPT_6 {
682 reg = <SC_R_GPT_6>; 708 reg = <SC_R_GPT_6>;
683 #power-domain-cells = <0>; 709 #power-domain-cells = <0>;
684 power-domains =<&pd_audio>; 710 power-domains =<&pd_audio>;
685 }; 711 };
686 pd_gpt7: PD_AUD_GPT_7 { 712 pd_gpt7: PD_AUD_GPT_7 {
687 reg = <SC_R_GPT_7>; 713 reg = <SC_R_GPT_7>;
688 #power-domain-cells = <0>; 714 #power-domain-cells = <0>;
689 power-domains =<&pd_audio>; 715 power-domains =<&pd_audio>;
690 }; 716 };
691 pd_gpt8: PD_AUD_GPT_8 { 717 pd_gpt8: PD_AUD_GPT_8 {
692 reg = <SC_R_GPT_8>; 718 reg = <SC_R_GPT_8>;
693 #power-domain-cells = <0>; 719 #power-domain-cells = <0>;
694 power-domains =<&pd_audio>; 720 power-domains =<&pd_audio>;
695 }; 721 };
696 pd_gpt9: PD_AUD_GPT_9 { 722 pd_gpt9: PD_AUD_GPT_9 {
697 reg = <SC_R_GPT_9>; 723 reg = <SC_R_GPT_9>;
698 #power-domain-cells = <0>; 724 #power-domain-cells = <0>;
699 power-domains =<&pd_audio>; 725 power-domains =<&pd_audio>;
700 }; 726 };
701 pd_gpt10: PD_AUD_GPT_10 { 727 pd_gpt10: PD_AUD_GPT_10 {
702 reg = <SC_R_GPT_10>; 728 reg = <SC_R_GPT_10>;
703 #power-domain-cells = <0>; 729 #power-domain-cells = <0>;
704 power-domains =<&pd_audio>; 730 power-domains =<&pd_audio>;
705 }; 731 };
706 pd_amix: PD_AUD_AMIX { 732 pd_amix: PD_AUD_AMIX {
707 reg = <SC_R_AMIX>; 733 reg = <SC_R_AMIX>;
708 #power-domain-cells = <0>; 734 #power-domain-cells = <0>;
709 power-domains =<&pd_audio>; 735 power-domains =<&pd_audio>;
710 }; 736 };
711 pd_mqs0: PD_AUD_MQS_0 { 737 pd_mqs0: PD_AUD_MQS_0 {
712 reg = <SC_R_MQS_0>; 738 reg = <SC_R_MQS_0>;
713 #power-domain-cells = <0>; 739 #power-domain-cells = <0>;
714 power-domains =<&pd_audio>; 740 power-domains =<&pd_audio>;
715 }; 741 };
716 pd_mclk_out0: PD_AUD_MCLK_OUT_0 { 742 pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
717 reg = <SC_R_MCLK_OUT_0>; 743 reg = <SC_R_MCLK_OUT_0>;
718 #power-domain-cells = <0>; 744 #power-domain-cells = <0>;
719 power-domains =<&pd_audio>; 745 power-domains =<&pd_audio>;
720 }; 746 };
721 pd_mclk_out1: PD_AUD_MCLK_OUT_1 { 747 pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
722 reg = <SC_R_MCLK_OUT_1>; 748 reg = <SC_R_MCLK_OUT_1>;
723 #power-domain-cells = <0>; 749 #power-domain-cells = <0>;
724 power-domains =<&pd_audio>; 750 power-domains =<&pd_audio>;
725 }; 751 };
726 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { 752 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
727 reg = <SC_R_AUDIO_PLL_0>; 753 reg = <SC_R_AUDIO_PLL_0>;
728 #power-domain-cells = <0>; 754 #power-domain-cells = <0>;
729 power-domains =<&pd_audio>; 755 power-domains =<&pd_audio>;
730 }; 756 };
731 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { 757 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
732 reg = <SC_R_AUDIO_PLL_1>; 758 reg = <SC_R_AUDIO_PLL_1>;
733 #power-domain-cells = <0>; 759 #power-domain-cells = <0>;
734 power-domains =<&pd_audio>; 760 power-domains =<&pd_audio>;
735 }; 761 };
736 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { 762 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
737 reg = <SC_R_AUDIO_CLK_0>; 763 reg = <SC_R_AUDIO_CLK_0>;
738 #power-domain-cells = <0>; 764 #power-domain-cells = <0>;
739 power-domains =<&pd_audio>; 765 power-domains =<&pd_audio>;
740 }; 766 };
741 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { 767 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
742 reg = <SC_R_AUDIO_CLK_1>; 768 reg = <SC_R_AUDIO_CLK_1>;
743 #power-domain-cells = <0>; 769 #power-domain-cells = <0>;
744 power-domains =<&pd_audio>; 770 power-domains =<&pd_audio>;
745 }; 771 };
746 }; 772 };
747 773
748 pd_dma: PD_DMA { 774 pd_dma: PD_DMA {
749 compatible = "nxp,imx8-pd"; 775 compatible = "nxp,imx8-pd";
750 reg = <SC_R_LAST>; 776 reg = <SC_R_LAST>;
751 #power-domain-cells = <0>; 777 #power-domain-cells = <0>;
752 #address-cells = <1>; 778 #address-cells = <1>;
753 #size-cells = <0>; 779 #size-cells = <0>;
754 780
755 pd_dma_flexcan0: PD_DMA_CAN_0 { 781 pd_dma_flexcan0: PD_DMA_CAN_0 {
756 reg = <SC_R_CAN_0>; 782 reg = <SC_R_CAN_0>;
757 #power-domain-cells = <0>; 783 #power-domain-cells = <0>;
758 power-domains = <&pd_dma>; 784 power-domains = <&pd_dma>;
759 }; 785 };
760 pd_dma_flexcan1: PD_DMA_CAN_1 { 786 pd_dma_flexcan1: PD_DMA_CAN_1 {
761 reg = <SC_R_CAN_1>; 787 reg = <SC_R_CAN_1>;
762 #power-domain-cells = <0>; 788 #power-domain-cells = <0>;
763 power-domains = <&pd_dma>; 789 power-domains = <&pd_dma>;
764 }; 790 };
765 pd_dma_flexcan2: PD_DMA_CAN_2 { 791 pd_dma_flexcan2: PD_DMA_CAN_2 {
766 reg = <SC_R_CAN_2>; 792 reg = <SC_R_CAN_2>;
767 #power-domain-cells = <0>; 793 #power-domain-cells = <0>;
768 power-domains = <&pd_dma>; 794 power-domains = <&pd_dma>;
769 }; 795 };
770 pd_dma_ftm0: PD_DMA_FTM_0 { 796 pd_dma_ftm0: PD_DMA_FTM_0 {
771 reg = <SC_R_FTM_0>; 797 reg = <SC_R_FTM_0>;
772 #power-domain-cells = <0>; 798 #power-domain-cells = <0>;
773 power-domains = <&pd_dma>; 799 power-domains = <&pd_dma>;
774 }; 800 };
775 pd_dma_ftm1: PD_DMA_FTM_1 { 801 pd_dma_ftm1: PD_DMA_FTM_1 {
776 reg = <SC_R_FTM_1>; 802 reg = <SC_R_FTM_1>;
777 #power-domain-cells = <0>; 803 #power-domain-cells = <0>;
778 power-domains = <&pd_dma>; 804 power-domains = <&pd_dma>;
779 }; 805 };
780 pd_dma_adc0: PD_DMA_ADC_0 { 806 pd_dma_adc0: PD_DMA_ADC_0 {
781 reg = <SC_R_ADC_0>; 807 reg = <SC_R_ADC_0>;
782 #power-domain-cells = <0>; 808 #power-domain-cells = <0>;
783 power-domains = <&pd_dma>; 809 power-domains = <&pd_dma>;
784 }; 810 };
785 pd_dma_adc1: PD_DMA_ADC_1 { 811 pd_dma_adc1: PD_DMA_ADC_1 {
786 reg = <SC_R_ADC_1>; 812 reg = <SC_R_ADC_1>;
787 #power-domain-cells = <0>; 813 #power-domain-cells = <0>;
788 power-domains = <&pd_dma>; 814 power-domains = <&pd_dma>;
789 }; 815 };
790 pd_dma_lpi2c0: PD_DMA_I2C_0 { 816 pd_dma_lpi2c0: PD_DMA_I2C_0 {
791 reg = <SC_R_I2C_0>; 817 reg = <SC_R_I2C_0>;
792 #power-domain-cells = <0>; 818 #power-domain-cells = <0>;
793 power-domains = <&pd_dma>; 819 power-domains = <&pd_dma>;
794 }; 820 };
795 pd_dma_lpi2c1: PD_DMA_I2C_1 { 821 pd_dma_lpi2c1: PD_DMA_I2C_1 {
796 reg = <SC_R_I2C_1>; 822 reg = <SC_R_I2C_1>;
797 #power-domain-cells = <0>; 823 #power-domain-cells = <0>;
798 power-domains = <&pd_dma>; 824 power-domains = <&pd_dma>;
799 }; 825 };
800 pd_dma_lpi2c2:PD_DMA_I2C_2 { 826 pd_dma_lpi2c2:PD_DMA_I2C_2 {
801 reg = <SC_R_I2C_2>; 827 reg = <SC_R_I2C_2>;
802 #power-domain-cells = <0>; 828 #power-domain-cells = <0>;
803 power-domains = <&pd_dma>; 829 power-domains = <&pd_dma>;
804 }; 830 };
805 pd_dma_lpi2c3: PD_DMA_I2C_3 { 831 pd_dma_lpi2c3: PD_DMA_I2C_3 {
806 reg = <SC_R_I2C_3>; 832 reg = <SC_R_I2C_3>;
807 #power-domain-cells = <0>; 833 #power-domain-cells = <0>;
808 power-domains = <&pd_dma>; 834 power-domains = <&pd_dma>;
809 }; 835 };
810 pd_dma_lpi2c4: PD_DMA_I2C_4 { 836 pd_dma_lpi2c4: PD_DMA_I2C_4 {
811 reg = <SC_R_I2C_4>; 837 reg = <SC_R_I2C_4>;
812 #power-domain-cells = <0>; 838 #power-domain-cells = <0>;
813 power-domains = <&pd_dma>; 839 power-domains = <&pd_dma>;
814 }; 840 };
815 pd_dma_lpuart0: PD_DMA_UART0 { 841 pd_dma_lpuart0: PD_DMA_UART0 {
816 reg = <SC_R_UART_0>; 842 reg = <SC_R_UART_0>;
817 #power-domain-cells = <0>; 843 #power-domain-cells = <0>;
818 power-domains = <&pd_dma>; 844 power-domains = <&pd_dma>;
819 }; 845 };
820 pd_dma_lpuart1: PD_DMA_UART1 { 846 pd_dma_lpuart1: PD_DMA_UART1 {
821 reg = <SC_R_UART_1>; 847 reg = <SC_R_UART_1>;
822 #power-domain-cells = <0>; 848 #power-domain-cells = <0>;
823 power-domains = <&pd_dma>; 849 power-domains = <&pd_dma>;
824 }; 850 };
825 pd_dma_lpuart2: PD_DMA_UART2 { 851 pd_dma_lpuart2: PD_DMA_UART2 {
826 reg = <SC_R_UART_2>; 852 reg = <SC_R_UART_2>;
827 #power-domain-cells = <0>; 853 #power-domain-cells = <0>;
828 power-domains = <&pd_dma>; 854 power-domains = <&pd_dma>;
829 }; 855 };
830 pd_dma_lpuart3: PD_DMA_UART3 { 856 pd_dma_lpuart3: PD_DMA_UART3 {
831 reg = <SC_R_UART_3>; 857 reg = <SC_R_UART_3>;
832 #power-domain-cells = <0>; 858 #power-domain-cells = <0>;
833 power-domains = <&pd_dma>; 859 power-domains = <&pd_dma>;
834 }; 860 };
835 pd_dma_lpuart4: PD_DMA_UART4 { 861 pd_dma_lpuart4: PD_DMA_UART4 {
836 reg = <SC_R_UART_4>; 862 reg = <SC_R_UART_4>;
837 #power-domain-cells = <0>; 863 #power-domain-cells = <0>;
838 power-domains = <&pd_dma>; 864 power-domains = <&pd_dma>;
839 }; 865 };
840 pd_dma_lpspi0: PD_DMA_SPI_0 { 866 pd_dma_lpspi0: PD_DMA_SPI_0 {
841 reg = <SC_R_SPI_0>; 867 reg = <SC_R_SPI_0>;
842 #power-domain-cells = <0>; 868 #power-domain-cells = <0>;
843 power-domains = <&pd_dma>; 869 power-domains = <&pd_dma>;
844 }; 870 };
845 pd_dma_lpspi1: PD_DMA_SPI_1 { 871 pd_dma_lpspi1: PD_DMA_SPI_1 {
846 reg = <SC_R_SPI_1>; 872 reg = <SC_R_SPI_1>;
847 #power-domain-cells = <0>; 873 #power-domain-cells = <0>;
848 power-domains = <&pd_dma>; 874 power-domains = <&pd_dma>;
849 }; 875 };
850 pd_dma_lpspi2: PD_DMA_SPI_2 { 876 pd_dma_lpspi2: PD_DMA_SPI_2 {
851 reg = <SC_R_SPI_2>; 877 reg = <SC_R_SPI_2>;
852 #power-domain-cells = <0>; 878 #power-domain-cells = <0>;
853 power-domains = <&pd_dma>; 879 power-domains = <&pd_dma>;
854 }; 880 };
855 pd_dma_lpspi3: PD_DMA_SPI_3 { 881 pd_dma_lpspi3: PD_DMA_SPI_3 {
856 reg = <SC_R_SPI_3>; 882 reg = <SC_R_SPI_3>;
857 #power-domain-cells = <0>; 883 #power-domain-cells = <0>;
858 power-domains = <&pd_dma>; 884 power-domains = <&pd_dma>;
859 }; 885 };
860 pd_dma_emvsim0: PD_DMA_EMVSIM_0 { 886 pd_dma_emvsim0: PD_DMA_EMVSIM_0 {
861 reg = <SC_R_EMVSIM_0>; 887 reg = <SC_R_EMVSIM_0>;
862 #power-domain-cells = <0>; 888 #power-domain-cells = <0>;
863 power-domains = <&pd_dma>; 889 power-domains = <&pd_dma>;
864 }; 890 };
865 pd_dma_emvsim1: PD_DMA_EMVSIM_1 { 891 pd_dma_emvsim1: PD_DMA_EMVSIM_1 {
866 reg = <SC_R_EMVSIM_1>; 892 reg = <SC_R_EMVSIM_1>;
867 #power-domain-cells = <0>; 893 #power-domain-cells = <0>;
868 power-domains = <&pd_dma>; 894 power-domains = <&pd_dma>;
869 }; 895 };
870 }; 896 };
871 pd_gpu: PD_GPU { 897 pd_gpu: PD_GPU {
872 compatible = "nxp,imx8-pd"; 898 compatible = "nxp,imx8-pd";
873 reg = <SC_R_LAST>; 899 reg = <SC_R_LAST>;
874 #power-domain-cells = <0>; 900 #power-domain-cells = <0>;
875 #address-cells = <1>; 901 #address-cells = <1>;
876 #size-cells = <0>; 902 #size-cells = <0>;
877 903
878 pd_gpu0: PD_GPU0 { 904 pd_gpu0: PD_GPU0 {
879 reg = <SC_R_GPU_0_PID0>; 905 reg = <SC_R_GPU_0_PID0>;
880 #power-domain-cells = <0>; 906 #power-domain-cells = <0>;
881 power-domains =<&pd_gpu>; 907 power-domains =<&pd_gpu>;
882 }; 908 };
883 pd_gpu1: PD_GPU1 { 909 pd_gpu1: PD_GPU1 {
884 reg = <SC_R_GPU_1_PID0>; 910 reg = <SC_R_GPU_1_PID0>;
885 #power-domain-cells = <0>; 911 #power-domain-cells = <0>;
886 power-domains =<&pd_gpu>; 912 power-domains =<&pd_gpu>;
887 }; 913 };
888 }; 914 };
889 915
890 pd_vpu: PD_VPU { 916 pd_vpu: PD_VPU {
891 compatible = "nxp,imx8-pd"; 917 compatible = "nxp,imx8-pd";
892 reg = <SC_R_VPU>; 918 reg = <SC_R_VPU>;
893 #power-domain-cells = <0>; 919 #power-domain-cells = <0>;
894 #address-cells = <1>; 920 #address-cells = <1>;
895 #size-cells = <0>; 921 #size-cells = <0>;
896 922
897 pd_vpu_core: VPU_CORE { 923 pd_vpu_core: VPU_CORE {
898 reg = <SC_R_VPUCORE>; 924 reg = <SC_R_VPUCORE>;
899 #power-domain-cells = <0>; 925 #power-domain-cells = <0>;
900 power-domains =<&pd_vpu>; 926 power-domains =<&pd_vpu>;
901 }; 927 };
902 928
903 pd_vpu_enc: VPU_ENC { 929 pd_vpu_enc: VPU_ENC {
904 reg = <SC_R_VPU_ENC_0>; 930 reg = <SC_R_VPU_ENC_0>;
905 #power-domain-cells = <0>; 931 #power-domain-cells = <0>;
906 power-domains =<&pd_vpu_core>; 932 power-domains =<&pd_vpu_core>;
907 }; 933 };
908 934
909 pd_vpu_dec: VPU_DEC { 935 pd_vpu_dec: VPU_DEC {
910 reg = <SC_R_VPU_DEC_0>; 936 reg = <SC_R_VPU_DEC_0>;
911 #power-domain-cells = <0>; 937 #power-domain-cells = <0>;
912 power-domains =<&pd_vpu_core>; 938 power-domains =<&pd_vpu_core>;
913 }; 939 };
914 }; 940 };
915 941
916 pd_isi_ch0: PD_IMAGING { 942 pd_isi_ch0: PD_IMAGING {
917 compatible = "nxp,imx8-pd"; 943 compatible = "nxp,imx8-pd";
918 reg = <SC_R_ISI_CH0>; 944 reg = <SC_R_ISI_CH0>;
919 #power-domain-cells = <0>; 945 #power-domain-cells = <0>;
920 #address-cells = <1>; 946 #address-cells = <1>;
921 #size-cells = <0>; 947 #size-cells = <0>;
922 948
923 pd_csi0: PD_MIPI_CSI0 { 949 pd_csi0: PD_MIPI_CSI0 {
924 reg = <SC_R_CSI_0>; 950 reg = <SC_R_CSI_0>;
925 #power-domain-cells = <0>; 951 #power-domain-cells = <0>;
926 power-domains =<&pd_isi_ch0>; 952 power-domains =<&pd_isi_ch0>;
927 #address-cells = <1>; 953 #address-cells = <1>;
928 #size-cells = <0>; 954 #size-cells = <0>;
929 955
930 pd_csi0_i2c0: PD_MIPI_CSI0_I2C { 956 pd_csi0_i2c0: PD_MIPI_CSI0_I2C {
931 reg = <SC_R_CSI_0_I2C_0>; 957 reg = <SC_R_CSI_0_I2C_0>;
932 #power-domain-cells = <0>; 958 #power-domain-cells = <0>;
933 power-domains =<&pd_csi0>; 959 power-domains =<&pd_csi0>;
934 }; 960 };
935 961
936 pd_csi0_pwm: PD_MIPI_CSI0_PWM { 962 pd_csi0_pwm: PD_MIPI_CSI0_PWM {
937 reg = <SC_R_CSI_0_PWM_0>; 963 reg = <SC_R_CSI_0_PWM_0>;
938 #power-domain-cells = <0>; 964 #power-domain-cells = <0>;
939 power-domains =<&pd_csi0>; 965 power-domains =<&pd_csi0>;
940 }; 966 };
941 }; 967 };
942 968
943 pd_csi1: PD_MIPI_CSI1 { 969 pd_csi1: PD_MIPI_CSI1 {
944 reg = <SC_R_CSI_1>; 970 reg = <SC_R_CSI_1>;
945 #power-domain-cells = <0>; 971 #power-domain-cells = <0>;
946 power-domains =<&pd_isi_ch0>; 972 power-domains =<&pd_isi_ch0>;
947 #address-cells = <1>; 973 #address-cells = <1>;
948 #size-cells = <0>; 974 #size-cells = <0>;
949 975
950 pd_csi1_i2c0: PD_MIPI_CSI1_I2C0 { 976 pd_csi1_i2c0: PD_MIPI_CSI1_I2C0 {
951 reg = <SC_R_CSI_1_I2C_0>; 977 reg = <SC_R_CSI_1_I2C_0>;
952 #power-domain-cells = <0>; 978 #power-domain-cells = <0>;
953 power-domains =<&pd_csi1>; 979 power-domains =<&pd_csi1>;
954 }; 980 };
955 981
956 pd_csi1_pwm: PD_MIPI_CSI1_PWM { 982 pd_csi1_pwm: PD_MIPI_CSI1_PWM {
957 reg = <SC_R_CSI_1_PWM_0>; 983 reg = <SC_R_CSI_1_PWM_0>;
958 #power-domain-cells = <0>; 984 #power-domain-cells = <0>;
959 power-domains =<&pd_csi1>; 985 power-domains =<&pd_csi1>;
960 }; 986 };
961 }; 987 };
962 988
963 pd_hdmi_rx: PD_HDMI_RX { 989 pd_hdmi_rx: PD_HDMI_RX {
964 reg = <SC_R_HDMI_RX>; 990 reg = <SC_R_HDMI_RX>;
965 #power-domain-cells = <0>; 991 #power-domain-cells = <0>;
966 power-domains =<&pd_isi_ch0>; 992 power-domains =<&pd_isi_ch0>;
967 #address-cells = <1>; 993 #address-cells = <1>;
968 #size-cells = <0>; 994 #size-cells = <0>;
969 995
970 pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C { 996 pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C {
971 reg = <SC_R_HDMI_RX_I2C_0>; 997 reg = <SC_R_HDMI_RX_I2C_0>;
972 #power-domain-cells = <0>; 998 #power-domain-cells = <0>;
973 power-domains =<&pd_hdmi_rx>; 999 power-domains =<&pd_hdmi_rx>;
974 }; 1000 };
975 }; 1001 };
976 1002
977 pd_isi_ch1: PD_IMAGING_PDMA1 { 1003 pd_isi_ch1: PD_IMAGING_PDMA1 {
978 reg = <SC_R_ISI_CH1>; 1004 reg = <SC_R_ISI_CH1>;
979 #power-domain-cells = <0>; 1005 #power-domain-cells = <0>;
980 power-domains =<&pd_isi_ch0>; 1006 power-domains =<&pd_isi_ch0>;
981 }; 1007 };
982 1008
983 pd_isi_ch2: PD_IMAGING_PDMA2 { 1009 pd_isi_ch2: PD_IMAGING_PDMA2 {
984 reg = <SC_R_ISI_CH2>; 1010 reg = <SC_R_ISI_CH2>;
985 #power-domain-cells = <0>; 1011 #power-domain-cells = <0>;
986 power-domains =<&pd_isi_ch0>; 1012 power-domains =<&pd_isi_ch0>;
987 }; 1013 };
988 1014
989 pd_isi_ch3: PD_IMAGING_PDMA3 { 1015 pd_isi_ch3: PD_IMAGING_PDMA3 {
990 reg = <SC_R_ISI_CH3>; 1016 reg = <SC_R_ISI_CH3>;
991 #power-domain-cells = <0>; 1017 #power-domain-cells = <0>;
992 power-domains =<&pd_isi_ch0>; 1018 power-domains =<&pd_isi_ch0>;
993 }; 1019 };
994 1020
995 pd_isi_ch4: PD_IMAGING_PDMA4 { 1021 pd_isi_ch4: PD_IMAGING_PDMA4 {
996 reg = <SC_R_ISI_CH4>; 1022 reg = <SC_R_ISI_CH4>;
997 #power-domain-cells = <0>; 1023 #power-domain-cells = <0>;
998 power-domains =<&pd_isi_ch0>; 1024 power-domains =<&pd_isi_ch0>;
999 }; 1025 };
1000 1026
1001 pd_isi_ch5: PD_IMAGING_PDMA5 { 1027 pd_isi_ch5: PD_IMAGING_PDMA5 {
1002 reg = <SC_R_ISI_CH5>; 1028 reg = <SC_R_ISI_CH5>;
1003 #power-domain-cells = <0>; 1029 #power-domain-cells = <0>;
1004 power-domains =<&pd_isi_ch0>; 1030 power-domains =<&pd_isi_ch0>;
1005 }; 1031 };
1006 1032
1007 pd_isi_ch6: PD_IMAGING_PDMA6 { 1033 pd_isi_ch6: PD_IMAGING_PDMA6 {
1008 reg = <SC_R_ISI_CH6>; 1034 reg = <SC_R_ISI_CH6>;
1009 #power-domain-cells = <0>; 1035 #power-domain-cells = <0>;
1010 power-domains =<&pd_isi_ch0>; 1036 power-domains =<&pd_isi_ch0>;
1011 }; 1037 };
1012 1038
1013 pd_isi_ch7: PD_IMAGING_PDMA7 { 1039 pd_isi_ch7: PD_IMAGING_PDMA7 {
1014 reg = <SC_R_ISI_CH7>; 1040 reg = <SC_R_ISI_CH7>;
1015 #power-domain-cells = <0>; 1041 #power-domain-cells = <0>;
1016 power-domains =<&pd_isi_ch0>; 1042 power-domains =<&pd_isi_ch0>;
1017 }; 1043 };
1018 }; 1044 };
1019 }; 1045 };
1020 1046
1021 tsens: thermal-sensor { 1047 tsens: thermal-sensor {
1022 compatible = "nxp,imx8qm-sc-tsens"; 1048 compatible = "nxp,imx8qm-sc-tsens";
1023 u-boot,dm-pre-reloc; 1049 u-boot,dm-pre-reloc;
1024 /* number of the temp sensor on the chip */ 1050 /* number of the temp sensor on the chip */
1025 tsens-num = <5>; 1051 tsens-num = <5>;
1026 #thermal-sensor-cells = <1>; 1052 #thermal-sensor-cells = <1>;
1027 }; 1053 };
1028 1054
1029 thermal-zones { 1055 thermal-zones {
1030 /* cpu thermal */ 1056 /* cpu thermal */
1031 cpu-thermal0 { 1057 cpu-thermal0 {
1032 polling-delay-passive = <250>; 1058 polling-delay-passive = <250>;
1033 polling-delay = <2000>; 1059 polling-delay = <2000>;
1034 /*the slope and offset of the temp sensor */ 1060 /*the slope and offset of the temp sensor */
1035 thermal-sensors = <&tsens 0>; 1061 thermal-sensors = <&tsens 0>;
1036 trips { 1062 trips {
1037 cpu_alert0: trip0 { 1063 cpu_alert0: trip0 {
1038 temperature = <107000>; 1064 temperature = <107000>;
1039 hysteresis = <2000>; 1065 hysteresis = <2000>;
1040 type = "passive"; 1066 type = "passive";
1041 }; 1067 };
1042 cpu_crit0: trip1 { 1068 cpu_crit0: trip1 {
1043 temperature = <127000>; 1069 temperature = <127000>;
1044 hysteresis = <2000>; 1070 hysteresis = <2000>;
1045 type = "critical"; 1071 type = "critical";
1046 }; 1072 };
1047 }; 1073 };
1048 }; 1074 };
1049 1075
1050 cpu-thermal1 { 1076 cpu-thermal1 {
1051 polling-delay-passive = <250>; 1077 polling-delay-passive = <250>;
1052 polling-delay = <2000>; 1078 polling-delay = <2000>;
1053 thermal-sensors = <&tsens 1>; 1079 thermal-sensors = <&tsens 1>;
1054 trips { 1080 trips {
1055 cpu_alert1: trip0 { 1081 cpu_alert1: trip0 {
1056 temperature = <107000>; 1082 temperature = <107000>;
1057 hysteresis = <2000>; 1083 hysteresis = <2000>;
1058 type = "passive"; 1084 type = "passive";
1059 }; 1085 };
1060 cpu_crit1: trip1 { 1086 cpu_crit1: trip1 {
1061 temperature = <127000>; 1087 temperature = <127000>;
1062 hysteresis = <2000>; 1088 hysteresis = <2000>;
1063 type = "critical"; 1089 type = "critical";
1064 }; 1090 };
1065 }; 1091 };
1066 }; 1092 };
1067 1093
1068 gpu-thermal0 { 1094 gpu-thermal0 {
1069 polling-delay-passive = <250>; 1095 polling-delay-passive = <250>;
1070 polling-delay = <2000>; 1096 polling-delay = <2000>;
1071 thermal-sensors = <&tsens 2>; 1097 thermal-sensors = <&tsens 2>;
1072 trips { 1098 trips {
1073 gpu_alert0: trip0 { 1099 gpu_alert0: trip0 {
1074 temperature = <107000>; 1100 temperature = <107000>;
1075 hysteresis = <2000>; 1101 hysteresis = <2000>;
1076 type = "passive"; 1102 type = "passive";
1077 }; 1103 };
1078 gpu_crit0: trip1 { 1104 gpu_crit0: trip1 {
1079 temperature = <127000>; 1105 temperature = <127000>;
1080 hysteresis = <2000>; 1106 hysteresis = <2000>;
1081 type = "critical"; 1107 type = "critical";
1082 }; 1108 };
1083 }; 1109 };
1084 }; 1110 };
1085 1111
1086 gpu-thermal1 { 1112 gpu-thermal1 {
1087 polling-delay-passive = <250>; 1113 polling-delay-passive = <250>;
1088 polling-delay = <2000>; 1114 polling-delay = <2000>;
1089 thermal-sensors = <&tsens 3>; 1115 thermal-sensors = <&tsens 3>;
1090 trips { 1116 trips {
1091 gpu_alert1: trip0 { 1117 gpu_alert1: trip0 {
1092 temperature = <107000>; 1118 temperature = <107000>;
1093 hysteresis = <2000>; 1119 hysteresis = <2000>;
1094 type = "passive"; 1120 type = "passive";
1095 }; 1121 };
1096 gpu_crit1: trip1 { 1122 gpu_crit1: trip1 {
1097 temperature = <127000>; 1123 temperature = <127000>;
1098 hysteresis = <2000>; 1124 hysteresis = <2000>;
1099 type = "critical"; 1125 type = "critical";
1100 }; 1126 };
1101 }; 1127 };
1102 }; 1128 };
1103 1129
1104 drc-thermal0 { 1130 drc-thermal0 {
1105 polling-delay-passive = <250>; 1131 polling-delay-passive = <250>;
1106 polling-delay = <2000>; 1132 polling-delay = <2000>;
1107 thermal-sensors = <&tsens 4>; 1133 thermal-sensors = <&tsens 4>;
1108 trips { 1134 trips {
1109 drc_alert0: trip0 { 1135 drc_alert0: trip0 {
1110 temperature = <107000>; 1136 temperature = <107000>;
1111 hysteresis = <2000>; 1137 hysteresis = <2000>;
1112 type = "passive"; 1138 type = "passive";
1113 }; 1139 };
1114 drc_crit0: trip1 { 1140 drc_crit0: trip1 {
1115 temperature = <127000>; 1141 temperature = <127000>;
1116 hysteresis = <2000>; 1142 hysteresis = <2000>;
1117 type = "critical"; 1143 type = "critical";
1118 }; 1144 };
1119 }; 1145 };
1120 }; 1146 };
1121 }; 1147 };
1122 1148
1123 rtc: rtc { 1149 rtc: rtc {
1124 compatible = "fsl,imx-sc-rtc"; 1150 compatible = "fsl,imx-sc-rtc";
1125 }; 1151 };
1126 1152
1127 dpu1_intsteer: dpu_intsteer@56000000 { 1153 dpu1_intsteer: dpu_intsteer@56000000 {
1128 compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; 1154 compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
1129 reg = <0x0 0x56000000 0x0 0x10000>; 1155 reg = <0x0 0x56000000 0x0 0x10000>;
1130 }; 1156 };
1131 1157
1132 dpu1: dpu@56180000 { 1158 dpu1: dpu@56180000 {
1133 #address-cells = <1>; 1159 #address-cells = <1>;
1134 #size-cells = <0>; 1160 #size-cells = <0>;
1135 compatible = "fsl,imx8qm-dpu"; 1161 compatible = "fsl,imx8qm-dpu";
1136 reg = <0x0 0x56180000 0x0 0x40000>; 1162 reg = <0x0 0x56180000 0x0 0x40000>;
1137 intsteer = <&dpu1_intsteer>; 1163 intsteer = <&dpu1_intsteer>;
1138 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1164 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1171 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1146 interrupt-names = "irq_common", 1172 interrupt-names = "irq_common",
1147 "irq_stream0a", 1173 "irq_stream0a",
1148 "irq_stream0b", /* to M4? */ 1174 "irq_stream0b", /* to M4? */
1149 "irq_stream1a", 1175 "irq_stream1a",
1150 "irq_stream1b", /* to M4? */ 1176 "irq_stream1b", /* to M4? */
1151 "irq_reserved0", 1177 "irq_reserved0",
1152 "irq_reserved1", 1178 "irq_reserved1",
1153 "irq_blit"; 1179 "irq_blit";
1154 clocks = <&clk IMX8QM_DC0_PLL0_CLK>, 1180 clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
1155 <&clk IMX8QM_DC0_PLL1_CLK>, 1181 <&clk IMX8QM_DC0_PLL1_CLK>,
1156 <&clk IMX8QM_DC0_DISP0_CLK>, 1182 <&clk IMX8QM_DC0_DISP0_CLK>,
1157 <&clk IMX8QM_DC0_DISP1_CLK>; 1183 <&clk IMX8QM_DC0_DISP1_CLK>;
1158 clock-names = "pll0", "pll1", "disp0", "disp1"; 1184 clock-names = "pll0", "pll1", "disp0", "disp1";
1159 power-domains = <&pd_dc0_pll1>; 1185 power-domains = <&pd_dc0_pll1>;
1160 status = "disabled"; 1186 status = "disabled";
1161 1187
1162 dpu1_disp0: port@0 { 1188 dpu1_disp0: port@0 {
1163 reg = <0>; 1189 reg = <0>;
1164 1190
1165 dpu1_disp0_mipi_dsi: mipi-dsi-endpoint { 1191 dpu1_disp0_mipi_dsi: mipi-dsi-endpoint {
1166 }; 1192 };
1167 }; 1193 };
1168 1194
1169 dpu1_disp1: port@1 { 1195 dpu1_disp1: port@1 {
1170 reg = <1>; 1196 reg = <1>;
1171 1197
1172 dpu1_disp1_lvds0: lvds0-endpoint { 1198 dpu1_disp1_lvds0: lvds0-endpoint {
1173 remote-endpoint = <&ldb1_lvds0>; 1199 remote-endpoint = <&ldb1_lvds0>;
1174 }; 1200 };
1175 1201
1176 dpu1_disp1_lvds1: lvds1-endpoint { 1202 dpu1_disp1_lvds1: lvds1-endpoint {
1177 remote-endpoint = <&ldb1_lvds1>; 1203 remote-endpoint = <&ldb1_lvds1>;
1178 }; 1204 };
1179 }; 1205 };
1180 }; 1206 };
1181 1207
1182 lvds_region1: lvds_region@56240000 { 1208 lvds_region1: lvds_region@56240000 {
1183 compatible = "fsl,imx8qm-lvds-region", "syscon"; 1209 compatible = "fsl,imx8qm-lvds-region", "syscon";
1184 reg = <0x0 0x56240000 0x0 0x10000>; 1210 reg = <0x0 0x56240000 0x0 0x10000>;
1185 }; 1211 };
1186 1212
1187 ldb1_phy: ldb_phy@56241000 { 1213 ldb1_phy: ldb_phy@56241000 {
1188 #address-cells = <1>; 1214 #address-cells = <1>;
1189 #size-cells = <0>; 1215 #size-cells = <0>;
1190 compatible = "mixel,lvds-phy"; 1216 compatible = "mixel,lvds-phy";
1191 reg = <0x0 0x56241000 0x0 0x100>; 1217 reg = <0x0 0x56241000 0x0 0x100>;
1192 clocks = <&clk IMX8QM_LVDS0_PHY_CLK>; 1218 clocks = <&clk IMX8QM_LVDS0_PHY_CLK>;
1193 clock-names = "phy"; 1219 clock-names = "phy";
1194 power-domains = <&pd_lvds0>; 1220 power-domains = <&pd_lvds0>;
1195 status = "disabled"; 1221 status = "disabled";
1196 1222
1197 ldb1_phy1: port@0 { 1223 ldb1_phy1: port@0 {
1198 reg = <0>; 1224 reg = <0>;
1199 #phy-cells = <0>; 1225 #phy-cells = <0>;
1200 }; 1226 };
1201 1227
1202 ldb1_phy2: port@1 { 1228 ldb1_phy2: port@1 {
1203 reg = <1>; 1229 reg = <1>;
1204 #phy-cells = <0>; 1230 #phy-cells = <0>;
1205 }; 1231 };
1206 }; 1232 };
1207 1233
1208 ldb1: ldb@562410e0 { 1234 ldb1: ldb@562410e0 {
1209 #address-cells = <1>; 1235 #address-cells = <1>;
1210 #size-cells = <0>; 1236 #size-cells = <0>;
1211 compatible = "fsl,imx8qm-ldb"; 1237 compatible = "fsl,imx8qm-ldb";
1212 clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, 1238 clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>,
1213 <&clk IMX8QM_LVDS0_BYPASS_CLK>; 1239 <&clk IMX8QM_LVDS0_BYPASS_CLK>;
1214 clock-names = "pixel", "bypass"; 1240 clock-names = "pixel", "bypass";
1215 power-domains = <&pd_lvds0>; 1241 power-domains = <&pd_lvds0>;
1216 gpr = <&lvds_region1>; 1242 gpr = <&lvds_region1>;
1217 status = "disabled"; 1243 status = "disabled";
1218 1244
1219 lvds-channel@0 { 1245 lvds-channel@0 {
1220 #address-cells = <1>; 1246 #address-cells = <1>;
1221 #size-cells = <0>; 1247 #size-cells = <0>;
1222 reg = <0>; 1248 reg = <0>;
1223 phys = <&ldb1_phy1>; 1249 phys = <&ldb1_phy1>;
1224 phy-names = "ldb_phy"; 1250 phy-names = "ldb_phy";
1225 status = "disabled"; 1251 status = "disabled";
1226 1252
1227 port@0 { 1253 port@0 {
1228 reg = <0>; 1254 reg = <0>;
1229 1255
1230 ldb1_lvds0: endpoint { 1256 ldb1_lvds0: endpoint {
1231 remote-endpoint = <&dpu1_disp1_lvds0>; 1257 remote-endpoint = <&dpu1_disp1_lvds0>;
1232 }; 1258 };
1233 }; 1259 };
1234 }; 1260 };
1235 1261
1236 lvds-channel@1 { 1262 lvds-channel@1 {
1237 #address-cells = <1>; 1263 #address-cells = <1>;
1238 #size-cells = <0>; 1264 #size-cells = <0>;
1239 reg = <1>; 1265 reg = <1>;
1240 phys = <&ldb1_phy2>; 1266 phys = <&ldb1_phy2>;
1241 phy-names = "ldb_phy"; 1267 phy-names = "ldb_phy";
1242 status = "disabled"; 1268 status = "disabled";
1243 1269
1244 port@0 { 1270 port@0 {
1245 reg = <0>; 1271 reg = <0>;
1246 1272
1247 ldb1_lvds1: endpoint { 1273 ldb1_lvds1: endpoint {
1248 remote-endpoint = <&dpu1_disp1_lvds1>; 1274 remote-endpoint = <&dpu1_disp1_lvds1>;
1249 }; 1275 };
1250 }; 1276 };
1251 }; 1277 };
1252 }; 1278 };
1253 1279
1254 dpu2_intsteer: dpu_intsteer@57000000 { 1280 dpu2_intsteer: dpu_intsteer@57000000 {
1255 compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; 1281 compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
1256 reg = <0x0 0x57000000 0x0 0x10000>; 1282 reg = <0x0 0x57000000 0x0 0x10000>;
1257 }; 1283 };
1258 1284
1259 dpu2: dpu@57180000 { 1285 dpu2: dpu@57180000 {
1260 #address-cells = <1>; 1286 #address-cells = <1>;
1261 #size-cells = <0>; 1287 #size-cells = <0>;
1262 compatible = "fsl,imx8qm-dpu"; 1288 compatible = "fsl,imx8qm-dpu";
1263 reg = <0x0 0x57180000 0x0 0x40000>; 1289 reg = <0x0 0x57180000 0x0 0x40000>;
1264 intsteer = <&dpu2_intsteer>; 1290 intsteer = <&dpu2_intsteer>;
1265 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1291 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1298 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1273 interrupt-names = "irq_common", 1299 interrupt-names = "irq_common",
1274 "irq_stream0a", 1300 "irq_stream0a",
1275 "irq_stream0b", /* to M4? */ 1301 "irq_stream0b", /* to M4? */
1276 "irq_stream1a", 1302 "irq_stream1a",
1277 "irq_stream1b", /* to M4? */ 1303 "irq_stream1b", /* to M4? */
1278 "irq_reserved0", 1304 "irq_reserved0",
1279 "irq_reserved1", 1305 "irq_reserved1",
1280 "irq_blit"; 1306 "irq_blit";
1281 clocks = <&clk IMX8QM_DC1_PLL0_CLK>, 1307 clocks = <&clk IMX8QM_DC1_PLL0_CLK>,
1282 <&clk IMX8QM_DC1_PLL1_CLK>, 1308 <&clk IMX8QM_DC1_PLL1_CLK>,
1283 <&clk IMX8QM_DC1_DISP0_CLK>, 1309 <&clk IMX8QM_DC1_DISP0_CLK>,
1284 <&clk IMX8QM_DC1_DISP1_CLK>; 1310 <&clk IMX8QM_DC1_DISP1_CLK>;
1285 clock-names = "pll0", "pll1", "disp0", "disp1"; 1311 clock-names = "pll0", "pll1", "disp0", "disp1";
1286 power-domains = <&pd_dc1_pll1>; 1312 power-domains = <&pd_dc1_pll1>;
1287 status = "disabled"; 1313 status = "disabled";
1288 1314
1289 dpu2_disp0: port@0 { 1315 dpu2_disp0: port@0 {
1290 reg = <0>; 1316 reg = <0>;
1291 1317
1292 dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { 1318 dpu2_disp0_mipi_dsi: mipi-dsi-endpoint {
1293 }; 1319 };
1294 }; 1320 };
1295 1321
1296 dpu2_disp1: port@1 { 1322 dpu2_disp1: port@1 {
1297 reg = <1>; 1323 reg = <1>;
1298 1324
1299 dpu2_disp1_lvds0: lvds0-endpoint { 1325 dpu2_disp1_lvds0: lvds0-endpoint {
1300 remote-endpoint = <&ldb2_lvds0>; 1326 remote-endpoint = <&ldb2_lvds0>;
1301 }; 1327 };
1302 1328
1303 dpu2_disp1_lvds1: lvds1-endpoint { 1329 dpu2_disp1_lvds1: lvds1-endpoint {
1304 remote-endpoint = <&ldb2_lvds1>; 1330 remote-endpoint = <&ldb2_lvds1>;
1305 }; 1331 };
1306 }; 1332 };
1307 }; 1333 };
1308 1334
1309 lvds_region2: lvds_region@57240000 { 1335 lvds_region2: lvds_region@57240000 {
1310 compatible = "fsl,imx8qm-lvds-region", "syscon"; 1336 compatible = "fsl,imx8qm-lvds-region", "syscon";
1311 reg = <0x0 0x57240000 0x0 0x10000>; 1337 reg = <0x0 0x57240000 0x0 0x10000>;
1312 }; 1338 };
1313 1339
1314 ldb2_phy: ldb_phy@57241000 { 1340 ldb2_phy: ldb_phy@57241000 {
1315 #address-cells = <1>; 1341 #address-cells = <1>;
1316 #size-cells = <0>; 1342 #size-cells = <0>;
1317 compatible = "mixel,lvds-phy"; 1343 compatible = "mixel,lvds-phy";
1318 reg = <0x0 0x57241000 0x0 0x100>; 1344 reg = <0x0 0x57241000 0x0 0x100>;
1319 clocks = <&clk IMX8QM_LVDS1_PHY_CLK>; 1345 clocks = <&clk IMX8QM_LVDS1_PHY_CLK>;
1320 clock-names = "phy"; 1346 clock-names = "phy";
1321 power-domains = <&pd_lvds1>; 1347 power-domains = <&pd_lvds1>;
1322 status = "disabled"; 1348 status = "disabled";
1323 1349
1324 ldb2_phy1: port@0 { 1350 ldb2_phy1: port@0 {
1325 reg = <0>; 1351 reg = <0>;
1326 #phy-cells = <0>; 1352 #phy-cells = <0>;
1327 }; 1353 };
1328 1354
1329 ldb2_phy2: port@1 { 1355 ldb2_phy2: port@1 {
1330 reg = <1>; 1356 reg = <1>;
1331 #phy-cells = <0>; 1357 #phy-cells = <0>;
1332 }; 1358 };
1333 }; 1359 };
1334 1360
1335 ldb2: ldb@572410e0 { 1361 ldb2: ldb@572410e0 {
1336 #address-cells = <1>; 1362 #address-cells = <1>;
1337 #size-cells = <0>; 1363 #size-cells = <0>;
1338 compatible = "fsl,imx8qm-ldb"; 1364 compatible = "fsl,imx8qm-ldb";
1339 clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, 1365 clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>,
1340 <&clk IMX8QM_LVDS1_BYPASS_CLK>; 1366 <&clk IMX8QM_LVDS1_BYPASS_CLK>;
1341 clock-names = "pixel", "bypass"; 1367 clock-names = "pixel", "bypass";
1342 power-domains = <&pd_lvds1>; 1368 power-domains = <&pd_lvds1>;
1343 gpr = <&lvds_region2>; 1369 gpr = <&lvds_region2>;
1344 status = "disabled"; 1370 status = "disabled";
1345 1371
1346 lvds-channel@0 { 1372 lvds-channel@0 {
1347 #address-cells = <1>; 1373 #address-cells = <1>;
1348 #size-cells = <0>; 1374 #size-cells = <0>;
1349 reg = <0>; 1375 reg = <0>;
1350 phys = <&ldb2_phy1>; 1376 phys = <&ldb2_phy1>;
1351 phy-names = "ldb_phy"; 1377 phy-names = "ldb_phy";
1352 status = "disabled"; 1378 status = "disabled";
1353 1379
1354 port@0 { 1380 port@0 {
1355 reg = <0>; 1381 reg = <0>;
1356 1382
1357 ldb2_lvds0: endpoint { 1383 ldb2_lvds0: endpoint {
1358 remote-endpoint = <&dpu2_disp1_lvds0>; 1384 remote-endpoint = <&dpu2_disp1_lvds0>;
1359 }; 1385 };
1360 }; 1386 };
1361 }; 1387 };
1362 1388
1363 lvds-channel@1 { 1389 lvds-channel@1 {
1364 #address-cells = <1>; 1390 #address-cells = <1>;
1365 #size-cells = <0>; 1391 #size-cells = <0>;
1366 reg = <1>; 1392 reg = <1>;
1367 phys = <&ldb2_phy2>; 1393 phys = <&ldb2_phy2>;
1368 phy-names = "ldb_phy"; 1394 phy-names = "ldb_phy";
1369 status = "disabled"; 1395 status = "disabled";
1370 1396
1371 port@0 { 1397 port@0 {
1372 reg = <0>; 1398 reg = <0>;
1373 1399
1374 ldb2_lvds1: endpoint { 1400 ldb2_lvds1: endpoint {
1375 remote-endpoint = <&dpu2_disp1_lvds1>; 1401 remote-endpoint = <&dpu2_disp1_lvds1>;
1376 }; 1402 };
1377 }; 1403 };
1378 }; 1404 };
1379 }; 1405 };
1380 1406
1381 camera { 1407 camera {
1382 compatible = "fsl,mxc-md", "simple-bus"; 1408 compatible = "fsl,mxc-md", "simple-bus";
1383 #address-cells = <2>; 1409 #address-cells = <2>;
1384 #size-cells = <2>; 1410 #size-cells = <2>;
1385 ranges; 1411 ranges;
1386 1412
1387 isi_0: isi@58100000 { 1413 isi_0: isi@58100000 {
1388 compatible = "fsl,imx8-isi"; 1414 compatible = "fsl,imx8-isi";
1389 reg = <0x0 0x58100000 0x0 0x10000>; 1415 reg = <0x0 0x58100000 0x0 0x10000>;
1390 interrupts = <0 297 0>; 1416 interrupts = <0 297 0>;
1391 interface = <2 0 2>; /* <Input MIPI_VCx Output> 1417 interface = <2 0 2>; /* <Input MIPI_VCx Output>
1392 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM 1418 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
1393 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only 1419 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
1394 Output: 0-DC0, 1-DC1, 2-MEM */ 1420 Output: 0-DC0, 1-DC1, 2-MEM */
1395 clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; 1421 clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
1396 clock-names = "per"; 1422 clock-names = "per";
1397 assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; 1423 assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
1398 assigned-clock-rates = <600000000>; 1424 assigned-clock-rates = <600000000>;
1399 power-domains =<&pd_isi_ch0>; 1425 power-domains =<&pd_isi_ch0>;
1400 status = "disabled"; 1426 status = "disabled";
1401 }; 1427 };
1402 1428
1403 isi_1: isi@58110000 { 1429 isi_1: isi@58110000 {
1404 compatible = "fsl,imx8-isi"; 1430 compatible = "fsl,imx8-isi";
1405 reg = <0x0 0x58110000 0x0 0x10000>; 1431 reg = <0x0 0x58110000 0x0 0x10000>;
1406 interrupts = <0 298 0>; 1432 interrupts = <0 298 0>;
1407 interface = <2 1 2>; 1433 interface = <2 1 2>;
1408 clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>; 1434 clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>;
1409 clock-names = "per"; 1435 clock-names = "per";
1410 assigned-clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>; 1436 assigned-clocks = <&clk IMX8QM_IMG_PDMA_1_CLK>;
1411 assigned-clock-rates = <600000000>; 1437 assigned-clock-rates = <600000000>;
1412 power-domains =<&pd_isi_ch1>; 1438 power-domains =<&pd_isi_ch1>;
1413 status = "disabled"; 1439 status = "disabled";
1414 }; 1440 };
1415 1441
1416 isi_2: isi@58120000 { 1442 isi_2: isi@58120000 {
1417 compatible = "fsl,imx8-isi"; 1443 compatible = "fsl,imx8-isi";
1418 reg = <0x0 0x58120000 0x0 0x10000>; 1444 reg = <0x0 0x58120000 0x0 0x10000>;
1419 interrupts = <0 299 0>; 1445 interrupts = <0 299 0>;
1420 interface = <2 2 2>; 1446 interface = <2 2 2>;
1421 clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>; 1447 clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>;
1422 clock-names = "per"; 1448 clock-names = "per";
1423 assigned-clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>; 1449 assigned-clocks = <&clk IMX8QM_IMG_PDMA_2_CLK>;
1424 assigned-clock-rates = <600000000>; 1450 assigned-clock-rates = <600000000>;
1425 power-domains =<&pd_isi_ch2>; 1451 power-domains =<&pd_isi_ch2>;
1426 status = "disabled"; 1452 status = "disabled";
1427 }; 1453 };
1428 1454
1429 isi_3: isi@58130000 { 1455 isi_3: isi@58130000 {
1430 compatible = "fsl,imx8-isi"; 1456 compatible = "fsl,imx8-isi";
1431 reg = <0x0 0x58130000 0x0 0x10000>; 1457 reg = <0x0 0x58130000 0x0 0x10000>;
1432 interrupts = <0 300 0>; 1458 interrupts = <0 300 0>;
1433 interface = <2 3 2>; 1459 interface = <2 3 2>;
1434 clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>; 1460 clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>;
1435 clock-names = "per"; 1461 clock-names = "per";
1436 assigned-clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>; 1462 assigned-clocks = <&clk IMX8QM_IMG_PDMA_3_CLK>;
1437 assigned-clock-rates = <600000000>; 1463 assigned-clock-rates = <600000000>;
1438 power-domains =<&pd_isi_ch3>; 1464 power-domains =<&pd_isi_ch3>;
1439 status = "disabled"; 1465 status = "disabled";
1440 }; 1466 };
1441 1467
1442 isi_4: isi@58140000 { 1468 isi_4: isi@58140000 {
1443 compatible = "fsl,imx8-isi"; 1469 compatible = "fsl,imx8-isi";
1444 reg = <0x0 0x58140000 0x0 0x10000>; 1470 reg = <0x0 0x58140000 0x0 0x10000>;
1445 interrupts = <0 301 0>; 1471 interrupts = <0 301 0>;
1446 interface = <3 0 2>; 1472 interface = <3 0 2>;
1447 clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>; 1473 clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>;
1448 clock-names = "per"; 1474 clock-names = "per";
1449 assigned-clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>; 1475 assigned-clocks = <&clk IMX8QM_IMG_PDMA_4_CLK>;
1450 assigned-clock-rates = <600000000>; 1476 assigned-clock-rates = <600000000>;
1451 power-domains =<&pd_isi_ch4>; 1477 power-domains =<&pd_isi_ch4>;
1452 status = "disabled"; 1478 status = "disabled";
1453 }; 1479 };
1454 1480
1455 isi_5: isi@58150000 { 1481 isi_5: isi@58150000 {
1456 compatible = "fsl,imx8-isi"; 1482 compatible = "fsl,imx8-isi";
1457 reg = <0x0 0x58150000 0x0 0x10000>; 1483 reg = <0x0 0x58150000 0x0 0x10000>;
1458 interrupts = <0 302 0>; 1484 interrupts = <0 302 0>;
1459 interface = <3 1 2>; 1485 interface = <3 1 2>;
1460 clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>; 1486 clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>;
1461 clock-names = "per"; 1487 clock-names = "per";
1462 assigned-clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>; 1488 assigned-clocks = <&clk IMX8QM_IMG_PDMA_5_CLK>;
1463 assigned-clock-rates = <600000000>; 1489 assigned-clock-rates = <600000000>;
1464 power-domains =<&pd_isi_ch5>; 1490 power-domains =<&pd_isi_ch5>;
1465 status = "disabled"; 1491 status = "disabled";
1466 }; 1492 };
1467 1493
1468 isi_6: isi@58160000 { 1494 isi_6: isi@58160000 {
1469 compatible = "fsl,imx8-isi"; 1495 compatible = "fsl,imx8-isi";
1470 reg = <0x0 0x58160000 0x0 0x10000>; 1496 reg = <0x0 0x58160000 0x0 0x10000>;
1471 interrupts = <0 303 0>; 1497 interrupts = <0 303 0>;
1472 interface = <3 2 2>; 1498 interface = <3 2 2>;
1473 clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>; 1499 clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>;
1474 clock-names = "per"; 1500 clock-names = "per";
1475 assigned-clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>; 1501 assigned-clocks = <&clk IMX8QM_IMG_PDMA_6_CLK>;
1476 assigned-clock-rates = <600000000>; 1502 assigned-clock-rates = <600000000>;
1477 power-domains =<&pd_isi_ch6>; 1503 power-domains =<&pd_isi_ch6>;
1478 status = "disabled"; 1504 status = "disabled";
1479 }; 1505 };
1480 1506
1481 isi_7: isi@58170000 { 1507 isi_7: isi@58170000 {
1482 compatible = "fsl,imx8-isi"; 1508 compatible = "fsl,imx8-isi";
1483 reg = <0x0 0x58170000 0x0 0x10000>; 1509 reg = <0x0 0x58170000 0x0 0x10000>;
1484 interrupts = <0 304 0>; 1510 interrupts = <0 304 0>;
1485 interface = <3 3 2>; 1511 interface = <3 3 2>;
1486 clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>; 1512 clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>;
1487 clock-names = "per"; 1513 clock-names = "per";
1488 assigned-clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>; 1514 assigned-clocks = <&clk IMX8QM_IMG_PDMA_7_CLK>;
1489 assigned-clock-rates = <600000000>; 1515 assigned-clock-rates = <600000000>;
1490 power-domains =<&pd_isi_ch7>; 1516 power-domains =<&pd_isi_ch7>;
1491 status = "disabled"; 1517 status = "disabled";
1492 }; 1518 };
1493 1519
1494 mipi_csi_0: csi@58227000 { 1520 mipi_csi_0: csi@58227000 {
1495 compatible = "fsl,mxc-mipi-csi2"; 1521 compatible = "fsl,mxc-mipi-csi2";
1496 reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ 1522 reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */
1497 <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ 1523 <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */
1498 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 1524 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
1499 interrupt-parent = <&irqsteer_csi0>; 1525 interrupt-parent = <&irqsteer_csi0>;
1500 clocks = <&clk IMX8QM_CSI0_APB_CLK>, 1526 clocks = <&clk IMX8QM_CSI0_APB_CLK>,
1501 <&clk IMX8QM_CSI0_CORE_CLK>, 1527 <&clk IMX8QM_CSI0_CORE_CLK>,
1502 <&clk IMX8QM_CSI0_ESC_CLK>, 1528 <&clk IMX8QM_CSI0_ESC_CLK>,
1503 <&clk IMX8QM_IMG_PXL_LINK_CSI0_CLK>; 1529 <&clk IMX8QM_IMG_PXL_LINK_CSI0_CLK>;
1504 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; 1530 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
1505 assigned-clocks = <&clk IMX8QM_CSI0_CORE_CLK>, 1531 assigned-clocks = <&clk IMX8QM_CSI0_CORE_CLK>,
1506 <&clk IMX8QM_CSI0_ESC_CLK>; 1532 <&clk IMX8QM_CSI0_ESC_CLK>;
1507 assigned-clock-rates = <360000000>, <72000000>; 1533 assigned-clock-rates = <360000000>, <72000000>;
1508 power-domains = <&pd_csi0>; 1534 power-domains = <&pd_csi0>;
1509 status = "disabled"; 1535 status = "disabled";
1510 }; 1536 };
1511 1537
1512 mipi_csi_1: csi@58247000 { 1538 mipi_csi_1: csi@58247000 {
1513 compatible = "fsl,mxc-mipi-csi2"; 1539 compatible = "fsl,mxc-mipi-csi2";
1514 reg = <0x0 0x58247000 0x0 0x1000>, /* CSI1 Controler base addr */ 1540 reg = <0x0 0x58247000 0x0 0x1000>, /* CSI1 Controler base addr */
1515 <0x0 0x58241000 0x0 0x1000>; /* CSI1 Subsystem CSR base addr */ 1541 <0x0 0x58241000 0x0 0x1000>; /* CSI1 Subsystem CSR base addr */
1516 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 1542 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
1517 interrupt-parent = <&irqsteer_csi1>; 1543 interrupt-parent = <&irqsteer_csi1>;
1518 clocks = <&clk IMX8QM_CSI1_APB_CLK>, 1544 clocks = <&clk IMX8QM_CSI1_APB_CLK>,
1519 <&clk IMX8QM_CSI1_CORE_CLK>, 1545 <&clk IMX8QM_CSI1_CORE_CLK>,
1520 <&clk IMX8QM_CSI1_ESC_CLK>, 1546 <&clk IMX8QM_CSI1_ESC_CLK>,
1521 <&clk IMX8QM_IMG_PXL_LINK_CSI1_CLK>; 1547 <&clk IMX8QM_IMG_PXL_LINK_CSI1_CLK>;
1522 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; 1548 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
1523 assigned-clocks = <&clk IMX8QM_CSI1_CORE_CLK>, 1549 assigned-clocks = <&clk IMX8QM_CSI1_CORE_CLK>,
1524 <&clk IMX8QM_CSI1_ESC_CLK>; 1550 <&clk IMX8QM_CSI1_ESC_CLK>;
1525 assigned-clock-rates = <360000000>, <72000000>; 1551 assigned-clock-rates = <360000000>, <72000000>;
1526 power-domains = <&pd_csi1>; 1552 power-domains = <&pd_csi1>;
1527 status = "disabled"; 1553 status = "disabled";
1528 }; 1554 };
1529 }; 1555 };
1530 1556
1531 gpio0: gpio@5d080000 { 1557 gpio0: gpio@5d080000 {
1532 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1558 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1533 reg = <0x0 0x5d080000 0x0 0x10000>; 1559 reg = <0x0 0x5d080000 0x0 0x10000>;
1534 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1535 gpio-controller; 1561 gpio-controller;
1536 #gpio-cells = <2>; 1562 #gpio-cells = <2>;
1537 interrupt-controller; 1563 interrupt-controller;
1538 #interrupt-cells = <2>; 1564 #interrupt-cells = <2>;
1539 power-domains = <&pd_lsio_gpio0>; 1565 power-domains = <&pd_lsio_gpio0>;
1540 }; 1566 };
1541 1567
1542 gpio1: gpio@5d090000 { 1568 gpio1: gpio@5d090000 {
1543 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1569 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1544 reg = <0x0 0x5d090000 0x0 0x10000>; 1570 reg = <0x0 0x5d090000 0x0 0x10000>;
1545 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1571 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1546 gpio-controller; 1572 gpio-controller;
1547 #gpio-cells = <2>; 1573 #gpio-cells = <2>;
1548 interrupt-controller; 1574 interrupt-controller;
1549 #interrupt-cells = <2>; 1575 #interrupt-cells = <2>;
1550 power-domains = <&pd_lsio_gpio1>; 1576 power-domains = <&pd_lsio_gpio1>;
1551 }; 1577 };
1552 1578
1553 gpio2: gpio@5d0a0000 { 1579 gpio2: gpio@5d0a0000 {
1554 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1580 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1555 reg = <0x0 0x5d0a0000 0x0 0x10000>; 1581 reg = <0x0 0x5d0a0000 0x0 0x10000>;
1556 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1582 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1557 gpio-controller; 1583 gpio-controller;
1558 #gpio-cells = <2>; 1584 #gpio-cells = <2>;
1559 interrupt-controller; 1585 interrupt-controller;
1560 #interrupt-cells = <2>; 1586 #interrupt-cells = <2>;
1561 power-domains = <&pd_lsio_gpio2>; 1587 power-domains = <&pd_lsio_gpio2>;
1562 }; 1588 };
1563 1589
1564 gpio3: gpio@5d0b0000 { 1590 gpio3: gpio@5d0b0000 {
1565 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1591 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1566 reg = <0x0 0x5d0b0000 0x0 0x10000>; 1592 reg = <0x0 0x5d0b0000 0x0 0x10000>;
1567 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1593 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1568 gpio-controller; 1594 gpio-controller;
1569 #gpio-cells = <2>; 1595 #gpio-cells = <2>;
1570 interrupt-controller; 1596 interrupt-controller;
1571 #interrupt-cells = <2>; 1597 #interrupt-cells = <2>;
1572 power-domains = <&pd_lsio_gpio3>; 1598 power-domains = <&pd_lsio_gpio3>;
1573 }; 1599 };
1574 1600
1575 gpio4: gpio@5d0c0000 { 1601 gpio4: gpio@5d0c0000 {
1576 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1602 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1577 reg = <0x0 0x5d0c0000 0x0 0x10000>; 1603 reg = <0x0 0x5d0c0000 0x0 0x10000>;
1578 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1604 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1579 gpio-controller; 1605 gpio-controller;
1580 #gpio-cells = <2>; 1606 #gpio-cells = <2>;
1581 interrupt-controller; 1607 interrupt-controller;
1582 #interrupt-cells = <2>; 1608 #interrupt-cells = <2>;
1583 power-domains = <&pd_lsio_gpio4>; 1609 power-domains = <&pd_lsio_gpio4>;
1584 }; 1610 };
1585 1611
1586 gpio5: gpio@5d0d0000 { 1612 gpio5: gpio@5d0d0000 {
1587 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1613 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1588 reg = <0x0 0x5d0d0000 0x0 0x10000>; 1614 reg = <0x0 0x5d0d0000 0x0 0x10000>;
1589 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1615 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1590 gpio-controller; 1616 gpio-controller;
1591 #gpio-cells = <2>; 1617 #gpio-cells = <2>;
1592 interrupt-controller; 1618 interrupt-controller;
1593 #interrupt-cells = <2>; 1619 #interrupt-cells = <2>;
1594 power-domains = <&pd_lsio_gpio5>; 1620 power-domains = <&pd_lsio_gpio5>;
1595 }; 1621 };
1596 1622
1597 gpio6: gpio@5d0e0000 { 1623 gpio6: gpio@5d0e0000 {
1598 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1624 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1599 reg = <0x0 0x5d0e0000 0x0 0x10000>; 1625 reg = <0x0 0x5d0e0000 0x0 0x10000>;
1600 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1626 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1601 gpio-controller; 1627 gpio-controller;
1602 #gpio-cells = <2>; 1628 #gpio-cells = <2>;
1603 interrupt-controller; 1629 interrupt-controller;
1604 #interrupt-cells = <2>; 1630 #interrupt-cells = <2>;
1605 power-domains = <&pd_lsio_gpio6>; 1631 power-domains = <&pd_lsio_gpio6>;
1606 }; 1632 };
1607 1633
1608 gpio7: gpio@5d0f0000 { 1634 gpio7: gpio@5d0f0000 {
1609 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1635 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1610 reg = <0x0 0x5d0f0000 0x0 0x10000>; 1636 reg = <0x0 0x5d0f0000 0x0 0x10000>;
1611 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1637 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1612 gpio-controller; 1638 gpio-controller;
1613 #gpio-cells = <2>; 1639 #gpio-cells = <2>;
1614 interrupt-controller; 1640 interrupt-controller;
1615 #interrupt-cells = <2>; 1641 #interrupt-cells = <2>;
1616 power-domains = <&pd_lsio_gpio7>; 1642 power-domains = <&pd_lsio_gpio7>;
1617 }; 1643 };
1618 1644
1619 i2c0: i2c@5a800000 { 1645 i2c0: i2c@5a800000 {
1620 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1646 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1621 reg = <0x0 0x5a800000 0x0 0x4000>; 1647 reg = <0x0 0x5a800000 0x0 0x4000>;
1622 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1648 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1623 interrupt-parent = <&gic>; 1649 interrupt-parent = <&gic>;
1624 clocks = <&clk IMX8QM_I2C0_CLK>, 1650 clocks = <&clk IMX8QM_I2C0_CLK>,
1625 <&clk IMX8QM_I2C0_IPG_CLK>; 1651 <&clk IMX8QM_I2C0_IPG_CLK>;
1626 clock-names = "per", "ipg"; 1652 clock-names = "per", "ipg";
1627 assigned-clocks = <&clk IMX8QM_I2C0_CLK>; 1653 assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
1628 assigned-clock-rates = <24000000>; 1654 assigned-clock-rates = <24000000>;
1629 power-domains = <&pd_dma_lpi2c0>; 1655 power-domains = <&pd_dma_lpi2c0>;
1630 status = "disabled"; 1656 status = "disabled";
1631 }; 1657 };
1632 1658
1633 i2c1: i2c@5a810000 { 1659 i2c1: i2c@5a810000 {
1634 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1660 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1635 reg = <0x0 0x5a810000 0x0 0x4000>; 1661 reg = <0x0 0x5a810000 0x0 0x4000>;
1636 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1662 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1637 interrupt-parent = <&gic>; 1663 interrupt-parent = <&gic>;
1638 clocks = <&clk IMX8QM_I2C1_CLK>, 1664 clocks = <&clk IMX8QM_I2C1_CLK>,
1639 <&clk IMX8QM_I2C1_IPG_CLK>; 1665 <&clk IMX8QM_I2C1_IPG_CLK>;
1640 clock-names = "per", "ipg"; 1666 clock-names = "per", "ipg";
1641 assigned-clocks = <&clk IMX8QM_I2C1_CLK>; 1667 assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
1642 assigned-clock-rates = <24000000>; 1668 assigned-clock-rates = <24000000>;
1643 power-domains = <&pd_dma_lpi2c1>; 1669 power-domains = <&pd_dma_lpi2c1>;
1644 status = "disabled"; 1670 status = "disabled";
1645 }; 1671 };
1646 1672
1647 i2c2: i2c@5a820000 { 1673 i2c2: i2c@5a820000 {
1648 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1674 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1649 reg = <0x0 0x5a820000 0x0 0x4000>; 1675 reg = <0x0 0x5a820000 0x0 0x4000>;
1650 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1676 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1651 interrupt-parent = <&gic>; 1677 interrupt-parent = <&gic>;
1652 clocks = <&clk IMX8QM_I2C2_CLK>, 1678 clocks = <&clk IMX8QM_I2C2_CLK>,
1653 <&clk IMX8QM_I2C2_IPG_CLK>; 1679 <&clk IMX8QM_I2C2_IPG_CLK>;
1654 clock-names = "per", "ipg"; 1680 clock-names = "per", "ipg";
1655 assigned-clocks = <&clk IMX8QM_I2C2_CLK>; 1681 assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
1656 assigned-clock-rates = <24000000>; 1682 assigned-clock-rates = <24000000>;
1657 power-domains = <&pd_dma_lpi2c2>; 1683 power-domains = <&pd_dma_lpi2c2>;
1658 status = "disabled"; 1684 status = "disabled";
1659 }; 1685 };
1660 1686
1661 i2c3: i2c@5a830000 { 1687 i2c3: i2c@5a830000 {
1662 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1688 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1663 reg = <0x0 0x5a830000 0x0 0x4000>; 1689 reg = <0x0 0x5a830000 0x0 0x4000>;
1664 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1690 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1665 interrupt-parent = <&gic>; 1691 interrupt-parent = <&gic>;
1666 clocks = <&clk IMX8QM_I2C3_CLK>, 1692 clocks = <&clk IMX8QM_I2C3_CLK>,
1667 <&clk IMX8QM_I2C3_IPG_CLK>; 1693 <&clk IMX8QM_I2C3_IPG_CLK>;
1668 clock-names = "per", "ipg"; 1694 clock-names = "per", "ipg";
1669 assigned-clocks = <&clk IMX8QM_I2C3_CLK>; 1695 assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
1670 assigned-clock-rates = <24000000>; 1696 assigned-clock-rates = <24000000>;
1671 power-domains = <&pd_dma_lpi2c3>; 1697 power-domains = <&pd_dma_lpi2c3>;
1672 status = "disabled"; 1698 status = "disabled";
1673 }; 1699 };
1674 1700
1675 i2c4: i2c@5a840000 { 1701 i2c4: i2c@5a840000 {
1676 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1702 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1677 reg = <0x0 0x5a840000 0x0 0x4000>; 1703 reg = <0x0 0x5a840000 0x0 0x4000>;
1678 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1704 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1679 interrupt-parent = <&gic>; 1705 interrupt-parent = <&gic>;
1680 clocks = <&clk IMX8QM_I2C4_CLK>, 1706 clocks = <&clk IMX8QM_I2C4_CLK>,
1681 <&clk IMX8QM_I2C4_IPG_CLK>; 1707 <&clk IMX8QM_I2C4_IPG_CLK>;
1682 clock-names = "per", "ipg"; 1708 clock-names = "per", "ipg";
1683 assigned-clocks = <&clk IMX8QM_I2C4_CLK>; 1709 assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
1684 assigned-clock-rates = <24000000>; 1710 assigned-clock-rates = <24000000>;
1685 power-domains = <&pd_dma_lpi2c4>; 1711 power-domains = <&pd_dma_lpi2c4>;
1686 status = "disabled"; 1712 status = "disabled";
1687 }; 1713 };
1688 1714
1689 irqsteer_hdmi: irqsteer@56260000 { 1715 irqsteer_hdmi: irqsteer@56260000 {
1690 compatible = "nxp,imx-irqsteer"; 1716 compatible = "nxp,imx-irqsteer";
1691 reg = <0x0 0x56260000 0x0 0x1000>; 1717 reg = <0x0 0x56260000 0x0 0x1000>;
1692 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1718 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1693 interrupt-controller; 1719 interrupt-controller;
1694 interrupt-parent = <&gic>; 1720 interrupt-parent = <&gic>;
1695 #interrupt-cells = <2>; 1721 #interrupt-cells = <2>;
1696 clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, 1722 clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
1697 <&clk IMX8QM_HDMI_LIS_IPG_CLK>; 1723 <&clk IMX8QM_HDMI_LIS_IPG_CLK>;
1698 clock-names = "pll", "ipg"; 1724 clock-names = "pll", "ipg";
1699 assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, 1725 assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
1700 <&clk IMX8QM_HDMI_LIS_IPG_CLK>; 1726 <&clk IMX8QM_HDMI_LIS_IPG_CLK>;
1701 assigned-clock-rates = <675000000>, <84000000>; 1727 assigned-clock-rates = <675000000>, <84000000>;
1702 power-domains = <&pd_hdmi>; 1728 power-domains = <&pd_hdmi>;
1703 }; 1729 };
1704 1730
1705 i2c0_hdmi: i2c@56266000 { 1731 i2c0_hdmi: i2c@56266000 {
1706 compatible = "fsl,imx8qm-lpi2c"; 1732 compatible = "fsl,imx8qm-lpi2c";
1707 reg = <0x0 0x56266000 0x0 0x1000>; 1733 reg = <0x0 0x56266000 0x0 0x1000>;
1708 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1734 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1709 interrupt-parent = <&irqsteer_hdmi>; 1735 interrupt-parent = <&irqsteer_hdmi>;
1710 clocks = <&clk IMX8QM_HDMI_I2C0_CLK>, 1736 clocks = <&clk IMX8QM_HDMI_I2C0_CLK>,
1711 <&clk IMX8QM_HDMI_I2C_IPG_CLK>; 1737 <&clk IMX8QM_HDMI_I2C_IPG_CLK>;
1712 clock-names = "per", "ipg"; 1738 clock-names = "per", "ipg";
1713 assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; 1739 assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>;
1714 assigned-clock-rates = <24000000>; 1740 assigned-clock-rates = <24000000>;
1715 power-domains = <&pd_hdmi_i2c0>; 1741 power-domains = <&pd_hdmi_i2c0>;
1716 status = "disabled"; 1742 status = "disabled";
1717 }; 1743 };
1718 1744
1719 irqsteer_lvds0: irqsteer@562400000 { 1745 irqsteer_lvds0: irqsteer@562400000 {
1720 compatible = "nxp,imx-irqsteer"; 1746 compatible = "nxp,imx-irqsteer";
1721 reg = <0x0 0x56240000 0x0 0x1000>; 1747 reg = <0x0 0x56240000 0x0 0x1000>;
1722 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1748 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1723 interrupt-controller; 1749 interrupt-controller;
1724 interrupt-parent = <&gic>; 1750 interrupt-parent = <&gic>;
1725 #interrupt-cells = <2>; 1751 #interrupt-cells = <2>;
1726 clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>; 1752 clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>;
1727 clock-names = "ipg"; 1753 clock-names = "ipg";
1728 power-domains = <&pd_lvds0>; 1754 power-domains = <&pd_lvds0>;
1729 }; 1755 };
1730 1756
1731 flexcan1: can@5a8d0000 { 1757 flexcan1: can@5a8d0000 {
1732 compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; 1758 compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
1733 reg = <0x0 0x5a8d0000 0x0 0x10000>; 1759 reg = <0x0 0x5a8d0000 0x0 0x10000>;
1734 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1735 clocks = <&clk IMX8QM_CAN0_IPG_CLK>, 1761 clocks = <&clk IMX8QM_CAN0_IPG_CLK>,
1736 <&clk IMX8QM_CAN0_CLK>; 1762 <&clk IMX8QM_CAN0_CLK>;
1737 clock-names = "ipg", "per"; 1763 clock-names = "ipg", "per";
1738 assigned-clocks = <&clk IMX8QM_CAN0_CLK>; 1764 assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
1739 assigned-clock-rates = <40000000>; 1765 assigned-clock-rates = <40000000>;
1740 power-domains = <&pd_dma_flexcan0>; 1766 power-domains = <&pd_dma_flexcan0>;
1741 status = "disabled"; 1767 status = "disabled";
1742 }; 1768 };
1743 1769
1744 flexcan2: can@5a8e0000 { 1770 flexcan2: can@5a8e0000 {
1745 compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; 1771 compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
1746 reg = <0x0 0x5a8e0000 0x0 0x10000>; 1772 reg = <0x0 0x5a8e0000 0x0 0x10000>;
1747 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1773 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1748 clocks = <&clk IMX8QM_CAN1_IPG_CLK>, 1774 clocks = <&clk IMX8QM_CAN1_IPG_CLK>,
1749 <&clk IMX8QM_CAN1_CLK>; 1775 <&clk IMX8QM_CAN1_CLK>;
1750 clock-names = "ipg", "per"; 1776 clock-names = "ipg", "per";
1751 assigned-clocks = <&clk IMX8QM_CAN1_CLK>; 1777 assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
1752 assigned-clock-rates = <40000000>; 1778 assigned-clock-rates = <40000000>;
1753 power-domains = <&pd_dma_flexcan1>; 1779 power-domains = <&pd_dma_flexcan1>;
1754 status = "disabled"; 1780 status = "disabled";
1755 }; 1781 };
1756 1782
1757 flexcan3: can@5a8f0000 { 1783 flexcan3: can@5a8f0000 {
1758 compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan"; 1784 compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
1759 reg = <0x0 0x5a8f0000 0x0 0x10000>; 1785 reg = <0x0 0x5a8f0000 0x0 0x10000>;
1760 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1786 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1761 clocks = <&clk IMX8QM_CAN2_IPG_CLK>, 1787 clocks = <&clk IMX8QM_CAN2_IPG_CLK>,
1762 <&clk IMX8QM_CAN2_CLK>; 1788 <&clk IMX8QM_CAN2_CLK>;
1763 clock-names = "ipg", "per"; 1789 clock-names = "ipg", "per";
1764 assigned-clocks = <&clk IMX8QM_CAN2_CLK>; 1790 assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
1765 assigned-clock-rates = <40000000>; 1791 assigned-clock-rates = <40000000>;
1766 power-domains = <&pd_dma_flexcan2>; 1792 power-domains = <&pd_dma_flexcan2>;
1767 status = "disabled"; 1793 status = "disabled";
1768 }; 1794 };
1769 1795
1770 i2c1_lvds0: i2c@56247000 { 1796 i2c1_lvds0: i2c@56247000 {
1771 compatible = "fsl,imx8qm-lpi2c"; 1797 compatible = "fsl,imx8qm-lpi2c";
1772 reg = <0x0 0x56247000 0x0 0x1000>; 1798 reg = <0x0 0x56247000 0x0 0x1000>;
1773 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 1799 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
1774 interrupt-parent = <&irqsteer_lvds0>; 1800 interrupt-parent = <&irqsteer_lvds0>;
1775 clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>, 1801 clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>,
1776 <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>; 1802 <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>;
1777 clock-names = "per", "ipg"; 1803 clock-names = "per", "ipg";
1778 assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; 1804 assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>;
1779 assigned-clock-rates = <24000000>; 1805 assigned-clock-rates = <24000000>;
1780 power-domains = <&pd_lvds0_i2c0>; 1806 power-domains = <&pd_lvds0_i2c0>;
1781 status = "disabled"; 1807 status = "disabled";
1782 }; 1808 };
1783 1809
1784 irqsteer_lvds1: irqsteer@572400000 { 1810 irqsteer_lvds1: irqsteer@572400000 {
1785 compatible = "nxp,imx-irqsteer"; 1811 compatible = "nxp,imx-irqsteer";
1786 reg = <0x0 0x57240000 0x0 0x1000>; 1812 reg = <0x0 0x57240000 0x0 0x1000>;
1787 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1813 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1788 interrupt-controller; 1814 interrupt-controller;
1789 interrupt-parent = <&gic>; 1815 interrupt-parent = <&gic>;
1790 #interrupt-cells = <2>; 1816 #interrupt-cells = <2>;
1791 clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>; 1817 clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>;
1792 clock-names = "ipg"; 1818 clock-names = "ipg";
1793 power-domains = <&pd_lvds1>; 1819 power-domains = <&pd_lvds1>;
1794 }; 1820 };
1795 1821
1796 i2c1_lvds1: i2c@57247000 { 1822 i2c1_lvds1: i2c@57247000 {
1797 compatible = "fsl,imx8qm-lpi2c"; 1823 compatible = "fsl,imx8qm-lpi2c";
1798 reg = <0x0 0x57247000 0x0 0x1000>; 1824 reg = <0x0 0x57247000 0x0 0x1000>;
1799 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 1825 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
1800 interrupt-parent = <&irqsteer_lvds1>; 1826 interrupt-parent = <&irqsteer_lvds1>;
1801 clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>, 1827 clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>,
1802 <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>; 1828 <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>;
1803 clock-names = "per", "ipg"; 1829 clock-names = "per", "ipg";
1804 assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; 1830 assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>;
1805 assigned-clock-rates = <24000000>; 1831 assigned-clock-rates = <24000000>;
1806 power-domains = <&pd_lvds1_i2c0>; 1832 power-domains = <&pd_lvds1_i2c0>;
1807 status = "disabled"; 1833 status = "disabled";
1808 }; 1834 };
1809 1835
1810 irqsteer_csi0: irqsteer@582200000 { 1836 irqsteer_csi0: irqsteer@582200000 {
1811 compatible = "nxp,imx-irqsteer"; 1837 compatible = "nxp,imx-irqsteer";
1812 reg = <0x0 0x58220000 0x0 0x1000>; 1838 reg = <0x0 0x58220000 0x0 0x1000>;
1813 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
1814 interrupt-controller; 1840 interrupt-controller;
1815 interrupt-parent = <&gic>; 1841 interrupt-parent = <&gic>;
1816 #interrupt-cells = <2>; 1842 #interrupt-cells = <2>;
1817 clocks = <&clk IMX8QM_CSI0_LIS_IPG_CLK>; 1843 clocks = <&clk IMX8QM_CSI0_LIS_IPG_CLK>;
1818 clock-names = "ipg"; 1844 clock-names = "ipg";
1819 power-domains = <&pd_csi0>; 1845 power-domains = <&pd_csi0>;
1820 }; 1846 };
1821 1847
1822 i2c0_mipi_csi0: i2c@58226000 { 1848 i2c0_mipi_csi0: i2c@58226000 {
1823 compatible = "fsl,imx8qm-lpi2c"; 1849 compatible = "fsl,imx8qm-lpi2c";
1824 reg = <0x0 0x58226000 0x0 0x1000>; 1850 reg = <0x0 0x58226000 0x0 0x1000>;
1825 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1851 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1826 interrupt-parent = <&irqsteer_csi0>; 1852 interrupt-parent = <&irqsteer_csi0>;
1827 clocks = <&clk IMX8QM_CSI0_I2C0_CLK>, 1853 clocks = <&clk IMX8QM_CSI0_I2C0_CLK>,
1828 <&clk IMX8QM_CSI0_I2C0_IPG_CLK>; 1854 <&clk IMX8QM_CSI0_I2C0_IPG_CLK>;
1829 clock-names = "per", "ipg"; 1855 clock-names = "per", "ipg";
1830 assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>; 1856 assigned-clocks = <&clk IMX8QM_CSI0_I2C0_CLK>;
1831 assigned-clock-rates = <24000000>; 1857 assigned-clock-rates = <24000000>;
1832 power-domains = <&pd_csi0_i2c0>; 1858 power-domains = <&pd_csi0_i2c0>;
1833 status = "disabled"; 1859 status = "disabled";
1834 }; 1860 };
1835 1861
1836 irqsteer_csi1: irqsteer@582400000 { 1862 irqsteer_csi1: irqsteer@582400000 {
1837 compatible = "nxp,imx-irqsteer"; 1863 compatible = "nxp,imx-irqsteer";
1838 reg = <0x0 0x58240000 0x0 0x1000>; 1864 reg = <0x0 0x58240000 0x0 0x1000>;
1839 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1865 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1840 interrupt-controller; 1866 interrupt-controller;
1841 interrupt-parent = <&gic>; 1867 interrupt-parent = <&gic>;
1842 #interrupt-cells = <2>; 1868 #interrupt-cells = <2>;
1843 clocks = <&clk IMX8QM_CSI1_LIS_IPG_CLK>; 1869 clocks = <&clk IMX8QM_CSI1_LIS_IPG_CLK>;
1844 clock-names = "ipg"; 1870 clock-names = "ipg";
1845 power-domains = <&pd_csi1>; 1871 power-domains = <&pd_csi1>;
1846 }; 1872 };
1847 1873
1848 i2c0_mipi_csi1: i2c@58246000 { 1874 i2c0_mipi_csi1: i2c@58246000 {
1849 compatible = "fsl,imx8qm-lpi2c"; 1875 compatible = "fsl,imx8qm-lpi2c";
1850 reg = <0x0 0x58246000 0x0 0x1000>; 1876 reg = <0x0 0x58246000 0x0 0x1000>;
1851 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1877 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1852 interrupt-parent = <&irqsteer_csi1>; 1878 interrupt-parent = <&irqsteer_csi1>;
1853 clocks = <&clk IMX8QM_CSI1_I2C0_CLK>, 1879 clocks = <&clk IMX8QM_CSI1_I2C0_CLK>,
1854 <&clk IMX8QM_CSI1_I2C0_IPG_CLK>; 1880 <&clk IMX8QM_CSI1_I2C0_IPG_CLK>;
1855 clock-names = "per", "ipg"; 1881 clock-names = "per", "ipg";
1856 assigned-clocks = <&clk IMX8QM_CSI1_I2C0_CLK>; 1882 assigned-clocks = <&clk IMX8QM_CSI1_I2C0_CLK>;
1857 assigned-clock-rates = <24000000>; 1883 assigned-clock-rates = <24000000>;
1858 power-domains = <&pd_csi1_i2c0>; 1884 power-domains = <&pd_csi1_i2c0>;
1859 status = "disabled"; 1885 status = "disabled";
1860 }; 1886 };
1861 1887
1862 irqsteer_dsi0: irqsteer@56220000 { 1888 irqsteer_dsi0: irqsteer@56220000 {
1863 compatible = "nxp,imx-irqsteer"; 1889 compatible = "nxp,imx-irqsteer";
1864 reg = <0x0 0x56220000 0x0 0x1000>; 1890 reg = <0x0 0x56220000 0x0 0x1000>;
1865 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1891 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1866 interrupt-controller; 1892 interrupt-controller;
1867 interrupt-parent = <&gic>; 1893 interrupt-parent = <&gic>;
1868 #interrupt-cells = <2>; 1894 #interrupt-cells = <2>;
1869 clocks = <&clk IMX8QM_DSI0_LIS_IPG_CLK>; 1895 clocks = <&clk IMX8QM_DSI0_LIS_IPG_CLK>;
1870 clock-names = "ipg"; 1896 clock-names = "ipg";
1871 power-domains = <&pd_mipi0>; 1897 power-domains = <&pd_mipi0>;
1872 }; 1898 };
1873 1899
1874 i2c0_mipi_dsi0: i2c@56226000 { 1900 i2c0_mipi_dsi0: i2c@56226000 {
1875 compatible = "fsl,imx8qm-lpi2c"; 1901 compatible = "fsl,imx8qm-lpi2c";
1876 reg = <0x0 0x56226000 0x0 0x1000>; 1902 reg = <0x0 0x56226000 0x0 0x1000>;
1877 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1903 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1878 interrupt-parent = <&irqsteer_dsi0>; 1904 interrupt-parent = <&irqsteer_dsi0>;
1879 clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>, 1905 clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>,
1880 <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>; 1906 <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>;
1881 clock-names = "per", "ipg"; 1907 clock-names = "per", "ipg";
1882 assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>; 1908 assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>;
1883 assigned-clock-rates = <24000000>; 1909 assigned-clock-rates = <24000000>;
1884 power-domains = <&pd_mipi0_i2c0>; 1910 power-domains = <&pd_mipi0_i2c0>;
1885 status = "disabled"; 1911 status = "disabled";
1886 }; 1912 };
1887 1913
1888 mipi0: mipi@56220000 { 1914 mipi0: mipi@56220000 {
1889 compatible = "fsl,imx8qm-mipi_dsi"; 1915 compatible = "fsl,imx8qm-mipi_dsi";
1890 reg = <0x0 0x56220000 0x0 0x10000>; 1916 reg = <0x0 0x56220000 0x0 0x10000>;
1891 interrupts = <0 59 4>; 1917 interrupts = <0 59 4>;
1892 fsl,irq-steer = <0x56220000>; 1918 fsl,irq-steer = <0x56220000>;
1893 fsl,irq-num = <0x10000>; 1919 fsl,irq-num = <0x10000>;
1894 clocks = 1920 clocks =
1895 <&clk IMX8QM_MIPI0_PXL_CLK>, 1921 <&clk IMX8QM_MIPI0_PXL_CLK>,
1896 <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, 1922 <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,
1897 <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; 1923 <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;
1898 clock-names = 1924 clock-names =
1899 "clk_pixel","clk_tx_esc", "clk_rx_esc"; 1925 "clk_pixel","clk_tx_esc", "clk_rx_esc";
1900 power-domains = <&pd_mipi0>; 1926 power-domains = <&pd_mipi0>;
1901 instance = <0>; 1927 instance = <0>;
1902 data_lanes = <4>; 1928 data_lanes = <4>;
1903 virtual_ch = <0>; 1929 virtual_ch = <0>;
1904 dpi_fmt = <5>; 1930 dpi_fmt = <5>;
1905 status = "disabled"; 1931 status = "disabled";
1906 }; 1932 };
1907 1933
1908 mipi1: mipi@57220000 { 1934 mipi1: mipi@57220000 {
1909 compatible = "fsl,imx8qm-mipi_dsi"; 1935 compatible = "fsl,imx8qm-mipi_dsi";
1910 reg = <0x0 0x57220000 0x0 0x10000>; 1936 reg = <0x0 0x57220000 0x0 0x10000>;
1911 interrupts = <0 60 4>; 1937 interrupts = <0 60 4>;
1912 fsl,irq-steer = <0x57220000>; 1938 fsl,irq-steer = <0x57220000>;
1913 fsl,irq-num = <0x10000>; 1939 fsl,irq-num = <0x10000>;
1914 clocks = 1940 clocks =
1915 <&clk IMX8QM_MIPI1_PXL_CLK>, 1941 <&clk IMX8QM_MIPI1_PXL_CLK>,
1916 <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>, 1942 <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>,
1917 <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>; 1943 <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>;
1918 clock-names = 1944 clock-names =
1919 "clk_pixel", "clk_tx_esc", "clk_rx_esc"; 1945 "clk_pixel", "clk_tx_esc", "clk_rx_esc";
1920 power-domains = <&pd_mipi1>; 1946 power-domains = <&pd_mipi1>;
1921 instance = <1>; 1947 instance = <1>;
1922 data_lanes = <4>; 1948 data_lanes = <4>;
1923 virtual_ch = <0>; 1949 virtual_ch = <0>;
1924 dpi_fmt = <5>; 1950 dpi_fmt = <5>;
1925 status = "disabled"; 1951 status = "disabled";
1926 }; 1952 };
1927 1953
1928 lpspi0: lpspi@5a000000 { 1954 lpspi0: lpspi@5a000000 {
1929 compatible = "fsl,imx7ulp-spi"; 1955 compatible = "fsl,imx7ulp-spi";
1930 reg = <0x0 0x5a000000 0x0 0x10000>; 1956 reg = <0x0 0x5a000000 0x0 0x10000>;
1931 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1957 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1932 interrupt-parent = <&gic>; 1958 interrupt-parent = <&gic>;
1933 clocks = <&clk IMX8QM_SPI0_CLK>; 1959 clocks = <&clk IMX8QM_SPI0_CLK>;
1934 clock-names = "ipg"; 1960 clock-names = "ipg";
1935 assigned-clocks = <&clk IMX8QM_SPI0_CLK>; 1961 assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
1936 assigned-clock-rates = <32000000>; 1962 assigned-clock-rates = <32000000>;
1937 power-domains = <&pd_dma_lpspi0>; 1963 power-domains = <&pd_dma_lpspi0>;
1938 status = "disabled"; 1964 status = "disabled";
1939 }; 1965 };
1940 1966
1941 lpuart0: serial@5a060000 { 1967 lpuart0: serial@5a060000 {
1942 compatible = "fsl,imx8qm-lpuart"; 1968 compatible = "fsl,imx8qm-lpuart";
1943 reg = <0x0 0x5a060000 0x0 0x1000>; 1969 reg = <0x0 0x5a060000 0x0 0x1000>;
1944 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1945 interrupt-parent = <&gic>; 1971 interrupt-parent = <&gic>;
1946 clocks = <&clk IMX8QM_UART0_CLK>, 1972 clocks = <&clk IMX8QM_UART0_CLK>,
1947 <&clk IMX8QM_UART0_IPG_CLK>; 1973 <&clk IMX8QM_UART0_IPG_CLK>;
1948 clock-names = "per", "ipg"; 1974 clock-names = "per", "ipg";
1949 assigned-clocks = <&clk IMX8QM_UART0_CLK>; 1975 assigned-clocks = <&clk IMX8QM_UART0_CLK>;
1950 assigned-clock-rates = <80000000>; 1976 assigned-clock-rates = <80000000>;
1951 power-domains = <&pd_dma_lpuart0>; 1977 power-domains = <&pd_dma_lpuart0>;
1952 status = "disabled"; 1978 status = "disabled";
1953 }; 1979 };
1954 1980
1955 lpuart1: serial@5a070000 { 1981 lpuart1: serial@5a070000 {
1956 compatible = "fsl,imx8qm-lpuart"; 1982 compatible = "fsl,imx8qm-lpuart";
1957 reg = <0x0 0x5a070000 0x0 0x1000>; 1983 reg = <0x0 0x5a070000 0x0 0x1000>;
1958 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 1984 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1959 interrupt-parent = <&gic>; 1985 interrupt-parent = <&gic>;
1960 clocks = <&clk IMX8QM_UART1_CLK>, 1986 clocks = <&clk IMX8QM_UART1_CLK>,
1961 <&clk IMX8QM_UART1_IPG_CLK>; 1987 <&clk IMX8QM_UART1_IPG_CLK>;
1962 clock-names = "per", "ipg"; 1988 clock-names = "per", "ipg";
1963 assigned-clocks = <&clk IMX8QM_UART1_CLK>; 1989 assigned-clocks = <&clk IMX8QM_UART1_CLK>;
1964 assigned-clock-rates = <80000000>; 1990 assigned-clock-rates = <80000000>;
1965 power-domains = <&pd_dma_lpuart1>; 1991 power-domains = <&pd_dma_lpuart1>;
1966 dma-names = "tx","rx"; 1992 dma-names = "tx","rx";
1967 dmas = <&edma0 15 0 0>, 1993 dmas = <&edma0 15 0 0>,
1968 <&edma0 14 0 1>; 1994 <&edma0 14 0 1>;
1969 status = "disabled"; 1995 status = "disabled";
1970 }; 1996 };
1971 1997
1972 lpuart2: serial@5a080000 { 1998 lpuart2: serial@5a080000 {
1973 compatible = "fsl,imx8qm-lpuart"; 1999 compatible = "fsl,imx8qm-lpuart";
1974 reg = <0x0 0x5a080000 0x0 0x1000>; 2000 reg = <0x0 0x5a080000 0x0 0x1000>;
1975 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 2001 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
1976 interrupt-parent = <&gic>; 2002 interrupt-parent = <&gic>;
1977 clocks = <&clk IMX8QM_UART2_CLK>, 2003 clocks = <&clk IMX8QM_UART2_CLK>,
1978 <&clk IMX8QM_UART2_IPG_CLK>; 2004 <&clk IMX8QM_UART2_IPG_CLK>;
1979 clock-names = "per", "ipg"; 2005 clock-names = "per", "ipg";
1980 assigned-clocks = <&clk IMX8QM_UART2_CLK>; 2006 assigned-clocks = <&clk IMX8QM_UART2_CLK>;
1981 assigned-clock-rates = <80000000>; 2007 assigned-clock-rates = <80000000>;
1982 power-domains = <&pd_dma_lpuart2>; 2008 power-domains = <&pd_dma_lpuart2>;
1983 dma-names = "tx","rx"; 2009 dma-names = "tx","rx";
1984 dmas = <&edma0 17 0 0>, 2010 dmas = <&edma0 17 0 0>,
1985 <&edma0 16 0 1>; 2011 <&edma0 16 0 1>;
1986 status = "disabled"; 2012 status = "disabled";
1987 }; 2013 };
1988 2014
1989 lpuart3: serial@5a090000 { 2015 lpuart3: serial@5a090000 {
1990 compatible = "fsl,imx8qm-lpuart"; 2016 compatible = "fsl,imx8qm-lpuart";
1991 reg = <0x0 0x5a090000 0x0 0x1000>; 2017 reg = <0x0 0x5a090000 0x0 0x1000>;
1992 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 2018 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1993 interrupt-parent = <&gic>; 2019 interrupt-parent = <&gic>;
1994 clocks = <&clk IMX8QM_UART3_CLK>, 2020 clocks = <&clk IMX8QM_UART3_CLK>,
1995 <&clk IMX8QM_UART3_IPG_CLK>; 2021 <&clk IMX8QM_UART3_IPG_CLK>;
1996 clock-names = "per", "ipg"; 2022 clock-names = "per", "ipg";
1997 assigned-clocks = <&clk IMX8QM_UART3_CLK>; 2023 assigned-clocks = <&clk IMX8QM_UART3_CLK>;
1998 assigned-clock-rates = <80000000>; 2024 assigned-clock-rates = <80000000>;
1999 power-domains = <&pd_dma_lpuart3>; 2025 power-domains = <&pd_dma_lpuart3>;
2000 dma-names = "tx","rx"; 2026 dma-names = "tx","rx";
2001 dmas = <&edma0 19 0 0>, 2027 dmas = <&edma0 19 0 0>,
2002 <&edma0 18 0 1>; 2028 <&edma0 18 0 1>;
2003 status = "disabled"; 2029 status = "disabled";
2004 }; 2030 };
2005 2031
2006 lpuart4: serial@5a0a0000 { 2032 lpuart4: serial@5a0a0000 {
2007 compatible = "fsl,imx8qm-lpuart"; 2033 compatible = "fsl,imx8qm-lpuart";
2008 reg = <0x0 0x5a0a0000 0x0 0x1000>; 2034 reg = <0x0 0x5a0a0000 0x0 0x1000>;
2009 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 2035 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
2010 interrupt-parent = <&gic>; 2036 interrupt-parent = <&gic>;
2011 clocks = <&clk IMX8QM_UART4_CLK>, 2037 clocks = <&clk IMX8QM_UART4_CLK>,
2012 <&clk IMX8QM_UART4_IPG_CLK>; 2038 <&clk IMX8QM_UART4_IPG_CLK>;
2013 clock-names = "per", "ipg"; 2039 clock-names = "per", "ipg";
2014 assigned-clocks = <&clk IMX8QM_UART4_CLK>; 2040 assigned-clocks = <&clk IMX8QM_UART4_CLK>;
2015 assigned-clock-rates = <80000000>; 2041 assigned-clock-rates = <80000000>;
2016 power-domains = <&pd_dma_lpuart4>; 2042 power-domains = <&pd_dma_lpuart4>;
2017 dma-names = "tx","rx"; 2043 dma-names = "tx","rx";
2018 dmas = <&edma0 21 0 0>, 2044 dmas = <&edma0 21 0 0>,
2019 <&edma0 20 0 1>; 2045 <&edma0 20 0 1>;
2020 status = "disabled"; 2046 status = "disabled";
2021 }; 2047 };
2022 2048
2023 edma0: dma-controller@5a1f0000 { 2049 edma0: dma-controller@5a1f0000 {
2024 compatible = "fsl,imx8qm-edma"; 2050 compatible = "fsl,imx8qm-edma";
2025 reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ 2051 reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
2026 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ 2052 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
2027 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ 2053 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
2028 <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */ 2054 <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */
2029 <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ 2055 <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
2030 <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */ 2056 <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */
2031 <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ 2057 <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
2032 <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */ 2058 <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */
2033 <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ 2059 <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
2034 <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ 2060 <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
2035 #dma-cells = <3>; 2061 #dma-cells = <3>;
2036 dma-channels = <10>; 2062 dma-channels = <10>;
2037 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2063 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2038 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 2072 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
2047 interrupt-names = "edma-chan12-tx", "edma-chan13-tx", 2073 interrupt-names = "edma-chan12-tx", "edma-chan13-tx",
2048 "edma-chan14-tx", "edma-chan15-tx", 2074 "edma-chan14-tx", "edma-chan15-tx",
2049 "edma-chan16-tx", "edma-chan17-tx", 2075 "edma-chan16-tx", "edma-chan17-tx",
2050 "edma-chan18-tx", "edma-chan19-tx", 2076 "edma-chan18-tx", "edma-chan19-tx",
2051 "edma-chan20-tx", "edma-chan21-tx"; 2077 "edma-chan20-tx", "edma-chan21-tx";
2052 status = "okay"; 2078 status = "okay";
2053 }; 2079 };
2054 2080
2055 edma2: dma-controller@591F0000 { 2081 edma2: dma-controller@591F0000 {
2056 compatible = "fsl,imx8qm-adma"; 2082 compatible = "fsl,imx8qm-adma";
2057 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ 2083 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
2058 <0x0 0x59210000 0x0 0x10000>, 2084 <0x0 0x59210000 0x0 0x10000>,
2059 <0x0 0x59220000 0x0 0x10000>, 2085 <0x0 0x59220000 0x0 0x10000>,
2060 <0x0 0x59230000 0x0 0x10000>, 2086 <0x0 0x59230000 0x0 0x10000>,
2061 <0x0 0x59240000 0x0 0x10000>, 2087 <0x0 0x59240000 0x0 0x10000>,
2062 <0x0 0x59250000 0x0 0x10000>, 2088 <0x0 0x59250000 0x0 0x10000>,
2063 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ 2089 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
2064 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ 2090 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
2065 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ 2091 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
2066 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ 2092 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
2067 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ 2093 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
2068 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ 2094 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
2069 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ 2095 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
2070 <0x0 0x592f0000 0x0 0x10000>; /* sai1 tx */ 2096 <0x0 0x592f0000 0x0 0x10000>; /* sai1 tx */
2071 #dma-cells = <3>; 2097 #dma-cells = <3>;
2072 shared-interrupt; 2098 shared-interrupt;
2073 dma-channels = <14>; 2099 dma-channels = <14>;
2074 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ 2100 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
2075 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2076 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
2077 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
2078 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
2080 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ 2106 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
2081 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2082 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 2108 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
2083 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 2110 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
2085 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 2112 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
2087 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 2113 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
2088 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */ 2114 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */
2089 "edma-chan2-tx", "edma-chan3-tx", 2115 "edma-chan2-tx", "edma-chan3-tx",
2090 "edma-chan4-tx", "edma-chan5-tx", 2116 "edma-chan4-tx", "edma-chan5-tx",
2091 "edma-chan6-tx", "edma-chan7-tx", /* esai0 */ 2117 "edma-chan6-tx", "edma-chan7-tx", /* esai0 */
2092 "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */ 2118 "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */
2093 "edma-chan12-tx", "edma-chan13-tx", /* sai0 */ 2119 "edma-chan12-tx", "edma-chan13-tx", /* sai0 */
2094 "edma-chan14-tx", "edma-chan15-tx"; /* sai1 */ 2120 "edma-chan14-tx", "edma-chan15-tx"; /* sai1 */
2095 status = "okay"; 2121 status = "okay";
2096 }; 2122 };
2097 2123
2098 edma3: dma-controller@599F0000 { 2124 edma3: dma-controller@599F0000 {
2099 compatible = "fsl,imx8qm-adma"; 2125 compatible = "fsl,imx8qm-adma";
2100 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ 2126 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
2101 <0x0 0x59A10000 0x0 0x10000>, 2127 <0x0 0x59A10000 0x0 0x10000>,
2102 <0x0 0x59A20000 0x0 0x10000>, 2128 <0x0 0x59A20000 0x0 0x10000>,
2103 <0x0 0x59A30000 0x0 0x10000>, 2129 <0x0 0x59A30000 0x0 0x10000>,
2104 <0x0 0x59A40000 0x0 0x10000>, 2130 <0x0 0x59A40000 0x0 0x10000>,
2105 <0x0 0x59A50000 0x0 0x10000>, 2131 <0x0 0x59A50000 0x0 0x10000>,
2106 <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */ 2132 <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */
2107 <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */ 2133 <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */
2108 <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */ 2134 <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */
2109 #dma-cells = <3>; 2135 #dma-cells = <3>;
2110 shared-interrupt; 2136 shared-interrupt;
2111 dma-channels = <9>; 2137 dma-channels = <9>;
2112 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */ 2138 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */
2113 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2118 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */ 2144 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
2119 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */ 2146 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
2121 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */ 2147 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */
2122 "edma-chan2-tx", "edma-chan3-tx", 2148 "edma-chan2-tx", "edma-chan3-tx",
2123 "edma-chan4-tx", "edma-chan5-tx", 2149 "edma-chan4-tx", "edma-chan5-tx",
2124 "edma-chan8-tx", "edma-chan9-tx", /* sai6 */ 2150 "edma-chan8-tx", "edma-chan9-tx", /* sai6 */
2125 "edma-chan10-tx"; /* sai7 */ 2151 "edma-chan10-tx"; /* sai7 */
2126 status = "okay"; 2152 status = "okay";
2127 }; 2153 };
2128 2154
2129 gpt0: gpt0@5d140000 { 2155 gpt0: gpt0@5d140000 {
2130 compatible = "fsl,imx8qm-gpt"; 2156 compatible = "fsl,imx8qm-gpt";
2131 reg = <0x0 0x5d140000 0x0 0x4000>; 2157 reg = <0x0 0x5d140000 0x0 0x4000>;
2132 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2158 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2133 clocks = <&clk IMX8QM_GPT0_CLK>, <&clk IMX8QM_GPT_3M>; 2159 clocks = <&clk IMX8QM_GPT0_CLK>, <&clk IMX8QM_GPT_3M>;
2134 clock-names = "ipg", "per"; 2160 clock-names = "ipg", "per";
2135 power-domains = <&pd_lsio_gpt0>; 2161 power-domains = <&pd_lsio_gpt0>;
2136 }; 2162 };
2137 2163
2138 gpu_3d0: gpu@53100000 { 2164 gpu_3d0: gpu@53100000 {
2139 compatible = "fsl,imx8-gpu"; 2165 compatible = "fsl,imx8-gpu";
2140 reg = <0x0 0x53100000 0 0x40000>; 2166 reg = <0x0 0x53100000 0 0x40000>;
2141 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2167 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
2142 clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; 2168 clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>;
2143 clock-names = "core", "shader"; 2169 clock-names = "core", "shader";
2144 assigned-clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>; 2170 assigned-clocks = <&clk IMX8QM_GPU0_CORE_CLK>, <&clk IMX8QM_GPU0_SHADER_CLK>;
2145 assigned-clock-rates = <800000000>, <1000000000>; 2171 assigned-clock-rates = <800000000>, <1000000000>;
2146 fsl,sc_gpu_pid = <SC_R_GPU_0_PID0>; 2172 fsl,sc_gpu_pid = <SC_R_GPU_0_PID0>;
2147 power-domains = <&pd_gpu0>; 2173 power-domains = <&pd_gpu0>;
2148 status = "disabled"; 2174 status = "disabled";
2149 }; 2175 };
2150 2176
2151 gpu_3d1: gpu@54100000 { 2177 gpu_3d1: gpu@54100000 {
2152 compatible = "fsl,imx8-gpu"; 2178 compatible = "fsl,imx8-gpu";
2153 reg = <0x0 0x54100000 0x0 0x40000>; 2179 reg = <0x0 0x54100000 0x0 0x40000>;
2154 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 2180 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
2155 clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; 2181 clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>;
2156 clock-names = "core", "shader"; 2182 clock-names = "core", "shader";
2157 assigned-clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>; 2183 assigned-clocks = <&clk IMX8QM_GPU1_CORE_CLK>, <&clk IMX8QM_GPU1_SHADER_CLK>;
2158 assigned-clock-rates = <800000000>, <1000000000>; 2184 assigned-clock-rates = <800000000>, <1000000000>;
2159 fsl,sc_gpu_pid = <SC_R_GPU_1_PID0>; 2185 fsl,sc_gpu_pid = <SC_R_GPU_1_PID0>;
2160 power-domains = <&pd_gpu1>; 2186 power-domains = <&pd_gpu1>;
2161 status = "disabled"; 2187 status = "disabled";
2162 }; 2188 };
2163 2189
2164 imx8_gpu_ss: imx8_gpu_ss { 2190 imx8_gpu_ss: imx8_gpu_ss {
2165 compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss"; 2191 compatible = "fsl,imx8qm-gpu", "fsl,imx8-gpu-ss";
2166 cores = <&gpu_3d0>, <&gpu_3d1>; 2192 cores = <&gpu_3d0>, <&gpu_3d1>;
2167 reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; 2193 reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>;
2168 reg-names = "phys_baseaddr", "contiguous_mem"; 2194 reg-names = "phys_baseaddr", "contiguous_mem";
2169 status = "disabled"; 2195 status = "disabled";
2170 }; 2196 };
2171 2197
2172 mlb: mlb@5B060000 { 2198 mlb: mlb@5B060000 {
2173 compatible = "fsl,imx6q-mlb150"; 2199 compatible = "fsl,imx6q-mlb150";
2174 reg = <0x0 0x5B060000 0x0 0x10000>; 2200 reg = <0x0 0x5B060000 0x0 0x10000>;
2175 interrupt-parent = <&gic>; 2201 interrupt-parent = <&gic>;
2176 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, 2202 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
2177 <0 266 IRQ_TYPE_LEVEL_HIGH>; 2203 <0 266 IRQ_TYPE_LEVEL_HIGH>;
2178 clocks = <&clk IMX8QM_MLB_CLK>, 2204 clocks = <&clk IMX8QM_MLB_CLK>,
2179 <&clk IMX8QM_MLB_HCLK>, 2205 <&clk IMX8QM_MLB_HCLK>,
2180 <&clk IMX8QM_MLB_IPG_CLK>; 2206 <&clk IMX8QM_MLB_IPG_CLK>;
2181 clock-names = "mlb", "hclk", "ipg"; 2207 clock-names = "mlb", "hclk", "ipg";
2182 assigned-clocks = <&clk IMX8QM_MLB_CLK>, 2208 assigned-clocks = <&clk IMX8QM_MLB_CLK>,
2183 <&clk IMX8QM_MLB_HCLK>, 2209 <&clk IMX8QM_MLB_HCLK>,
2184 <&clk IMX8QM_MLB_IPG_CLK>; 2210 <&clk IMX8QM_MLB_IPG_CLK>;
2185 assigned-clock-rates = <333333333>, <333333333>, <83333333>; 2211 assigned-clock-rates = <333333333>, <333333333>, <83333333>;
2186 power-domains = <&pd_conn_mlb0>; 2212 power-domains = <&pd_conn_mlb0>;
2187 status = "disabled"; 2213 status = "disabled";
2188 }; 2214 };
2189 2215
2190 usdhc1: usdhc@5b010000 { 2216 usdhc1: usdhc@5b010000 {
2191 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 2217 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
2192 interrupt-parent = <&gic>; 2218 interrupt-parent = <&gic>;
2193 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 2219 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
2194 reg = <0x0 0x5b010000 0x0 0x10000>; 2220 reg = <0x0 0x5b010000 0x0 0x10000>;
2195 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, 2221 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
2196 <&clk IMX8QM_SDHC0_CLK>, 2222 <&clk IMX8QM_SDHC0_CLK>,
2197 <&clk IMX8QM_CLK_DUMMY>; 2223 <&clk IMX8QM_CLK_DUMMY>;
2198 clock-names = "ipg", "per", "ahb"; 2224 clock-names = "ipg", "per", "ahb";
2199 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; 2225 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
2200 assigned-clock-rates = <400000000>; 2226 assigned-clock-rates = <400000000>;
2201 power-domains = <&pd_conn_sdch0>; 2227 power-domains = <&pd_conn_sdch0>;
2202 fsl,tuning-start-tap = <20>; 2228 fsl,tuning-start-tap = <20>;
2203 fsl,tuning-step= <2>; 2229 fsl,tuning-step= <2>;
2204 status = "disabled"; 2230 status = "disabled";
2205 }; 2231 };
2206 2232
2207 usdhc2: usdhc@5b020000 { 2233 usdhc2: usdhc@5b020000 {
2208 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 2234 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
2209 interrupt-parent = <&gic>; 2235 interrupt-parent = <&gic>;
2210 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 2236 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
2211 reg = <0x0 0x5b020000 0x0 0x10000>; 2237 reg = <0x0 0x5b020000 0x0 0x10000>;
2212 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, 2238 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
2213 <&clk IMX8QM_SDHC1_CLK>, 2239 <&clk IMX8QM_SDHC1_CLK>,
2214 <&clk IMX8QM_CLK_DUMMY>; 2240 <&clk IMX8QM_CLK_DUMMY>;
2215 clock-names = "ipg", "per", "ahb"; 2241 clock-names = "ipg", "per", "ahb";
2216 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; 2242 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
2217 assigned-clock-rates = <200000000>; 2243 assigned-clock-rates = <200000000>;
2218 power-domains = <&pd_conn_sdch1>; 2244 power-domains = <&pd_conn_sdch1>;
2219 fsl,tuning-start-tap = <20>; 2245 fsl,tuning-start-tap = <20>;
2220 fsl,tuning-step= <2>; 2246 fsl,tuning-step= <2>;
2221 status = "disabled"; 2247 status = "disabled";
2222 }; 2248 };
2223 2249
2224 usdhc3: usdhc@5b030000 { 2250 usdhc3: usdhc@5b030000 {
2225 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 2251 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
2226 interrupt-parent = <&gic>; 2252 interrupt-parent = <&gic>;
2227 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 2253 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
2228 reg = <0x0 0x5b030000 0x0 0x10000>; 2254 reg = <0x0 0x5b030000 0x0 0x10000>;
2229 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, 2255 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
2230 <&clk IMX8QM_SDHC2_CLK>, 2256 <&clk IMX8QM_SDHC2_CLK>,
2231 <&clk IMX8QM_CLK_DUMMY>; 2257 <&clk IMX8QM_CLK_DUMMY>;
2232 clock-names = "ipg", "per", "ahb"; 2258 clock-names = "ipg", "per", "ahb";
2233 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; 2259 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
2234 assigned-clock-rates = <200000000>; 2260 assigned-clock-rates = <200000000>;
2235 power-domains = <&pd_conn_sdch2>; 2261 power-domains = <&pd_conn_sdch2>;
2236 fsl,tuning-start-tap = <20>; 2262 fsl,tuning-start-tap = <20>;
2237 fsl,tuning-step = <2>; 2263 fsl,tuning-step = <2>;
2238 status = "disabled"; 2264 status = "disabled";
2239 }; 2265 };
2240 2266
2241 fec1: ethernet@5b040000 { 2267 fec1: ethernet@5b040000 {
2242 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; 2268 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
2243 reg = <0x0 0x5b040000 0x0 0x10000>; 2269 reg = <0x0 0x5b040000 0x0 0x10000>;
2244 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2270 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 2273 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
2248 clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>, 2274 clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
2249 <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>; 2275 <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>;
2250 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 2276 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
2251 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, 2277 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
2252 <&clk IMX8QM_ENET0_REF_DIV>, 2278 <&clk IMX8QM_ENET0_REF_DIV>,
2253 <&clk IMX8QM_ENET0_PTP_CLK>; 2279 <&clk IMX8QM_ENET0_PTP_CLK>;
2254 assigned-clock-rates = <250000000>, <125000000>, <125000000>; 2280 assigned-clock-rates = <250000000>, <125000000>, <125000000>;
2255 fsl,num-tx-queues=<3>; 2281 fsl,num-tx-queues=<3>;
2256 fsl,num-rx-queues=<3>; 2282 fsl,num-rx-queues=<3>;
2257 power-domains = <&pd_conn_enet0>; 2283 power-domains = <&pd_conn_enet0>;
2258 iommus = <&smmu 0x12 0x7f80>; 2284 iommus = <&smmu 0x12 0x7f80>;
2259 status = "disabled"; 2285 status = "disabled";
2260 }; 2286 };
2261 2287
2262 fec2: ethernet@5b050000 { 2288 fec2: ethernet@5b050000 {
2263 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; 2289 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
2264 reg = <0x0 0x5b050000 0x0 0x10000>; 2290 reg = <0x0 0x5b050000 0x0 0x10000>;
2265 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2291 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2266 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2267 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2268 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2294 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2269 clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>, 2295 clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
2270 <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>; 2296 <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>;
2271 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 2297 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
2272 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, 2298 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
2273 <&clk IMX8QM_ENET1_REF_DIV>, 2299 <&clk IMX8QM_ENET1_REF_DIV>,
2274 <&clk IMX8QM_ENET1_PTP_CLK>; 2300 <&clk IMX8QM_ENET1_PTP_CLK>;
2275 assigned-clock-rates = <250000000>, <125000000>, <125000000>; 2301 assigned-clock-rates = <250000000>, <125000000>, <125000000>;
2276 fsl,num-tx-queues=<3>; 2302 fsl,num-tx-queues=<3>;
2277 fsl,num-rx-queues=<3>; 2303 fsl,num-rx-queues=<3>;
2278 power-domains = <&pd_conn_enet1>; 2304 power-domains = <&pd_conn_enet1>;
2279 iommus = <&smmu 0x12 0x7f80>; 2305 iommus = <&smmu 0x12 0x7f80>;
2280 status = "disabled"; 2306 status = "disabled";
2281 }; 2307 };
2282 2308
2283 usbmisc1: usbmisc@5b0d0200 { 2309 usbmisc1: usbmisc@5b0d0200 {
2284 #index-cells = <1>; 2310 #index-cells = <1>;
2285 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 2311 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
2286 reg = <0x0 0x5b0d0200 0x0 0x200>; 2312 reg = <0x0 0x5b0d0200 0x0 0x200>;
2287 }; 2313 };
2288 2314
2289 usbphy1: usbphy@0x5b100000 { 2315 usbphy1: usbphy@0x5b100000 {
2290 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 2316 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
2291 reg = <0x0 0x5b100000 0x0 0x200>; 2317 reg = <0x0 0x5b100000 0x0 0x200>;
2292 clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; 2318 clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>;
2293 power-domains = <&pd_conn_usbotg0_phy>; 2319 power-domains = <&pd_conn_usbotg0_phy>;
2294 2320
2295 }; 2321 };
2296 2322
2297 usbotg1: usb@5b0d0000 { 2323 usbotg1: usb@5b0d0000 {
2298 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 2324 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
2299 reg = <0x0 0x5b0d0000 0x0 0x200>; 2325 reg = <0x0 0x5b0d0000 0x0 0x200>;
2300 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 2326 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
2301 fsl,usbphy = <&usbphy1>; 2327 fsl,usbphy = <&usbphy1>;
2302 fsl,usbmisc = <&usbmisc1 0>; 2328 fsl,usbmisc = <&usbmisc1 0>;
2303 clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; 2329 clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>;
2304 phy-clkgate-delay-us = <400>; 2330 phy-clkgate-delay-us = <400>;
2305 status = "disabled"; 2331 status = "disabled";
2306 #stream-id-cells = <1>; 2332 #stream-id-cells = <1>;
2307 power-domains = <&pd_conn_usbotg0>; 2333 power-domains = <&pd_conn_usbotg0>;
2308 }; 2334 };
2309 2335
2310 usb2_phy: phy@0x5b160000 { 2336 usb2_phy: phy@0x5b160000 {
2311 compatible = "fsl,imx8-usb-phy"; 2337 compatible = "fsl,imx8-usb-phy";
2312 reg = <0x0 0x5b160000 0x0 0x10000>; 2338 reg = <0x0 0x5b160000 0x0 0x10000>;
2313 power-domains = <&pd_conn_usb2_phy>; 2339 power-domains = <&pd_conn_usb2_phy>;
2314 }; 2340 };
2315 2341
2316 usb2: usb@0x5b110000 { 2342 usb2: usb@0x5b110000 {
2317 compatible = "fsl,imx8-usb3"; 2343 compatible = "fsl,imx8-usb3";
2318 reg = <0x0 0x5b110000 0x0 0x38000>; 2344 reg = <0x0 0x5b110000 0x0 0x38000>;
2319 fsl,usbphy = <&usb2_phy>; 2345 fsl,usbphy = <&usb2_phy>;
2320 status = "disabled"; 2346 status = "disabled";
2321 power-domains = <&pd_conn_usb2>; 2347 power-domains = <&pd_conn_usb2>;
2322 }; 2348 };
2323 2349
2324 ddr_pmu0: ddr_pmu@5c020000 { 2350 ddr_pmu0: ddr_pmu@5c020000 {
2325 compatible = "fsl,imx8-ddr-pmu"; 2351 compatible = "fsl,imx8-ddr-pmu";
2326 reg = <0x0 0x5c020000 0x0 0x10000>; 2352 reg = <0x0 0x5c020000 0x0 0x10000>;
2327 interrupt-parent = <&gic>; 2353 interrupt-parent = <&gic>;
2328 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 2354 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
2329 }; 2355 };
2330 2356
2331 ddr_pmu1: ddr_pmu@5c120000 { 2357 ddr_pmu1: ddr_pmu@5c120000 {
2332 compatible = "fsl,imx8-ddr-pmu"; 2358 compatible = "fsl,imx8-ddr-pmu";
2333 reg = <0x0 0x5c120000 0x0 0x10000>; 2359 reg = <0x0 0x5c120000 0x0 0x10000>;
2334 interrupt-parent = <&gic>; 2360 interrupt-parent = <&gic>;
2335 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2361 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2336 }; 2362 };
2337 2363
2338 vpu: vpu@2c000000 { 2364 vpu: vpu@2c000000 {
2339 compatible = "nxp,imx8qm-vpu", "nxp,imx8x-vpu"; 2365 compatible = "nxp,imx8qm-vpu", "nxp,imx8x-vpu";
2340 reg = <0x0 0x2c000000 0x0 0x1000000>; 2366 reg = <0x0 0x2c000000 0x0 0x1000000>;
2341 reg-names = "iobase_vpu"; 2367 reg-names = "iobase_vpu";
2342 interrupts = <0 464 0x4>; 2368 interrupts = <0 464 0x4>;
2343 interrupt-names = "irq_vpu"; 2369 interrupt-names = "irq_vpu";
2344 clocks = <&clk IMX8QM_VPU_DDR_CLK>, 2370 clocks = <&clk IMX8QM_VPU_DDR_CLK>,
2345 <&clk IMX8QM_VPU_SYS_CLK>, 2371 <&clk IMX8QM_VPU_SYS_CLK>,
2346 <&clk IMX8QM_VPU_XUVI_CLK>, 2372 <&clk IMX8QM_VPU_XUVI_CLK>,
2347 <&clk IMX8QM_VPU_UART_CLK>; 2373 <&clk IMX8QM_VPU_UART_CLK>;
2348 clock-names = "clk_vpu_ddr", "clk_vpu_sys", 2374 clock-names = "clk_vpu_ddr", "clk_vpu_sys",
2349 "clk_vpu_xuvi", "clk_vpu_uart"; 2375 "clk_vpu_xuvi", "clk_vpu_uart";
2350 assigned-clocks = <&clk IMX8QM_VPU_DDR_CLK>, 2376 assigned-clocks = <&clk IMX8QM_VPU_DDR_CLK>,
2351 <&clk IMX8QM_VPU_SYS_CLK>, 2377 <&clk IMX8QM_VPU_SYS_CLK>,
2352 <&clk IMX8QM_VPU_XUVI_CLK>, 2378 <&clk IMX8QM_VPU_XUVI_CLK>,
2353 <&clk IMX8QM_VPU_UART_CLK>; 2379 <&clk IMX8QM_VPU_UART_CLK>;
2354 assigned-clock-rates = <800000000>, <600000000>, 2380 assigned-clock-rates = <800000000>, <600000000>,
2355 <600000000>, <80000000>; 2381 <600000000>, <80000000>;
2356 power-domains = <&pd_vpu_dec>; 2382 power-domains = <&pd_vpu_dec>;
2357 status = "disabled"; 2383 status = "disabled";
2358 }; 2384 };
2359 2385
2360 acm: acm@59e00000 { 2386 acm: acm@59e00000 {
2361 compatible = "nxp,imx8qm-acm"; 2387 compatible = "nxp,imx8qm-acm";
2362 reg = <0x0 0x59e00000 0x0 0x1D0000>; 2388 reg = <0x0 0x59e00000 0x0 0x1D0000>;
2363 status = "disabled"; 2389 status = "disabled";
2364 }; 2390 };
2365 2391
2366 esai0: esai@59010000 { 2392 esai0: esai@59010000 {
2367 compatible = "fsl,imx8qm-esai"; 2393 compatible = "fsl,imx8qm-esai";
2368 reg = <0x0 0x59010000 0x0 0x10000>; 2394 reg = <0x0 0x59010000 0x0 0x10000>;
2369 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 2395 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
2370 clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>, 2396 clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>,
2371 <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>, 2397 <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>,
2372 <&clk IMX8QM_CLK_DUMMY>, 2398 <&clk IMX8QM_CLK_DUMMY>,
2373 <&clk IMX8QM_CLK_DUMMY>; 2399 <&clk IMX8QM_CLK_DUMMY>;
2374 clock-names = "core", "extal", "fsys", "spba"; 2400 clock-names = "core", "extal", "fsys", "spba";
2375 dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; 2401 dmas = <&edma2 6 0 1>, <&edma2 7 0 0>;
2376 dma-names = "rx", "tx"; 2402 dma-names = "rx", "tx";
2377 power-domains = <&pd_esai0>; 2403 power-domains = <&pd_esai0>;
2378 status = "disabled"; 2404 status = "disabled";
2379 }; 2405 };
2380 2406
2381 spdif0: spdif@59020000 { 2407 spdif0: spdif@59020000 {
2382 compatible = "fsl,imx8qm-spdif"; 2408 compatible = "fsl,imx8qm-spdif";
2383 reg = <0x0 0x59020000 0x0 0x10000>; 2409 reg = <0x0 0x59020000 0x0 0x10000>;
2384 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 2410 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
2385 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 2411 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
2386 clocks = <&clk IMX8QM_AUD_SPDIF_0_GCLKW>, /* core */ 2412 clocks = <&clk IMX8QM_AUD_SPDIF_0_GCLKW>, /* core */
2387 <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */ 2413 <&clk IMX8QM_CLK_DUMMY>, /* rxtx0 */
2388 <&clk IMX8QM_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ 2414 <&clk IMX8QM_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
2389 <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */ 2415 <&clk IMX8QM_CLK_DUMMY>, /* rxtx2 */
2390 <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */ 2416 <&clk IMX8QM_CLK_DUMMY>, /* rxtx3 */
2391 <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */ 2417 <&clk IMX8QM_CLK_DUMMY>, /* rxtx4 */
2392 <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */ 2418 <&clk IMX8QM_IPG_AUD_CLK_ROOT>, /* rxtx5 */
2393 <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */ 2419 <&clk IMX8QM_CLK_DUMMY>, /* rxtx6 */
2394 <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */ 2420 <&clk IMX8QM_CLK_DUMMY>, /* rxtx7 */
2395 <&clk IMX8QM_CLK_DUMMY>; /* spba */ 2421 <&clk IMX8QM_CLK_DUMMY>; /* spba */
2396 clock-names = "core", "rxtx0", 2422 clock-names = "core", "rxtx0",
2397 "rxtx1", "rxtx2", 2423 "rxtx1", "rxtx2",
2398 "rxtx3", "rxtx4", 2424 "rxtx3", "rxtx4",
2399 "rxtx5", "rxtx6", 2425 "rxtx5", "rxtx6",
2400 "rxtx7", "spba"; 2426 "rxtx7", "spba";
2401 dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; 2427 dmas = <&edma2 8 0 5>, <&edma2 9 0 4>;
2402 dma-names = "rx", "tx"; 2428 dma-names = "rx", "tx";
2403 power-domains = <&pd_spdif0>; 2429 power-domains = <&pd_spdif0>;
2404 status = "disabled"; 2430 status = "disabled";
2405 }; 2431 };
2406 2432
2407 sai1: sai@59050000 { 2433 sai1: sai@59050000 {
2408 compatible = "fsl,imx8qm-sai"; 2434 compatible = "fsl,imx8qm-sai";
2409 reg = <0x0 0x59050000 0x0 0x10000>; 2435 reg = <0x0 0x59050000 0x0 0x10000>;
2410 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 2436 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
2411 clocks = <&clk IMX8QM_AUD_SAI_1_IPG>, 2437 clocks = <&clk IMX8QM_AUD_SAI_1_IPG>,
2412 <&clk IMX8QM_CLK_DUMMY>, 2438 <&clk IMX8QM_CLK_DUMMY>,
2413 <&clk IMX8QM_AUD_SAI_1_MCLK>, 2439 <&clk IMX8QM_AUD_SAI_1_MCLK>,
2414 <&clk IMX8QM_CLK_DUMMY>, 2440 <&clk IMX8QM_CLK_DUMMY>,
2415 <&clk IMX8QM_CLK_DUMMY>; 2441 <&clk IMX8QM_CLK_DUMMY>;
2416 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2442 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2417 dma-names = "rx", "tx"; 2443 dma-names = "rx", "tx";
2418 dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; 2444 dmas = <&edma2 14 0 1>, <&edma2 15 0 0>;
2419 status = "disabled"; 2445 status = "disabled";
2420 power-domains = <&pd_sai1>; 2446 power-domains = <&pd_sai1>;
2421 }; 2447 };
2422 2448
2423 2449
2424 sai0: sai@59040000 { 2450 sai0: sai@59040000 {
2425 compatible = "fsl,imx8qm-sai"; 2451 compatible = "fsl,imx8qm-sai";
2426 reg = <0x0 0x59040000 0x0 0x10000>; 2452 reg = <0x0 0x59040000 0x0 0x10000>;
2427 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 2453 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
2428 clocks = <&clk IMX8QM_AUD_SAI_0_IPG>, 2454 clocks = <&clk IMX8QM_AUD_SAI_0_IPG>,
2429 <&clk IMX8QM_CLK_DUMMY>, 2455 <&clk IMX8QM_CLK_DUMMY>,
2430 <&clk IMX8QM_AUD_SAI_0_MCLK>, 2456 <&clk IMX8QM_AUD_SAI_0_MCLK>,
2431 <&clk IMX8QM_CLK_DUMMY>, 2457 <&clk IMX8QM_CLK_DUMMY>,
2432 <&clk IMX8QM_CLK_DUMMY>; 2458 <&clk IMX8QM_CLK_DUMMY>;
2433 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2459 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2434 dma-names = "rx", "tx"; 2460 dma-names = "rx", "tx";
2435 dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; 2461 dmas = <&edma2 12 0 1>, <&edma2 13 0 0>;
2436 status = "disabled"; 2462 status = "disabled";
2437 power-domains = <&pd_sai0>; 2463 power-domains = <&pd_sai0>;
2438 }; 2464 };
2439 2465
2440 sai6: sai@59820000 { 2466 sai6: sai@59820000 {
2441 compatible = "fsl,imx8qm-sai"; 2467 compatible = "fsl,imx8qm-sai";
2442 reg = <0x0 0x59820000 0x0 0x10000>; 2468 reg = <0x0 0x59820000 0x0 0x10000>;
2443 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 2469 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
2444 clocks = <&clk IMX8QM_AUD_SAI_6_IPG>, 2470 clocks = <&clk IMX8QM_AUD_SAI_6_IPG>,
2445 <&clk IMX8QM_CLK_DUMMY>, 2471 <&clk IMX8QM_CLK_DUMMY>,
2446 <&clk IMX8QM_AUD_SAI_6_MCLK>, 2472 <&clk IMX8QM_AUD_SAI_6_MCLK>,
2447 <&clk IMX8QM_CLK_DUMMY>, 2473 <&clk IMX8QM_CLK_DUMMY>,
2448 <&clk IMX8QM_CLK_DUMMY>; 2474 <&clk IMX8QM_CLK_DUMMY>;
2449 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2475 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2450 dma-names = "rx", "tx"; 2476 dma-names = "rx", "tx";
2451 dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; 2477 dmas = <&edma3 8 0 1>, <&edma3 9 0 0>;
2452 status = "disabled"; 2478 status = "disabled";
2453 power-domains = <&pd_sai6>; 2479 power-domains = <&pd_sai6>;
2454 }; 2480 };
2455 2481
2456 sai7: sai@59830000 { 2482 sai7: sai@59830000 {
2457 compatible = "fsl,imx8qm-sai"; 2483 compatible = "fsl,imx8qm-sai";
2458 reg = <0x0 0x59830000 0x0 0x10000>; 2484 reg = <0x0 0x59830000 0x0 0x10000>;
2459 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 2485 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
2460 clocks = <&clk IMX8QM_AUD_SAI_7_IPG>, 2486 clocks = <&clk IMX8QM_AUD_SAI_7_IPG>,
2461 <&clk IMX8QM_CLK_DUMMY>, 2487 <&clk IMX8QM_CLK_DUMMY>,
2462 <&clk IMX8QM_AUD_SAI_7_MCLK>, 2488 <&clk IMX8QM_AUD_SAI_7_MCLK>,
2463 <&clk IMX8QM_CLK_DUMMY>, 2489 <&clk IMX8QM_CLK_DUMMY>,
2464 <&clk IMX8QM_CLK_DUMMY>; 2490 <&clk IMX8QM_CLK_DUMMY>;
2465 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2491 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2466 dma-names = "tx"; 2492 dma-names = "tx";
2467 dmas = <&edma3 10 0 0>; 2493 dmas = <&edma3 10 0 0>;
2468 status = "disabled"; 2494 status = "disabled";
2469 power-domains = <&pd_sai7>; 2495 power-domains = <&pd_sai7>;
2470 }; 2496 };
2471 2497
2472 amix: amix@59840000 { 2498 amix: amix@59840000 {
2473 compatible = "fsl,imx8qm-amix"; 2499 compatible = "fsl,imx8qm-amix";
2474 reg = <0x0 0x59840000 0x0 0x10000>; 2500 reg = <0x0 0x59840000 0x0 0x10000>;
2475 clocks = <&clk IMX8QM_AUD_AMIX_IPG>; 2501 clocks = <&clk IMX8QM_AUD_AMIX_IPG>;
2476 clock-names = "ipg"; 2502 clock-names = "ipg";
2477 power-domains = <&pd_amix>; 2503 power-domains = <&pd_amix>;
2478 status = "disabled"; 2504 status = "disabled";
2479 }; 2505 };
2480 2506
2481 asrc0: asrc@59000000 { 2507 asrc0: asrc@59000000 {
2482 compatible = "fsl,imx8qm-asrc0"; 2508 compatible = "fsl,imx8qm-asrc0";
2483 reg = <0x0 0x59000000 0x0 0x10000>; 2509 reg = <0x0 0x59000000 0x0 0x10000>;
2484 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 2510 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2511 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2486 clocks = <&clk IMX8QM_AUD_ASRC_0_IPG>, 2512 clocks = <&clk IMX8QM_AUD_ASRC_0_IPG>,
2487 <&clk IMX8QM_AUD_ASRC_0_MEM>, 2513 <&clk IMX8QM_AUD_ASRC_0_MEM>,
2488 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, 2514 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
2489 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, 2515 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
2490 <&clk IMX8QM_CLK_DUMMY>, 2516 <&clk IMX8QM_CLK_DUMMY>,
2491 <&clk IMX8QM_CLK_DUMMY>, 2517 <&clk IMX8QM_CLK_DUMMY>,
2492 <&clk IMX8QM_CLK_DUMMY>, 2518 <&clk IMX8QM_CLK_DUMMY>,
2493 <&clk IMX8QM_CLK_DUMMY>, 2519 <&clk IMX8QM_CLK_DUMMY>,
2494 <&clk IMX8QM_CLK_DUMMY>, 2520 <&clk IMX8QM_CLK_DUMMY>,
2495 <&clk IMX8QM_CLK_DUMMY>, 2521 <&clk IMX8QM_CLK_DUMMY>,
2496 <&clk IMX8QM_CLK_DUMMY>, 2522 <&clk IMX8QM_CLK_DUMMY>,
2497 <&clk IMX8QM_CLK_DUMMY>, 2523 <&clk IMX8QM_CLK_DUMMY>,
2498 <&clk IMX8QM_CLK_DUMMY>, 2524 <&clk IMX8QM_CLK_DUMMY>,
2499 <&clk IMX8QM_CLK_DUMMY>, 2525 <&clk IMX8QM_CLK_DUMMY>,
2500 <&clk IMX8QM_CLK_DUMMY>, 2526 <&clk IMX8QM_CLK_DUMMY>,
2501 <&clk IMX8QM_CLK_DUMMY>, 2527 <&clk IMX8QM_CLK_DUMMY>,
2502 <&clk IMX8QM_CLK_DUMMY>, 2528 <&clk IMX8QM_CLK_DUMMY>,
2503 <&clk IMX8QM_CLK_DUMMY>, 2529 <&clk IMX8QM_CLK_DUMMY>,
2504 <&clk IMX8QM_CLK_DUMMY>; 2530 <&clk IMX8QM_CLK_DUMMY>;
2505 clock-names = "ipg", "mem", 2531 clock-names = "ipg", "mem",
2506 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 2532 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
2507 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 2533 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
2508 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 2534 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
2509 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 2535 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
2510 "spba"; 2536 "spba";
2511 dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, 2537 dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>,
2512 <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; 2538 <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>;
2513 dma-names = "rxa", "rxb", "rxc", 2539 dma-names = "rxa", "rxb", "rxc",
2514 "txa", "txb", "txc"; 2540 "txa", "txb", "txc";
2515 fsl,asrc-rate = <8000>; 2541 fsl,asrc-rate = <8000>;
2516 fsl,asrc-width = <16>; 2542 fsl,asrc-width = <16>;
2517 power-domains = <&pd_asrc0>; 2543 power-domains = <&pd_asrc0>;
2518 status = "disabled"; 2544 status = "disabled";
2519 }; 2545 };
2520 2546
2521 asrc1: asrc@59800000 { 2547 asrc1: asrc@59800000 {
2522 compatible = "fsl,imx8qm-asrc1"; 2548 compatible = "fsl,imx8qm-asrc1";
2523 reg = <0x0 0x59800000 0x0 0x10000>; 2549 reg = <0x0 0x59800000 0x0 0x10000>;
2524 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 2550 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
2525 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 2551 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
2526 clocks = <&clk IMX8QM_AUD_ASRC_1_IPG>, 2552 clocks = <&clk IMX8QM_AUD_ASRC_1_IPG>,
2527 <&clk IMX8QM_AUD_ASRC_1_MEM>, 2553 <&clk IMX8QM_AUD_ASRC_1_MEM>,
2528 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, 2554 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
2529 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, 2555 <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
2530 <&clk IMX8QM_CLK_DUMMY>, 2556 <&clk IMX8QM_CLK_DUMMY>,
2531 <&clk IMX8QM_CLK_DUMMY>, 2557 <&clk IMX8QM_CLK_DUMMY>,
2532 <&clk IMX8QM_CLK_DUMMY>, 2558 <&clk IMX8QM_CLK_DUMMY>,
2533 <&clk IMX8QM_CLK_DUMMY>, 2559 <&clk IMX8QM_CLK_DUMMY>,
2534 <&clk IMX8QM_CLK_DUMMY>, 2560 <&clk IMX8QM_CLK_DUMMY>,
2535 <&clk IMX8QM_CLK_DUMMY>, 2561 <&clk IMX8QM_CLK_DUMMY>,
2536 <&clk IMX8QM_CLK_DUMMY>, 2562 <&clk IMX8QM_CLK_DUMMY>,
2537 <&clk IMX8QM_CLK_DUMMY>, 2563 <&clk IMX8QM_CLK_DUMMY>,
2538 <&clk IMX8QM_CLK_DUMMY>, 2564 <&clk IMX8QM_CLK_DUMMY>,
2539 <&clk IMX8QM_CLK_DUMMY>, 2565 <&clk IMX8QM_CLK_DUMMY>,
2540 <&clk IMX8QM_CLK_DUMMY>, 2566 <&clk IMX8QM_CLK_DUMMY>,
2541 <&clk IMX8QM_CLK_DUMMY>, 2567 <&clk IMX8QM_CLK_DUMMY>,
2542 <&clk IMX8QM_CLK_DUMMY>, 2568 <&clk IMX8QM_CLK_DUMMY>,
2543 <&clk IMX8QM_CLK_DUMMY>, 2569 <&clk IMX8QM_CLK_DUMMY>,
2544 <&clk IMX8QM_CLK_DUMMY>; 2570 <&clk IMX8QM_CLK_DUMMY>;
2545 clock-names = "ipg", "mem", 2571 clock-names = "ipg", "mem",
2546 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 2572 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
2547 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 2573 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
2548 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 2574 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
2549 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 2575 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
2550 "spba"; 2576 "spba";
2551 dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, 2577 dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>,
2552 <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; 2578 <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>;
2553 dma-names = "rxa", "rxb", "rxc", 2579 dma-names = "rxa", "rxb", "rxc",
2554 "txa", "txb", "txc"; 2580 "txa", "txb", "txc";
2555 fsl,asrc-rate = <8000>; 2581 fsl,asrc-rate = <8000>;
2556 fsl,asrc-width = <16>; 2582 fsl,asrc-width = <16>;
2557 power-domains = <&pd_asrc1>; 2583 power-domains = <&pd_asrc1>;
2558 status = "disabled"; 2584 status = "disabled";
2559 }; 2585 };
2560 2586
2561 mqs: mqs@59850000 { 2587 mqs: mqs@59850000 {
2562 compatible = "fsl,imx8qm-mqs"; 2588 compatible = "fsl,imx8qm-mqs";
2563 reg = <0x0 0x59850000 0x0 0x10000>; 2589 reg = <0x0 0x59850000 0x0 0x10000>;
2564 clocks = <&clk IMX8QM_AUD_MQS_IPG>, 2590 clocks = <&clk IMX8QM_AUD_MQS_IPG>,
2565 <&clk IMX8QM_AUD_MQS_HMCLK>; 2591 <&clk IMX8QM_AUD_MQS_HMCLK>;
2566 clock-names = "core", "mclk"; 2592 clock-names = "core", "mclk";
2567 power-domains = <&pd_mqs0>; 2593 power-domains = <&pd_mqs0>;
2568 status = "disabled"; 2594 status = "disabled";
2569 }; 2595 };
2570 2596
2571 flexspi0: flexspi@05d120000 { 2597 flexspi0: flexspi@05d120000 {
2572 #address-cells = <1>; 2598 #address-cells = <1>;
2573 #size-cells = <0>; 2599 #size-cells = <0>;
2574 compatible = "fsl,imx8qm-flexspi"; 2600 compatible = "fsl,imx8qm-flexspi";
2575 reg = <0x0 0x5d120000 0x0 0x10000>, 2601 reg = <0x0 0x5d120000 0x0 0x10000>,
2576 <0x0 0x08000000 0x0 0x19ffffff>; 2602 <0x0 0x08000000 0x0 0x19ffffff>;
2577 reg-names = "FlexSPI", "FlexSPI-memory"; 2603 reg-names = "FlexSPI", "FlexSPI-memory";
2578 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2604 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2579 clocks = <&clk IMX8QM_FSPI0_CLK>, 2605 clocks = <&clk IMX8QM_FSPI0_CLK>,
2580 <&clk IMX8QM_FSPI0_CLK>; 2606 <&clk IMX8QM_FSPI0_CLK>;
2581 assigned-clock-rates = <29000000>,<29000000>; 2607 assigned-clock-rates = <29000000>,<29000000>;
2582 clock-names = "qspi_en", "qspi"; 2608 clock-names = "qspi_en", "qspi";
2583 power-domains = <&pd_lsio_flexspi0>; 2609 power-domains = <&pd_lsio_flexspi0>;
2584 status = "disabled"; 2610 status = "disabled";
2585 }; 2611 };
2586 2612
2587 display-subsystem { 2613 display-subsystem {
2588 compatible = "fsl,imx-display-subsystem"; 2614 compatible = "fsl,imx-display-subsystem";
2589 ports = <&dpu1_disp0>, <&dpu1_disp1>, 2615 ports = <&dpu1_disp0>, <&dpu1_disp1>,
2590 <&dpu2_disp0>, <&dpu2_disp1>; 2616 <&dpu2_disp0>, <&dpu2_disp1>;
2591 }; 2617 };
2592 2618
2593 dma_cap: dma_cap { 2619 dma_cap: dma_cap {
2594 compatible = "dma-capability"; 2620 compatible = "dma-capability";
2595 only-dma-mask32 = <1>; 2621 only-dma-mask32 = <1>;
2596 }; 2622 };
2597 2623
2598 hsio: hsio@5f080000 { 2624 hsio: hsio@5f080000 {
2599 compatible = "fsl,imx8qm-hsio", "syscon"; 2625 compatible = "fsl,imx8qm-hsio", "syscon";
2600 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ 2626 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
2601 }; 2627 };
2602 2628
2603 pciea: pcie@0x5f000000 { 2629 pciea: pcie@0x5f000000 {
2604 compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; 2630 compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
2605 reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */ 2631 reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */
2606 <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */ 2632 <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */
2607 reg-names = "dbi", "config"; 2633 reg-names = "dbi", "config";
2608 #address-cells = <3>; 2634 #address-cells = <3>;
2609 #size-cells = <2>; 2635 #size-cells = <2>;
2610 device_type = "pci"; 2636 device_type = "pci";
2611 ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ 2637 ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */
2612 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ 2638 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
2613 num-lanes = <1>; 2639 num-lanes = <1>;
2614 2640
2615 #interrupt-cells = <1>; 2641 #interrupt-cells = <1>;
2616 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 2642 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2617 interrupt-names = "msi"; 2643 interrupt-names = "msi";
2618 2644
2619 /* 2645 /*
2620 * Set these clocks in default, then clocks should be 2646 * Set these clocks in default, then clocks should be
2621 * refined for exact hw design of imx8 pcie. 2647 * refined for exact hw design of imx8 pcie.
2622 */ 2648 */
2623 clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, 2649 clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
2624 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, 2650 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
2625 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, 2651 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
2626 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; 2652 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>;
2627 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 2653 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
2628 2654
2629 interrupt-map-mask = <0 0 0 0x7>; 2655 interrupt-map-mask = <0 0 0 0x7>;
2630 interrupt-map = <0 0 0 1 &gic 0 73 4>, 2656 interrupt-map = <0 0 0 1 &gic 0 73 4>,
2631 <0 0 0 2 &gic 0 74 4>, 2657 <0 0 0 2 &gic 0 74 4>,
2632 <0 0 0 3 &gic 0 75 4>, 2658 <0 0 0 3 &gic 0 75 4>,
2633 <0 0 0 4 &gic 0 76 4>; 2659 <0 0 0 4 &gic 0 76 4>;
2634 power-domains = <&pd_pcie0>; 2660 power-domains = <&pd_pcie0>;
2635 fsl,max-link-speed = <3>; 2661 fsl,max-link-speed = <3>;
2636 hsio-cfg = <PCIEAX1PCIEBX1SATA>; 2662 hsio-cfg = <PCIEAX1PCIEBX1SATA>;
2637 hsio = <&hsio>; 2663 hsio = <&hsio>;
2638 ctrl-id = <0>; /* pciea */ 2664 ctrl-id = <0>; /* pciea */
2639 cpu-base-addr = <0x40000000>; 2665 cpu-base-addr = <0x40000000>;
2640 status = "disabled"; 2666 status = "disabled";
2641 }; 2667 };
2642 2668
2643 pcieb: pcie@0x5f010000 { 2669 pcieb: pcie@0x5f010000 {
2644 compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; 2670 compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
2645 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */ 2671 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */
2646 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ 2672 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
2647 reg-names = "dbi", "config"; 2673 reg-names = "dbi", "config";
2648 #address-cells = <3>; 2674 #address-cells = <3>;
2649 #size-cells = <2>; 2675 #size-cells = <2>;
2650 device_type = "pci"; 2676 device_type = "pci";
2651 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 2677 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
2652 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ 2678 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
2653 num-lanes = <1>; 2679 num-lanes = <1>;
2654 2680
2655 #interrupt-cells = <1>; 2681 #interrupt-cells = <1>;
2656 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2682 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2657 interrupt-names = "msi"; 2683 interrupt-names = "msi";
2658 2684
2659 /* 2685 /*
2660 * Set these clocks in default, then clocks should be 2686 * Set these clocks in default, then clocks should be
2661 * refined for exact hw design of imx8 pcie. 2687 * refined for exact hw design of imx8 pcie.
2662 */ 2688 */
2663 clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, 2689 clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
2664 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, 2690 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
2665 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, 2691 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
2666 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; 2692 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>;
2667 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 2693 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
2668 2694
2669 interrupt-map-mask = <0 0 0 0x7>; 2695 interrupt-map-mask = <0 0 0 0x7>;
2670 interrupt-map = <0 0 0 1 &gic 0 105 4>, 2696 interrupt-map = <0 0 0 1 &gic 0 105 4>,
2671 <0 0 0 2 &gic 0 106 4>, 2697 <0 0 0 2 &gic 0 106 4>,
2672 <0 0 0 3 &gic 0 107 4>, 2698 <0 0 0 3 &gic 0 107 4>,
2673 <0 0 0 4 &gic 0 108 4>; 2699 <0 0 0 4 &gic 0 108 4>;
2674 power-domains = <&pd_pcie1>; 2700 power-domains = <&pd_pcie1>;
2675 fsl,max-link-speed = <3>; 2701 fsl,max-link-speed = <3>;
2676 hsio-cfg = <PCIEAX1PCIEBX1SATA>; 2702 hsio-cfg = <PCIEAX1PCIEBX1SATA>;
2677 hsio = <&hsio>; 2703 hsio = <&hsio>;
2678 ctrl-id = <1>; /* pciea */ 2704 ctrl-id = <1>; /* pciea */
2679 cpu-base-addr = <0x80000000>; 2705 cpu-base-addr = <0x80000000>;
2680 status = "disabled"; 2706 status = "disabled";
2681 }; 2707 };
2682 2708
2683 imx_ion { 2709 imx_ion {
2684 compatible = "fsl,mxc-ion"; 2710 compatible = "fsl,mxc-ion";
2685 fsl,heap-id = <0>; 2711 fsl,heap-id = <0>;
2686 }; 2712 };
2687 }; 2713 };
2688 2714
2689 &A53_0 { 2715 &A53_0 {
2690 operating-points = < 2716 operating-points = <
2691 /* kHz uV */ 2717 /* kHz uV */
2692 1200000 1150000 2718 1200000 1150000
2693 >; 2719 >;
2694 clocks = <&clk IMX8QM_A53_DIV>; 2720 clocks = <&clk IMX8QM_A53_DIV>;
2695 }; 2721 };
2696 2722
2697 &A72_0 { 2723 &A72_0 {
2698 operating-points = < 2724 operating-points = <
2699 /* kHz uV */ 2725 /* kHz uV */
2700 1596000 1150000 2726 1596000 1150000
2701 >; 2727 >;
2702 clocks = <&clk IMX8QM_A72_DIV>; 2728 clocks = <&clk IMX8QM_A72_DIV>;
2703 }; 2729 };
2704 2730
arch/arm/dts/fsl-imx8qxp.dtsi
Diff comments   View file @ 70fa29c
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "fsl-imx8-ca35.dtsi" 17 #include "fsl-imx8-ca35.dtsi"
18 #include <dt-bindings/soc/imx_rsrc.h> 18 #include <dt-bindings/soc/imx_rsrc.h>
19 #include <dt-bindings/soc/imx8_hsio.h> 19 #include <dt-bindings/soc/imx8_hsio.h>
20 #include <dt-bindings/soc/imx8_pd.h> 20 #include <dt-bindings/soc/imx8_pd.h>
21 #include <dt-bindings/clock/imx8qxp-clock.h> 21 #include <dt-bindings/clock/imx8qxp-clock.h>
22 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 22 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
23 #include <dt-bindings/gpio/gpio.h> 23 #include <dt-bindings/gpio/gpio.h>
24 24
25 / { 25 / {
26 compatible = "fsl,imx8qxp"; 26 compatible = "fsl,imx8qxp";
27 interrupt-parent = <&gic>; 27 interrupt-parent = <&gic>;
28 #address-cells = <2>; 28 #address-cells = <2>;
29 #size-cells = <2>; 29 #size-cells = <2>;
30 30
31 aliases { 31 aliases {
32 csi0 = &mipi_csi_0; 32 csi0 = &mipi_csi_0;
33 dpu0 = &dpu1; 33 dpu0 = &dpu1;
34 ethernet0 = &fec1; 34 ethernet0 = &fec1;
35 ethernet1 = &fec2; 35 ethernet1 = &fec2;
36 ldb0 = &ldb1; 36 ldb0 = &ldb1;
37 ldb1 = &ldb2; 37 ldb1 = &ldb2;
38 isi0 = &isi_0; 38 isi0 = &isi_0;
39 isi1 = &isi_1; 39 isi1 = &isi_1;
40 isi2 = &isi_2; 40 isi2 = &isi_2;
41 isi3 = &isi_3; 41 isi3 = &isi_3;
42 isi4 = &isi_4; 42 isi4 = &isi_4;
43 isi5 = &isi_5; 43 isi5 = &isi_5;
44 isi6 = &isi_6; 44 isi6 = &isi_6;
45 isi7 = &isi_7; 45 isi7 = &isi_7;
46 serial0 = &lpuart0; 46 serial0 = &lpuart0;
47 serial1 = &lpuart1; 47 serial1 = &lpuart1;
48 serial2 = &lpuart2; 48 serial2 = &lpuart2;
49 serial3 = &lpuart3; 49 serial3 = &lpuart3;
50 gpio0 = &gpio0; 50 gpio0 = &gpio0;
51 gpio1 = &gpio1; 51 gpio1 = &gpio1;
52 gpio2 = &gpio2; 52 gpio2 = &gpio2;
53 gpio3 = &gpio3; 53 gpio3 = &gpio3;
54 gpio4 = &gpio4; 54 gpio4 = &gpio4;
55 gpio5 = &gpio5; 55 gpio5 = &gpio5;
56 gpio6 = &gpio6; 56 gpio6 = &gpio6;
57 gpio7 = &gpio7; 57 gpio7 = &gpio7;
58 i2c0 = &i2c0; 58 i2c0 = &i2c0;
59 i2c1 = &i2c1; 59 i2c1 = &i2c1;
60 i2c2 = &i2c2; 60 i2c2 = &i2c2;
61 i2c3 = &i2c3; 61 i2c3 = &i2c3;
62 i2c13 = &i2c0_mipi_lvds0; 62 i2c13 = &i2c0_mipi_lvds0;
63 i2c15 = &i2c0_mipi_lvds1; 63 i2c15 = &i2c0_mipi_lvds1;
64 spi0 = &flexspi0; 64 spi0 = &flexspi0;
65 usb0 = &usbotg1; 65 usb0 = &usbotg1;
66 usbphy0 = &usbphy1; 66 usbphy0 = &usbphy1;
67 usb1 = &usb2; 67 usb1 = &usb2;
68 usbphy1 = &usb2_phy; 68 usbphy1 = &usb2_phy;
69 }; 69 };
70 70
71 memory@80000000 { 71 memory@80000000 {
72 device_type = "memory"; 72 device_type = "memory";
73 reg = <0x00000000 0x80000000 0 0x40000000>; 73 reg = <0x00000000 0x80000000 0 0x40000000>;
74 /* DRAM space - 1, size : 1 GB DRAM */ 74 /* DRAM space - 1, size : 1 GB DRAM */
75 }; 75 };
76 76
77 reserved-memory { 77 reserved-memory {
78 #address-cells = <2>; 78 #address-cells = <2>;
79 #size-cells = <2>; 79 #size-cells = <2>;
80 ranges; 80 ranges;
81 81
82 /* global autoconfigured region for contiguous allocations */ 82 /* global autoconfigured region for contiguous allocations */
83 linux,cma { 83 linux,cma {
84 compatible = "shared-dma-pool"; 84 compatible = "shared-dma-pool";
85 reusable; 85 reusable;
86 size = <0 0x28000000>; 86 size = <0 0x28000000>;
87 alloc-ranges = <0 0x80000000 0 0x80000000>; 87 alloc-ranges = <0 0x80000000 0 0x80000000>;
88 linux,cma-default; 88 linux,cma-default;
89 }; 89 };
90 }; 90 };
91 91
92 gic: interrupt-controller@51a00000 { 92 gic: interrupt-controller@51a00000 {
93 compatible = "arm,gic-v3"; 93 compatible = "arm,gic-v3";
94 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 94 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
95 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 95 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
96 #interrupt-cells = <3>; 96 #interrupt-cells = <3>;
97 interrupt-controller; 97 interrupt-controller;
98 interrupts = <GIC_PPI 9 98 interrupts = <GIC_PPI 9
99 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 99 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
100 }; 100 };
101 101
102 mu8: mu@5d230000 {
103 compatible = "fsl,imx-m4-mu";
104 reg = <0x0 0x5d230000 0x0 0x10000>;
105 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
106 power-domains = <&pd_lsio_mu8a>;
107 status = "okay";
108 };
109
102 mu: mu@5d1b0000 { 110 mu: mu@5d1b0000 {
103 compatible = "fsl,imx8-mu"; 111 compatible = "fsl,imx8-mu";
104 reg = <0x0 0x5d1b0000 0x0 0x10000>; 112 reg = <0x0 0x5d1b0000 0x0 0x10000>;
105 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 113 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
106 fsl,scu_ap_mu_id = <0>; 114 fsl,scu_ap_mu_id = <0>;
107 #mbox-cells = <4>; 115 #mbox-cells = <4>;
108 status = "okay"; 116 status = "okay";
109 }; 117 };
110 118
111 mu13: mu13@5d280000 { 119 mu13: mu13@5d280000 {
112 compatible = "fsl,imx8-mu-hifi"; 120 compatible = "fsl,imx8-mu-hifi";
113 reg = <0x0 0x5d280000 0x0 0x10000>; 121 reg = <0x0 0x5d280000 0x0 0x10000>;
114 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 122 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
115 fsl,hifi_ap_mu_id = <13>; 123 fsl,hifi_ap_mu_id = <13>;
116 status = "okay"; 124 status = "okay";
117 }; 125 };
118 126
119 clk: clk { 127 clk: clk {
120 compatible = "fsl,imx8qxp-clk"; 128 compatible = "fsl,imx8qxp-clk";
121 #clock-cells = <1>; 129 #clock-cells = <1>;
122 }; 130 };
123 131
124 iomuxc: iomuxc { 132 iomuxc: iomuxc {
125 compatible = "fsl,imx8qxp-iomuxc"; 133 compatible = "fsl,imx8qxp-iomuxc";
126 }; 134 };
127 135
128 rtc: rtc { 136 rtc: rtc {
129 compatible = "fsl,imx-sc-rtc"; 137 compatible = "fsl,imx-sc-rtc";
130 }; 138 };
131 139
132 timer { 140 timer {
133 compatible = "arm,armv8-timer"; 141 compatible = "arm,armv8-timer";
134 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
135 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
136 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
137 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
138 clock-frequency = <8000000>; 146 clock-frequency = <8000000>;
139 }; 147 };
140 148
141 imx8qx-pm { 149 imx8qx-pm {
142 compatible = "simple-bus"; 150 compatible = "simple-bus";
143 #address-cells = <1>; 151 #address-cells = <1>;
144 #size-cells = <0>; 152 #size-cells = <0>;
145 153
146 pd_lsio: PD_LSIO { 154 pd_lsio: PD_LSIO {
147 compatible = "nxp,imx8-pd"; 155 compatible = "nxp,imx8-pd";
148 reg = <SC_R_LAST>; 156 reg = <SC_R_LAST>;
149 #power-domain-cells = <0>; 157 #power-domain-cells = <0>;
150 #address-cells = <1>; 158 #address-cells = <1>;
151 #size-cells = <0>; 159 #size-cells = <0>;
152 160
153 pd_lsio_pwm0: PD_LSIO_PWM_0 { 161 pd_lsio_pwm0: PD_LSIO_PWM_0 {
154 reg = <SC_R_PWM_0>; 162 reg = <SC_R_PWM_0>;
155 #power-domain-cells = <0>; 163 #power-domain-cells = <0>;
156 power-domains = <&pd_lsio>; 164 power-domains = <&pd_lsio>;
157 }; 165 };
158 pd_lsio_pwm1: PD_LSIO_PWM_1 { 166 pd_lsio_pwm1: PD_LSIO_PWM_1 {
159 reg = <SC_R_PWM_1>; 167 reg = <SC_R_PWM_1>;
160 #power-domain-cells = <0>; 168 #power-domain-cells = <0>;
161 power-domains = <&pd_lsio>; 169 power-domains = <&pd_lsio>;
162 }; 170 };
163 pd_lsio_pwm2: PD_LSIO_PWM_2 { 171 pd_lsio_pwm2: PD_LSIO_PWM_2 {
164 reg = <SC_R_PWM_2>; 172 reg = <SC_R_PWM_2>;
165 #power-domain-cells = <0>; 173 #power-domain-cells = <0>;
166 power-domains = <&pd_lsio>; 174 power-domains = <&pd_lsio>;
167 }; 175 };
168 pd_lsio_pwm3: PD_LSIO_PWM_3 { 176 pd_lsio_pwm3: PD_LSIO_PWM_3 {
169 reg = <SC_R_PWM_3>; 177 reg = <SC_R_PWM_3>;
170 #power-domain-cells = <0>; 178 #power-domain-cells = <0>;
171 power-domains = <&pd_lsio>; 179 power-domains = <&pd_lsio>;
172 }; 180 };
173 pd_lsio_pwm4: PD_LSIO_PWM_4 { 181 pd_lsio_pwm4: PD_LSIO_PWM_4 {
174 reg = <SC_R_PWM_4>; 182 reg = <SC_R_PWM_4>;
175 #power-domain-cells = <0>; 183 #power-domain-cells = <0>;
176 power-domains = <&pd_lsio>; 184 power-domains = <&pd_lsio>;
177 }; 185 };
178 pd_lsio_pwm5: PD_LSIO_PWM_5 { 186 pd_lsio_pwm5: PD_LSIO_PWM_5 {
179 reg = <SC_R_PWM_5>; 187 reg = <SC_R_PWM_5>;
180 #power-domain-cells = <0>; 188 #power-domain-cells = <0>;
181 power-domains = <&pd_lsio>; 189 power-domains = <&pd_lsio>;
182 }; 190 };
183 pd_lsio_pwm6: PD_LSIO_PWM_6 { 191 pd_lsio_pwm6: PD_LSIO_PWM_6 {
184 reg = <SC_R_PWM_6>; 192 reg = <SC_R_PWM_6>;
185 #power-domain-cells = <0>; 193 #power-domain-cells = <0>;
186 power-domains = <&pd_lsio>; 194 power-domains = <&pd_lsio>;
187 }; 195 };
188 pd_lsio_pwm7: PD_LSIO_PWM_7 { 196 pd_lsio_pwm7: PD_LSIO_PWM_7 {
189 reg = <SC_R_PWM_7>; 197 reg = <SC_R_PWM_7>;
190 #power-domain-cells = <0>; 198 #power-domain-cells = <0>;
191 power-domains = <&pd_lsio>; 199 power-domains = <&pd_lsio>;
192 }; 200 };
193 pd_lsio_kpp: PD_LSIO_KPP { 201 pd_lsio_kpp: PD_LSIO_KPP {
194 reg = <SC_R_KPP>; 202 reg = <SC_R_KPP>;
195 #power-domain-cells = <0>; 203 #power-domain-cells = <0>;
196 power-domains = <&pd_lsio>; 204 power-domains = <&pd_lsio>;
197 }; 205 };
198 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 206 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
199 reg = <SC_R_GPIO_0>; 207 reg = <SC_R_GPIO_0>;
200 #power-domain-cells = <0>; 208 #power-domain-cells = <0>;
201 power-domains = <&pd_lsio>; 209 power-domains = <&pd_lsio>;
202 }; 210 };
203 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 211 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
204 reg = <SC_R_GPIO_1>; 212 reg = <SC_R_GPIO_1>;
205 #power-domain-cells = <0>; 213 #power-domain-cells = <0>;
206 power-domains = <&pd_lsio>; 214 power-domains = <&pd_lsio>;
207 }; 215 };
208 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 216 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
209 reg = <SC_R_GPIO_2>; 217 reg = <SC_R_GPIO_2>;
210 #power-domain-cells = <0>; 218 #power-domain-cells = <0>;
211 power-domains = <&pd_lsio>; 219 power-domains = <&pd_lsio>;
212 }; 220 };
213 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 221 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
214 reg = <SC_R_GPIO_3>; 222 reg = <SC_R_GPIO_3>;
215 #power-domain-cells = <0>; 223 #power-domain-cells = <0>;
216 power-domains = <&pd_lsio>; 224 power-domains = <&pd_lsio>;
217 }; 225 };
218 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 226 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
219 reg = <SC_R_GPIO_4>; 227 reg = <SC_R_GPIO_4>;
220 #power-domain-cells = <0>; 228 #power-domain-cells = <0>;
221 power-domains = <&pd_lsio>; 229 power-domains = <&pd_lsio>;
222 }; 230 };
223 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 231 pd_lsio_gpio5: PD_LSIO_GPIO_5{
224 reg = <SC_R_GPIO_5>; 232 reg = <SC_R_GPIO_5>;
225 #power-domain-cells = <0>; 233 #power-domain-cells = <0>;
226 power-domains = <&pd_lsio>; 234 power-domains = <&pd_lsio>;
227 }; 235 };
228 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 236 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
229 reg = <SC_R_GPIO_6>; 237 reg = <SC_R_GPIO_6>;
230 #power-domain-cells = <0>; 238 #power-domain-cells = <0>;
231 power-domains = <&pd_lsio>; 239 power-domains = <&pd_lsio>;
232 }; 240 };
233 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 241 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
234 reg = <SC_R_GPIO_7>; 242 reg = <SC_R_GPIO_7>;
235 #power-domain-cells = <0>; 243 #power-domain-cells = <0>;
236 power-domains = <&pd_lsio>; 244 power-domains = <&pd_lsio>;
237 }; 245 };
238 pd_lsio_gpt0: PD_LSIO_GPT_0 { 246 pd_lsio_gpt0: PD_LSIO_GPT_0 {
239 reg = <SC_R_GPT_0>; 247 reg = <SC_R_GPT_0>;
240 #power-domain-cells = <0>; 248 #power-domain-cells = <0>;
241 power-domains = <&pd_lsio>; 249 power-domains = <&pd_lsio>;
242 }; 250 };
243 pd_lsio_gpt1: PD_LSIO_GPT_1 { 251 pd_lsio_gpt1: PD_LSIO_GPT_1 {
244 reg = <SC_R_GPT_1>; 252 reg = <SC_R_GPT_1>;
245 #power-domain-cells = <0>; 253 #power-domain-cells = <0>;
246 power-domains = <&pd_lsio>; 254 power-domains = <&pd_lsio>;
247 }; 255 };
248 pd_lsio_gpt2: PD_LSIO_GPT_2 { 256 pd_lsio_gpt2: PD_LSIO_GPT_2 {
249 reg = <SC_R_GPT_2>; 257 reg = <SC_R_GPT_2>;
250 #power-domain-cells = <0>; 258 #power-domain-cells = <0>;
251 power-domains = <&pd_lsio>; 259 power-domains = <&pd_lsio>;
252 }; 260 };
253 pd_lsio_gpt3: PD_LSIO_GPT_3 { 261 pd_lsio_gpt3: PD_LSIO_GPT_3 {
254 reg = <SC_R_GPT_3>; 262 reg = <SC_R_GPT_3>;
255 #power-domain-cells = <0>; 263 #power-domain-cells = <0>;
256 power-domains = <&pd_lsio>; 264 power-domains = <&pd_lsio>;
257 }; 265 };
258 pd_lsio_gpt4: PD_LSIO_GPT_4 { 266 pd_lsio_gpt4: PD_LSIO_GPT_4 {
259 reg = <SC_R_GPT_4>; 267 reg = <SC_R_GPT_4>;
260 #power-domain-cells = <0>; 268 #power-domain-cells = <0>;
261 power-domains = <&pd_lsio>; 269 power-domains = <&pd_lsio>;
262 }; 270 };
263 pd_lsio_flexspi0: PD_LSIO_FSPI_0 { 271 pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
264 reg = <SC_R_FSPI_0>; 272 reg = <SC_R_FSPI_0>;
265 #power-domain-cells = <0>; 273 #power-domain-cells = <0>;
266 power-domains = <&pd_lsio>; 274 power-domains = <&pd_lsio>;
267 }; 275 };
268 pd_lsio_flexspi1: PD_LSIO_FSPI_1{ 276 pd_lsio_flexspi1: PD_LSIO_FSPI_1{
269 reg = <SC_R_FSPI_1>; 277 reg = <SC_R_FSPI_1>;
278 #power-domain-cells = <0>;
279 power-domains = <&pd_lsio>;
280 };
281 pd_lsio_mu8a: PD_LSIO_MU8A {
282 reg = <SC_R_MU_8A>;
270 #power-domain-cells = <0>; 283 #power-domain-cells = <0>;
271 power-domains = <&pd_lsio>; 284 power-domains = <&pd_lsio>;
272 }; 285 };
273 }; 286 };
274 287
275 pd_conn: PD_CONN { 288 pd_conn: PD_CONN {
276 compatible = "nxp,imx8-pd"; 289 compatible = "nxp,imx8-pd";
277 reg = <SC_R_LAST>; 290 reg = <SC_R_LAST>;
278 #power-domain-cells = <0>; 291 #power-domain-cells = <0>;
279 #address-cells = <1>; 292 #address-cells = <1>;
280 #size-cells = <0>; 293 #size-cells = <0>;
281 294
282 pd_conn_usbotg0: PD_CONN_USB_0 { 295 pd_conn_usbotg0: PD_CONN_USB_0 {
283 reg = <SC_R_USB_0>; 296 reg = <SC_R_USB_0>;
284 #power-domain-cells = <0>; 297 #power-domain-cells = <0>;
285 power-domains = <&pd_conn>; 298 power-domains = <&pd_conn>;
286 }; 299 };
287 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { 300 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
288 reg = <SC_R_USB_0_PHY>; 301 reg = <SC_R_USB_0_PHY>;
289 #power-domain-cells = <0>; 302 #power-domain-cells = <0>;
290 power-domains = <&pd_conn>; 303 power-domains = <&pd_conn>;
291 }; 304 };
292 pd_conn_usbotg1: PD_CONN_USB_1 { 305 pd_conn_usbotg1: PD_CONN_USB_1 {
293 reg = <SC_R_USB_1>; 306 reg = <SC_R_USB_1>;
294 #power-domain-cells = <0>; 307 #power-domain-cells = <0>;
295 power-domains = <&pd_conn>; 308 power-domains = <&pd_conn>;
296 }; 309 };
297 pd_conn_usb2: PD_CONN_USB_2 { 310 pd_conn_usb2: PD_CONN_USB_2 {
298 reg = <SC_R_USB_2>; 311 reg = <SC_R_USB_2>;
299 #power-domain-cells = <0>; 312 #power-domain-cells = <0>;
300 power-domains = <&pd_conn>; 313 power-domains = <&pd_conn>;
301 }; 314 };
302 pd_conn_usb2_phy: PD_CONN_USB_2_PHY { 315 pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
303 reg = <SC_R_USB_2_PHY>; 316 reg = <SC_R_USB_2_PHY>;
304 #power-domain-cells = <0>; 317 #power-domain-cells = <0>;
305 power-domains = <&pd_conn>; 318 power-domains = <&pd_conn>;
306 }; 319 };
307 pd_conn_sdch0: PD_CONN_SDHC_0 { 320 pd_conn_sdch0: PD_CONN_SDHC_0 {
308 reg = <SC_R_SDHC_0>; 321 reg = <SC_R_SDHC_0>;
309 #power-domain-cells = <0>; 322 #power-domain-cells = <0>;
310 power-domains = <&pd_conn>; 323 power-domains = <&pd_conn>;
311 }; 324 };
312 pd_conn_sdch1: PD_CONN_SDHC_1 { 325 pd_conn_sdch1: PD_CONN_SDHC_1 {
313 reg = <SC_R_SDHC_1>; 326 reg = <SC_R_SDHC_1>;
314 #power-domain-cells = <0>; 327 #power-domain-cells = <0>;
315 power-domains = <&pd_conn>; 328 power-domains = <&pd_conn>;
316 }; 329 };
317 pd_conn_sdch2: PD_CONN_SDHC_2 { 330 pd_conn_sdch2: PD_CONN_SDHC_2 {
318 reg = <SC_R_SDHC_2>; 331 reg = <SC_R_SDHC_2>;
319 #power-domain-cells = <0>; 332 #power-domain-cells = <0>;
320 power-domains = <&pd_conn>; 333 power-domains = <&pd_conn>;
321 }; 334 };
322 pd_conn_enet0: PD_CONN_ENET_0 { 335 pd_conn_enet0: PD_CONN_ENET_0 {
323 reg = <SC_R_ENET_0>; 336 reg = <SC_R_ENET_0>;
324 #power-domain-cells = <0>; 337 #power-domain-cells = <0>;
325 power-domains = <&pd_conn>; 338 power-domains = <&pd_conn>;
326 }; 339 };
327 pd_conn_enet1: PD_CONN_ENET_1 { 340 pd_conn_enet1: PD_CONN_ENET_1 {
328 reg = <SC_R_ENET_1>; 341 reg = <SC_R_ENET_1>;
329 #power-domain-cells = <0>; 342 #power-domain-cells = <0>;
330 power-domains = <&pd_conn>; 343 power-domains = <&pd_conn>;
331 }; 344 };
332 pd_conn_nand: PD_CONN_NAND { 345 pd_conn_nand: PD_CONN_NAND {
333 reg = <SC_R_NAND>; 346 reg = <SC_R_NAND>;
334 #power-domain-cells = <0>; 347 #power-domain-cells = <0>;
335 power-domains = <&pd_conn>; 348 power-domains = <&pd_conn>;
336 }; 349 };
337 pd_conn_mlb0: PD_CONN_MLB_0 { 350 pd_conn_mlb0: PD_CONN_MLB_0 {
338 reg = <SC_R_MLB_0>; 351 reg = <SC_R_MLB_0>;
339 #power-domain-cells = <0>; 352 #power-domain-cells = <0>;
340 power-domains = <&pd_conn>; 353 power-domains = <&pd_conn>;
341 }; 354 };
342 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { 355 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
343 reg = <SC_R_DMA_4_CH0>; 356 reg = <SC_R_DMA_4_CH0>;
344 #power-domain-cells = <0>; 357 #power-domain-cells = <0>;
345 power-domains =<&pd_conn>; 358 power-domains =<&pd_conn>;
346 }; 359 };
347 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { 360 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
348 reg = <SC_R_DMA_4_CH1>; 361 reg = <SC_R_DMA_4_CH1>;
349 #power-domain-cells = <0>; 362 #power-domain-cells = <0>;
350 power-domains =<&pd_conn>; 363 power-domains =<&pd_conn>;
351 }; 364 };
352 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { 365 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
353 reg = <SC_R_DMA_4_CH2>; 366 reg = <SC_R_DMA_4_CH2>;
354 #power-domain-cells = <0>; 367 #power-domain-cells = <0>;
355 power-domains =<&pd_conn>; 368 power-domains =<&pd_conn>;
356 }; 369 };
357 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { 370 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
358 reg = <SC_R_DMA_4_CH3>; 371 reg = <SC_R_DMA_4_CH3>;
359 #power-domain-cells = <0>; 372 #power-domain-cells = <0>;
360 power-domains =<&pd_conn>; 373 power-domains =<&pd_conn>;
361 }; 374 };
362 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { 375 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
363 reg = <SC_R_DMA_4_CH4>; 376 reg = <SC_R_DMA_4_CH4>;
364 #power-domain-cells = <0>; 377 #power-domain-cells = <0>;
365 power-domains =<&pd_conn>; 378 power-domains =<&pd_conn>;
366 }; 379 };
367 }; 380 };
368 381
369 pd_audio: PD_AUDIO { 382 pd_audio: PD_AUDIO {
370 compatible = "nxp,imx8-pd"; 383 compatible = "nxp,imx8-pd";
371 reg = <SC_R_LAST>; 384 reg = <SC_R_LAST>;
372 #power-domain-cells = <0>; 385 #power-domain-cells = <0>;
373 #address-cells = <1>; 386 #address-cells = <1>;
374 #size-cells = <0>; 387 #size-cells = <0>;
375 388
376 pd_asrc0:PD_AUD_ASRC_0 { 389 pd_asrc0:PD_AUD_ASRC_0 {
377 reg = <SC_R_ASRC_0>; 390 reg = <SC_R_ASRC_0>;
378 #power-domain-cells = <0>; 391 #power-domain-cells = <0>;
379 power-domains =<&pd_audio>; 392 power-domains =<&pd_audio>;
380 }; 393 };
381 pd_asrc1: PD_AUD_ASRC_1 { 394 pd_asrc1: PD_AUD_ASRC_1 {
382 reg = <SC_R_ASRC_1>; 395 reg = <SC_R_ASRC_1>;
383 #power-domain-cells = <0>; 396 #power-domain-cells = <0>;
384 power-domains =<&pd_audio>; 397 power-domains =<&pd_audio>;
385 }; 398 };
386 pd_esai0: PD_AUD_ESAI_0 { 399 pd_esai0: PD_AUD_ESAI_0 {
387 reg = <SC_R_ESAI_0>; 400 reg = <SC_R_ESAI_0>;
388 #power-domain-cells = <0>; 401 #power-domain-cells = <0>;
389 power-domains =<&pd_audio>; 402 power-domains =<&pd_audio>;
390 }; 403 };
391 pd_spdif0: PD_AUD_SPDIF_0 { 404 pd_spdif0: PD_AUD_SPDIF_0 {
392 reg = <SC_R_SPDIF_0>; 405 reg = <SC_R_SPDIF_0>;
393 #power-domain-cells = <0>; 406 #power-domain-cells = <0>;
394 power-domains =<&pd_audio>; 407 power-domains =<&pd_audio>;
395 }; 408 };
396 pd_sai0:PD_AUD_SAI_0 { 409 pd_sai0:PD_AUD_SAI_0 {
397 reg = <SC_R_SAI_0>; 410 reg = <SC_R_SAI_0>;
398 #power-domain-cells = <0>; 411 #power-domain-cells = <0>;
399 power-domains =<&pd_audio>; 412 power-domains =<&pd_audio>;
400 }; 413 };
401 pd_sai1: PD_AUD_SAI_1 { 414 pd_sai1: PD_AUD_SAI_1 {
402 reg = <SC_R_SAI_1>; 415 reg = <SC_R_SAI_1>;
403 #power-domain-cells = <0>; 416 #power-domain-cells = <0>;
404 power-domains =<&pd_audio>; 417 power-domains =<&pd_audio>;
405 }; 418 };
406 pd_sai2: PD_AUD_SAI_2 { 419 pd_sai2: PD_AUD_SAI_2 {
407 reg = <SC_R_SAI_2>; 420 reg = <SC_R_SAI_2>;
408 #power-domain-cells = <0>; 421 #power-domain-cells = <0>;
409 power-domains =<&pd_audio>; 422 power-domains =<&pd_audio>;
410 }; 423 };
411 pd_sai3: PD_AUD_SAI_3 { 424 pd_sai3: PD_AUD_SAI_3 {
412 reg = <SC_R_SAI_3>; 425 reg = <SC_R_SAI_3>;
413 #power-domain-cells = <0>; 426 #power-domain-cells = <0>;
414 power-domains =<&pd_audio>; 427 power-domains =<&pd_audio>;
415 }; 428 };
416 pd_sai4: PD_AUD_SAI_4 { 429 pd_sai4: PD_AUD_SAI_4 {
417 reg = <SC_R_SAI_4>; 430 reg = <SC_R_SAI_4>;
418 #power-domain-cells = <0>; 431 #power-domain-cells = <0>;
419 power-domains =<&pd_audio>; 432 power-domains =<&pd_audio>;
420 }; 433 };
421 pd_sai5: PD_AUD_SAI_5 { 434 pd_sai5: PD_AUD_SAI_5 {
422 reg = <SC_R_SAI_5>; 435 reg = <SC_R_SAI_5>;
423 #power-domain-cells = <0>; 436 #power-domain-cells = <0>;
424 power-domains =<&pd_audio>; 437 power-domains =<&pd_audio>;
425 }; 438 };
426 pd_gpt5: PD_AUD_GPT_5 { 439 pd_gpt5: PD_AUD_GPT_5 {
427 reg = <SC_R_GPT_5>; 440 reg = <SC_R_GPT_5>;
428 #power-domain-cells = <0>; 441 #power-domain-cells = <0>;
429 power-domains =<&pd_audio>; 442 power-domains =<&pd_audio>;
430 }; 443 };
431 pd_gpt6: PD_AUD_GPT_6 { 444 pd_gpt6: PD_AUD_GPT_6 {
432 reg = <SC_R_GPT_6>; 445 reg = <SC_R_GPT_6>;
433 #power-domain-cells = <0>; 446 #power-domain-cells = <0>;
434 power-domains =<&pd_audio>; 447 power-domains =<&pd_audio>;
435 }; 448 };
436 pd_gpt7: PD_AUD_GPT_7 { 449 pd_gpt7: PD_AUD_GPT_7 {
437 reg = <SC_R_GPT_7>; 450 reg = <SC_R_GPT_7>;
438 #power-domain-cells = <0>; 451 #power-domain-cells = <0>;
439 power-domains =<&pd_audio>; 452 power-domains =<&pd_audio>;
440 }; 453 };
441 pd_gpt8: PD_AUD_GPT_8 { 454 pd_gpt8: PD_AUD_GPT_8 {
442 reg = <SC_R_GPT_8>; 455 reg = <SC_R_GPT_8>;
443 #power-domain-cells = <0>; 456 #power-domain-cells = <0>;
444 power-domains =<&pd_audio>; 457 power-domains =<&pd_audio>;
445 }; 458 };
446 pd_gpt9: PD_AUD_GPT_9 { 459 pd_gpt9: PD_AUD_GPT_9 {
447 reg = <SC_R_GPT_9>; 460 reg = <SC_R_GPT_9>;
448 #power-domain-cells = <0>; 461 #power-domain-cells = <0>;
449 power-domains =<&pd_audio>; 462 power-domains =<&pd_audio>;
450 }; 463 };
451 pd_gpt10: PD_AUD_GPT_10 { 464 pd_gpt10: PD_AUD_GPT_10 {
452 reg = <SC_R_GPT_10>; 465 reg = <SC_R_GPT_10>;
453 #power-domain-cells = <0>; 466 #power-domain-cells = <0>;
454 power-domains =<&pd_audio>; 467 power-domains =<&pd_audio>;
455 }; 468 };
456 pd_amix: PD_AUD_AMIX { 469 pd_amix: PD_AUD_AMIX {
457 reg = <SC_R_AMIX>; 470 reg = <SC_R_AMIX>;
458 #power-domain-cells = <0>; 471 #power-domain-cells = <0>;
459 power-domains =<&pd_audio>; 472 power-domains =<&pd_audio>;
460 }; 473 };
461 pd_mqs0: PD_AUD_MQS_0 { 474 pd_mqs0: PD_AUD_MQS_0 {
462 reg = <SC_R_MQS_0>; 475 reg = <SC_R_MQS_0>;
463 #power-domain-cells = <0>; 476 #power-domain-cells = <0>;
464 power-domains =<&pd_audio>; 477 power-domains =<&pd_audio>;
465 }; 478 };
466 pd_hifi: PD_AUD_HIFI { 479 pd_hifi: PD_AUD_HIFI {
467 reg = <SC_R_DSP>; 480 reg = <SC_R_DSP>;
468 #power-domain-cells = <0>; 481 #power-domain-cells = <0>;
469 power-domains =<&pd_audio>; 482 power-domains =<&pd_audio>;
470 }; 483 };
471 pd_hifi_ram: PD_AUD_OCRAM { 484 pd_hifi_ram: PD_AUD_OCRAM {
472 reg = <SC_R_DSP_RAM>; 485 reg = <SC_R_DSP_RAM>;
473 #power-domain-cells = <0>; 486 #power-domain-cells = <0>;
474 power-domains =<&pd_audio>; 487 power-domains =<&pd_audio>;
475 }; 488 };
476 pd_mclk_out0: PD_AUD_MCLK_OUT_0 { 489 pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
477 reg = <SC_R_MCLK_OUT_0>; 490 reg = <SC_R_MCLK_OUT_0>;
478 #power-domain-cells = <0>; 491 #power-domain-cells = <0>;
479 power-domains =<&pd_audio>; 492 power-domains =<&pd_audio>;
480 }; 493 };
481 pd_mclk_out1: PD_AUD_MCLK_OUT_1 { 494 pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
482 reg = <SC_R_MCLK_OUT_1>; 495 reg = <SC_R_MCLK_OUT_1>;
483 #power-domain-cells = <0>; 496 #power-domain-cells = <0>;
484 power-domains =<&pd_audio>; 497 power-domains =<&pd_audio>;
485 }; 498 };
486 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { 499 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
487 reg = <SC_R_AUDIO_PLL_0>; 500 reg = <SC_R_AUDIO_PLL_0>;
488 #power-domain-cells = <0>; 501 #power-domain-cells = <0>;
489 power-domains =<&pd_audio>; 502 power-domains =<&pd_audio>;
490 }; 503 };
491 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { 504 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
492 reg = <SC_R_AUDIO_PLL_1>; 505 reg = <SC_R_AUDIO_PLL_1>;
493 #power-domain-cells = <0>; 506 #power-domain-cells = <0>;
494 power-domains =<&pd_audio>; 507 power-domains =<&pd_audio>;
495 }; 508 };
496 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { 509 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
497 reg = <SC_R_AUDIO_CLK_0>; 510 reg = <SC_R_AUDIO_CLK_0>;
498 #power-domain-cells = <0>; 511 #power-domain-cells = <0>;
499 power-domains =<&pd_audio>; 512 power-domains =<&pd_audio>;
500 }; 513 };
501 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { 514 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
502 reg = <SC_R_AUDIO_CLK_1>; 515 reg = <SC_R_AUDIO_CLK_1>;
503 #power-domain-cells = <0>; 516 #power-domain-cells = <0>;
504 power-domains =<&pd_audio>; 517 power-domains =<&pd_audio>;
505 }; 518 };
506 }; 519 };
507 520
508 pd_dma: PD_DMA { 521 pd_dma: PD_DMA {
509 compatible = "nxp,imx8-pd"; 522 compatible = "nxp,imx8-pd";
510 reg = <SC_R_LAST>; 523 reg = <SC_R_LAST>;
511 #power-domain-cells = <0>; 524 #power-domain-cells = <0>;
512 #address-cells = <1>; 525 #address-cells = <1>;
513 #size-cells = <0>; 526 #size-cells = <0>;
514 527
515 pd_dma_flexcan0: PD_DMA_CAN_0 { 528 pd_dma_flexcan0: PD_DMA_CAN_0 {
516 reg = <SC_R_CAN_0>; 529 reg = <SC_R_CAN_0>;
517 #power-domain-cells = <0>; 530 #power-domain-cells = <0>;
518 power-domains = <&pd_dma>; 531 power-domains = <&pd_dma>;
519 }; 532 };
520 pd_dma_flexcan1: PD_DMA_CAN_1 { 533 pd_dma_flexcan1: PD_DMA_CAN_1 {
521 reg = <SC_R_CAN_1>; 534 reg = <SC_R_CAN_1>;
522 #power-domain-cells = <0>; 535 #power-domain-cells = <0>;
523 power-domains = <&pd_dma>; 536 power-domains = <&pd_dma>;
524 }; 537 };
525 pd_dma_flexcan2: PD_DMA_CAN_2 { 538 pd_dma_flexcan2: PD_DMA_CAN_2 {
526 reg = <SC_R_CAN_2>; 539 reg = <SC_R_CAN_2>;
527 #power-domain-cells = <0>; 540 #power-domain-cells = <0>;
528 power-domains = <&pd_dma>; 541 power-domains = <&pd_dma>;
529 }; 542 };
530 pd_dma_ftm0: PD_DMA_FTM_0 { 543 pd_dma_ftm0: PD_DMA_FTM_0 {
531 reg = <SC_R_FTM_0>; 544 reg = <SC_R_FTM_0>;
532 #power-domain-cells = <0>; 545 #power-domain-cells = <0>;
533 power-domains = <&pd_dma>; 546 power-domains = <&pd_dma>;
534 }; 547 };
535 pd_dma_ftm1: PD_DMA_FTM_1 { 548 pd_dma_ftm1: PD_DMA_FTM_1 {
536 reg = <SC_R_FTM_1>; 549 reg = <SC_R_FTM_1>;
537 #power-domain-cells = <0>; 550 #power-domain-cells = <0>;
538 power-domains = <&pd_dma>; 551 power-domains = <&pd_dma>;
539 }; 552 };
540 pd_dma_adc0: PD_DMA_ADC_0 { 553 pd_dma_adc0: PD_DMA_ADC_0 {
541 reg = <SC_R_ADC_0>; 554 reg = <SC_R_ADC_0>;
542 #power-domain-cells = <0>; 555 #power-domain-cells = <0>;
543 power-domains = <&pd_dma>; 556 power-domains = <&pd_dma>;
544 }; 557 };
545 pd_dma_lpi2c0: PD_DMA_I2C_0 { 558 pd_dma_lpi2c0: PD_DMA_I2C_0 {
546 reg = <SC_R_I2C_0>; 559 reg = <SC_R_I2C_0>;
547 #power-domain-cells = <0>; 560 #power-domain-cells = <0>;
548 power-domains = <&pd_dma>; 561 power-domains = <&pd_dma>;
549 }; 562 };
550 pd_dma_lpi2c1: PD_DMA_I2C_1 { 563 pd_dma_lpi2c1: PD_DMA_I2C_1 {
551 reg = <SC_R_I2C_1>; 564 reg = <SC_R_I2C_1>;
552 #power-domain-cells = <0>; 565 #power-domain-cells = <0>;
553 power-domains = <&pd_dma>; 566 power-domains = <&pd_dma>;
554 }; 567 };
555 pd_dma_lpi2c2:PD_DMA_I2C_2 { 568 pd_dma_lpi2c2:PD_DMA_I2C_2 {
556 reg = <SC_R_I2C_2>; 569 reg = <SC_R_I2C_2>;
557 #power-domain-cells = <0>; 570 #power-domain-cells = <0>;
558 power-domains = <&pd_dma>; 571 power-domains = <&pd_dma>;
559 }; 572 };
560 pd_dma_lpi2c3: PD_DMA_I2C_3 { 573 pd_dma_lpi2c3: PD_DMA_I2C_3 {
561 reg = <SC_R_I2C_3>; 574 reg = <SC_R_I2C_3>;
562 #power-domain-cells = <0>; 575 #power-domain-cells = <0>;
563 power-domains = <&pd_dma>; 576 power-domains = <&pd_dma>;
564 }; 577 };
565 pd_dma_lpuart0: PD_DMA_UART0 { 578 pd_dma_lpuart0: PD_DMA_UART0 {
566 reg = <SC_R_UART_0>; 579 reg = <SC_R_UART_0>;
567 #power-domain-cells = <0>; 580 #power-domain-cells = <0>;
568 power-domains = <&pd_dma>; 581 power-domains = <&pd_dma>;
569 }; 582 };
570 pd_dma_lpuart1: PD_DMA_UART1 { 583 pd_dma_lpuart1: PD_DMA_UART1 {
571 reg = <SC_R_UART_1>; 584 reg = <SC_R_UART_1>;
572 #power-domain-cells = <0>; 585 #power-domain-cells = <0>;
573 power-domains = <&pd_dma>; 586 power-domains = <&pd_dma>;
574 }; 587 };
575 pd_dma_lpuart2: PD_DMA_UART2 { 588 pd_dma_lpuart2: PD_DMA_UART2 {
576 reg = <SC_R_UART_2>; 589 reg = <SC_R_UART_2>;
577 #power-domain-cells = <0>; 590 #power-domain-cells = <0>;
578 power-domains = <&pd_dma>; 591 power-domains = <&pd_dma>;
579 }; 592 };
580 pd_dma_lpuart3: PD_DMA_UART3 { 593 pd_dma_lpuart3: PD_DMA_UART3 {
581 reg = <SC_R_UART_3>; 594 reg = <SC_R_UART_3>;
582 #power-domain-cells = <0>; 595 #power-domain-cells = <0>;
583 power-domains = <&pd_dma>; 596 power-domains = <&pd_dma>;
584 }; 597 };
585 pd_dma_lpspi0: PD_DMA_SPI_0 { 598 pd_dma_lpspi0: PD_DMA_SPI_0 {
586 reg = <SC_R_SPI_0>; 599 reg = <SC_R_SPI_0>;
587 #power-domain-cells = <0>; 600 #power-domain-cells = <0>;
588 power-domains = <&pd_dma>; 601 power-domains = <&pd_dma>;
589 }; 602 };
590 pd_dma_lpspi1: PD_DMA_SPI_1 { 603 pd_dma_lpspi1: PD_DMA_SPI_1 {
591 reg = <SC_R_SPI_1>; 604 reg = <SC_R_SPI_1>;
592 #power-domain-cells = <0>; 605 #power-domain-cells = <0>;
593 power-domains = <&pd_dma>; 606 power-domains = <&pd_dma>;
594 }; 607 };
595 pd_dma_lpspi2: PD_DMA_SPI_2 { 608 pd_dma_lpspi2: PD_DMA_SPI_2 {
596 reg = <SC_R_SPI_2>; 609 reg = <SC_R_SPI_2>;
597 #power-domain-cells = <0>; 610 #power-domain-cells = <0>;
598 power-domains = <&pd_dma>; 611 power-domains = <&pd_dma>;
599 }; 612 };
600 pd_dma_lpspi3: PD_DMA_SPI_3 { 613 pd_dma_lpspi3: PD_DMA_SPI_3 {
601 reg = <SC_R_SPI_3>; 614 reg = <SC_R_SPI_3>;
602 #power-domain-cells = <0>; 615 #power-domain-cells = <0>;
603 power-domains = <&pd_dma>; 616 power-domains = <&pd_dma>;
604 }; 617 };
605 pd_dma_pwm0: PD_DMA_PWM_0 { 618 pd_dma_pwm0: PD_DMA_PWM_0 {
606 reg = <SC_R_LCD_0_PWM_0>; 619 reg = <SC_R_LCD_0_PWM_0>;
607 #power-domain-cells = <0>; 620 #power-domain-cells = <0>;
608 power-domains = <&pd_dma>; 621 power-domains = <&pd_dma>;
609 }; 622 };
610 pd_dma_lcd0: PD_DMA_LCD_0 { 623 pd_dma_lcd0: PD_DMA_LCD_0 {
611 reg = <SC_R_LCD_0>; 624 reg = <SC_R_LCD_0>;
612 #power-domain-cells = <0>; 625 #power-domain-cells = <0>;
613 power-domains = <&pd_dma>; 626 power-domains = <&pd_dma>;
614 }; 627 };
615 }; 628 };
616 629
617 pd_gpu: gpu-power-domain { 630 pd_gpu: gpu-power-domain {
618 compatible = "nxp,imx8-pd"; 631 compatible = "nxp,imx8-pd";
619 reg = <SC_R_LAST>; 632 reg = <SC_R_LAST>;
620 #power-domain-cells = <0>; 633 #power-domain-cells = <0>;
621 #address-cells = <1>; 634 #address-cells = <1>;
622 #size-cells = <0>; 635 #size-cells = <0>;
623 636
624 pd_gpu0: gpu0 { 637 pd_gpu0: gpu0 {
625 name = "gpu0"; 638 name = "gpu0";
626 reg = <SC_R_GPU_0_PID0>; 639 reg = <SC_R_GPU_0_PID0>;
627 #power-domain-cells = <0>; 640 #power-domain-cells = <0>;
628 power-domains =<&pd_gpu>; 641 power-domains =<&pd_gpu>;
629 #address-cells = <1>; 642 #address-cells = <1>;
630 #size-cells = <0>; 643 #size-cells = <0>;
631 }; 644 };
632 }; 645 };
633 646
634 pd_vpu: vpu-power-domain { 647 pd_vpu: vpu-power-domain {
635 compatible = "nxp,imx8-pd"; 648 compatible = "nxp,imx8-pd";
636 reg = <SC_R_VPU>; 649 reg = <SC_R_VPU>;
637 #power-domain-cells = <0>; 650 #power-domain-cells = <0>;
638 #address-cells = <1>; 651 #address-cells = <1>;
639 #size-cells = <0>; 652 #size-cells = <0>;
640 653
641 pd_vpu_core: vpu_core { 654 pd_vpu_core: vpu_core {
642 name = "vpu_core"; 655 name = "vpu_core";
643 reg = <SC_R_VPUCORE>; 656 reg = <SC_R_VPUCORE>;
644 #power-domain-cells = <0>; 657 #power-domain-cells = <0>;
645 power-domains =<&pd_vpu>; 658 power-domains =<&pd_vpu>;
646 }; 659 };
647 }; 660 };
648 661
649 pd_hsio: hsio-power-domain { 662 pd_hsio: hsio-power-domain {
650 compatible = "nxp,imx8-pd"; 663 compatible = "nxp,imx8-pd";
651 reg = <SC_R_LAST>; 664 reg = <SC_R_LAST>;
652 #power-domain-cells = <0>; 665 #power-domain-cells = <0>;
653 #address-cells = <1>; 666 #address-cells = <1>;
654 #size-cells = <0>; 667 #size-cells = <0>;
655 668
656 pd_serdes1: PD_HSIO_SERDES_1 { 669 pd_serdes1: PD_HSIO_SERDES_1 {
657 reg = <SC_R_SERDES_1>; 670 reg = <SC_R_SERDES_1>;
658 #power-domain-cells = <0>; 671 #power-domain-cells = <0>;
659 power-domains =<&pd_hsio>; 672 power-domains =<&pd_hsio>;
660 #address-cells = <1>; 673 #address-cells = <1>;
661 #size-cells = <0>; 674 #size-cells = <0>;
662 675
663 pd_pcie: PD_HSIO_PCIE_B { 676 pd_pcie: PD_HSIO_PCIE_B {
664 reg = <SC_R_PCIE_B>; 677 reg = <SC_R_PCIE_B>;
665 #power-domain-cells = <0>; 678 #power-domain-cells = <0>;
666 power-domains =<&pd_serdes1>; 679 power-domains =<&pd_serdes1>;
667 }; 680 };
668 }; 681 };
669 pd_gpio: PD_HSIO_GPIO { 682 pd_gpio: PD_HSIO_GPIO {
670 reg = <SC_R_HSIO_GPIO>; 683 reg = <SC_R_HSIO_GPIO>;
671 #power-domain-cells = <0>; 684 #power-domain-cells = <0>;
672 power-domains =<&pd_hsio>; 685 power-domains =<&pd_hsio>;
673 }; 686 };
674 }; 687 };
675 688
676 pd_cm40: PD_CM40 { 689 pd_cm40: PD_CM40 {
677 compatible = "nxp,imx8-pd"; 690 compatible = "nxp,imx8-pd";
678 reg = <SC_R_LAST>; 691 reg = <SC_R_LAST>;
679 #power-domain-cells = <0>; 692 #power-domain-cells = <0>;
680 #address-cells = <1>; 693 #address-cells = <1>;
681 #size-cells = <0>; 694 #size-cells = <0>;
682 695
683 pd_cm40_i2c: PD_CM40_I2C { 696 pd_cm40_i2c: PD_CM40_I2C {
684 reg = <SC_R_M4_0_I2C>; 697 reg = <SC_R_M4_0_I2C>;
685 #power-domain-cells = <0>; 698 #power-domain-cells = <0>;
686 power-domains =<&pd_cm40>; 699 power-domains =<&pd_cm40>;
687 }; 700 };
688 701
689 pd_cm40_intmux: PD_CM40_INTMUX { 702 pd_cm40_intmux: PD_CM40_INTMUX {
690 reg = <SC_R_M4_0_INTMUX>; 703 reg = <SC_R_M4_0_INTMUX>;
691 #power-domain-cells = <0>; 704 #power-domain-cells = <0>;
692 power-domains =<&pd_cm40>; 705 power-domains =<&pd_cm40>;
693 }; 706 };
694 }; 707 };
695 708
696 709
697 pd_dc0: PD_DC_0 { 710 pd_dc0: PD_DC_0 {
698 compatible = "nxp,imx8-pd"; 711 compatible = "nxp,imx8-pd";
699 reg = <SC_R_DC_0>; 712 reg = <SC_R_DC_0>;
700 #power-domain-cells = <0>; 713 #power-domain-cells = <0>;
701 #address-cells = <1>; 714 #address-cells = <1>;
702 #size-cells = <0>; 715 #size-cells = <0>;
703 716
704 pd_dc0_pll0: PD_DC_0_PLL_0{ 717 pd_dc0_pll0: PD_DC_0_PLL_0{
705 reg = <SC_R_DC_0_PLL_0>; 718 reg = <SC_R_DC_0_PLL_0>;
706 #power-domain-cells = <0>; 719 #power-domain-cells = <0>;
707 power-domains =<&pd_dc0>; 720 power-domains =<&pd_dc0>;
708 #address-cells = <1>; 721 #address-cells = <1>;
709 #size-cells = <0>; 722 #size-cells = <0>;
710 723
711 pd_dc0_pll1: PD_DC_0_PLL_1{ 724 pd_dc0_pll1: PD_DC_0_PLL_1{
712 reg = <SC_R_DC_0_PLL_1>; 725 reg = <SC_R_DC_0_PLL_1>;
713 #power-domain-cells = <0>; 726 #power-domain-cells = <0>;
714 power-domains =<&pd_dc0_pll0>; 727 power-domains =<&pd_dc0_pll0>;
715 }; 728 };
716 }; 729 };
717 pd_mipi_dsi0: PD_MIPI_0_DSI { 730 pd_mipi_dsi0: PD_MIPI_0_DSI {
718 reg = <SC_R_MIPI_0>; 731 reg = <SC_R_MIPI_0>;
719 #power-domain-cells = <0>; 732 #power-domain-cells = <0>;
720 power-domains =<&pd_dc0>; 733 power-domains =<&pd_dc0>;
721 #address-cells = <1>; 734 #address-cells = <1>;
722 #size-cells = <0>; 735 #size-cells = <0>;
723 736
724 pd_mipi_dsi_0_lvds: PD_LVDS0 { 737 pd_mipi_dsi_0_lvds: PD_LVDS0 {
725 reg = <SC_R_LVDS_0>; 738 reg = <SC_R_LVDS_0>;
726 #power-domain-cells = <0>; 739 #power-domain-cells = <0>;
727 power-domains =<&pd_mipi_dsi0>; 740 power-domains =<&pd_mipi_dsi0>;
728 }; 741 };
729 742
730 pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { 743 pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 {
731 reg = <SC_R_MIPI_0_I2C_0>; 744 reg = <SC_R_MIPI_0_I2C_0>;
732 #power-domain-cells = <0>; 745 #power-domain-cells = <0>;
733 power-domains =<&pd_mipi_dsi0>; 746 power-domains =<&pd_mipi_dsi0>;
734 }; 747 };
735 pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { 748 pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 {
736 reg = <SC_R_MIPI_0_I2C_1>; 749 reg = <SC_R_MIPI_0_I2C_1>;
737 #power-domain-cells = <0>; 750 #power-domain-cells = <0>;
738 power-domains =<&pd_mipi_dsi0>; 751 power-domains =<&pd_mipi_dsi0>;
739 }; 752 };
740 pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { 753 pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 {
741 reg = <SC_R_MIPI_0_PWM_0>; 754 reg = <SC_R_MIPI_0_PWM_0>;
742 #power-domain-cells = <0>; 755 #power-domain-cells = <0>;
743 power-domains =<&pd_mipi_dsi0>; 756 power-domains =<&pd_mipi_dsi0>;
744 }; 757 };
745 }; 758 };
746 759
747 pd_mipi_dsi1: PD_MIPI_1_DSI { 760 pd_mipi_dsi1: PD_MIPI_1_DSI {
748 reg = <SC_R_MIPI_1>; 761 reg = <SC_R_MIPI_1>;
749 #power-domain-cells = <0>; 762 #power-domain-cells = <0>;
750 power-domains =<&pd_dc0>; 763 power-domains =<&pd_dc0>;
751 #address-cells = <1>; 764 #address-cells = <1>;
752 #size-cells = <0>; 765 #size-cells = <0>;
753 766
754 pd_mipi_dsi_1_lvds: PD_LVDS1 { 767 pd_mipi_dsi_1_lvds: PD_LVDS1 {
755 reg = <SC_R_LVDS_1>; 768 reg = <SC_R_LVDS_1>;
756 #power-domain-cells = <0>; 769 #power-domain-cells = <0>;
757 power-domains =<&pd_mipi_dsi1>; 770 power-domains =<&pd_mipi_dsi1>;
758 }; 771 };
759 772
760 pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { 773 pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 {
761 reg = <SC_R_MIPI_1_I2C_0>; 774 reg = <SC_R_MIPI_1_I2C_0>;
762 #power-domain-cells = <0>; 775 #power-domain-cells = <0>;
763 power-domains =<&pd_mipi_dsi1>; 776 power-domains =<&pd_mipi_dsi1>;
764 }; 777 };
765 pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { 778 pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 {
766 reg = <SC_R_MIPI_1_I2C_1>; 779 reg = <SC_R_MIPI_1_I2C_1>;
767 #power-domain-cells = <0>; 780 #power-domain-cells = <0>;
768 power-domains =<&pd_mipi_dsi1>; 781 power-domains =<&pd_mipi_dsi1>;
769 }; 782 };
770 pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { 783 pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 {
771 reg = <SC_R_MIPI_1_PWM_0>; 784 reg = <SC_R_MIPI_1_PWM_0>;
772 #power-domain-cells = <0>; 785 #power-domain-cells = <0>;
773 power-domains =<&pd_mipi_dsi1>; 786 power-domains =<&pd_mipi_dsi1>;
774 }; 787 };
775 }; 788 };
776 }; 789 };
777 790
778 pd_isi_ch0: PD_IMAGING { 791 pd_isi_ch0: PD_IMAGING {
779 compatible = "nxp,imx8-pd"; 792 compatible = "nxp,imx8-pd";
780 reg = <SC_R_ISI_CH0>; 793 reg = <SC_R_ISI_CH0>;
781 #power-domain-cells = <0>; 794 #power-domain-cells = <0>;
782 #address-cells = <1>; 795 #address-cells = <1>;
783 #size-cells = <0>; 796 #size-cells = <0>;
784 797
785 pd_mipi_csi: PD_MIPI_CSI0 { 798 pd_mipi_csi: PD_MIPI_CSI0 {
786 reg = <SC_R_CSI_0>; 799 reg = <SC_R_CSI_0>;
787 #power-domain-cells = <0>; 800 #power-domain-cells = <0>;
788 #address-cells = <1>; 801 #address-cells = <1>;
789 #size-cells = <0>; 802 #size-cells = <0>;
790 power-domains =<&pd_isi_ch0>; 803 power-domains =<&pd_isi_ch0>;
791 804
792 pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C { 805 pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C {
793 name = "mipi_csi0_i2c"; 806 name = "mipi_csi0_i2c";
794 reg = <SC_R_CSI_0_I2C_0>; 807 reg = <SC_R_CSI_0_I2C_0>;
795 #power-domain-cells = <0>; 808 #power-domain-cells = <0>;
796 power-domains =<&pd_mipi_csi>; 809 power-domains =<&pd_mipi_csi>;
797 }; 810 };
798 811
799 pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { 812 pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM {
800 name = "mipi_csi0_pwm"; 813 name = "mipi_csi0_pwm";
801 reg = <SC_R_CSI_0_PWM_0>; 814 reg = <SC_R_CSI_0_PWM_0>;
802 #power-domain-cells = <0>; 815 #power-domain-cells = <0>;
803 power-domains =<&pd_mipi_csi>; 816 power-domains =<&pd_mipi_csi>;
804 }; 817 };
805 }; 818 };
806 819
807 pd_isi_ch1: PD_IMAGING_PDMA1 { 820 pd_isi_ch1: PD_IMAGING_PDMA1 {
808 reg = <SC_R_ISI_CH1>; 821 reg = <SC_R_ISI_CH1>;
809 #power-domain-cells = <0>; 822 #power-domain-cells = <0>;
810 power-domains =<&pd_isi_ch0>; 823 power-domains =<&pd_isi_ch0>;
811 }; 824 };
812 825
813 pd_isi_ch2: PD_IMAGING_PDMA2 { 826 pd_isi_ch2: PD_IMAGING_PDMA2 {
814 reg = <SC_R_ISI_CH2>; 827 reg = <SC_R_ISI_CH2>;
815 #power-domain-cells = <0>; 828 #power-domain-cells = <0>;
816 power-domains =<&pd_isi_ch0>; 829 power-domains =<&pd_isi_ch0>;
817 }; 830 };
818 831
819 pd_isi_ch3: PD_IMAGING_PDMA3 { 832 pd_isi_ch3: PD_IMAGING_PDMA3 {
820 reg = <SC_R_ISI_CH3>; 833 reg = <SC_R_ISI_CH3>;
821 #power-domain-cells = <0>; 834 #power-domain-cells = <0>;
822 power-domains =<&pd_isi_ch0>; 835 power-domains =<&pd_isi_ch0>;
823 }; 836 };
824 837
825 pd_isi_ch4: PD_IMAGING_PDMA4 { 838 pd_isi_ch4: PD_IMAGING_PDMA4 {
826 reg = <SC_R_ISI_CH4>; 839 reg = <SC_R_ISI_CH4>;
827 #power-domain-cells = <0>; 840 #power-domain-cells = <0>;
828 power-domains =<&pd_isi_ch0>; 841 power-domains =<&pd_isi_ch0>;
829 }; 842 };
830 843
831 pd_isi_ch5: PD_IMAGING_PDMA5 { 844 pd_isi_ch5: PD_IMAGING_PDMA5 {
832 reg = <SC_R_ISI_CH5>; 845 reg = <SC_R_ISI_CH5>;
833 #power-domain-cells = <0>; 846 #power-domain-cells = <0>;
834 power-domains =<&pd_isi_ch0>; 847 power-domains =<&pd_isi_ch0>;
835 }; 848 };
836 849
837 pd_isi_ch6: PD_IMAGING_PDMA6 { 850 pd_isi_ch6: PD_IMAGING_PDMA6 {
838 reg = <SC_R_ISI_CH6>; 851 reg = <SC_R_ISI_CH6>;
839 #power-domain-cells = <0>; 852 #power-domain-cells = <0>;
840 power-domains =<&pd_isi_ch0>; 853 power-domains =<&pd_isi_ch0>;
841 }; 854 };
842 855
843 pd_isi_ch7: PD_IMAGING_PDMA7 { 856 pd_isi_ch7: PD_IMAGING_PDMA7 {
844 reg = <SC_R_ISI_CH7>; 857 reg = <SC_R_ISI_CH7>;
845 #power-domain-cells = <0>; 858 #power-domain-cells = <0>;
846 power-domains =<&pd_isi_ch0>; 859 power-domains =<&pd_isi_ch0>;
847 }; 860 };
848 }; 861 };
849 }; 862 };
850 863
851 tsens: thermal-sensor { 864 tsens: thermal-sensor {
852 compatible = "nxp,imx8qxp-sc-tsens"; 865 compatible = "nxp,imx8qxp-sc-tsens";
853 u-boot,dm-pre-reloc; 866 u-boot,dm-pre-reloc;
854 /* number of the temp sensor on the chip */ 867 /* number of the temp sensor on the chip */
855 tsens-num = <1>; 868 tsens-num = <1>;
856 #thermal-sensor-cells = <1>; 869 #thermal-sensor-cells = <1>;
857 }; 870 };
858 871
859 thermal-zones { 872 thermal-zones {
860 /* cpu thermal */ 873 /* cpu thermal */
861 cpu-thermal0 { 874 cpu-thermal0 {
862 polling-delay-passive = <250>; 875 polling-delay-passive = <250>;
863 polling-delay = <2000>; 876 polling-delay = <2000>;
864 /*the slope and offset of the temp sensor */ 877 /*the slope and offset of the temp sensor */
865 thermal-sensors = <&tsens 0>; 878 thermal-sensors = <&tsens 0>;
866 trips { 879 trips {
867 cpu_alert0: trip0 { 880 cpu_alert0: trip0 {
868 temperature = <107000>; 881 temperature = <107000>;
869 hysteresis = <2000>; 882 hysteresis = <2000>;
870 type = "passive"; 883 type = "passive";
871 }; 884 };
872 cpu_crit0: trip1 { 885 cpu_crit0: trip1 {
873 temperature = <127000>; 886 temperature = <127000>;
874 hysteresis = <2000>; 887 hysteresis = <2000>;
875 type = "critical"; 888 type = "critical";
876 }; 889 };
877 }; 890 };
878 }; 891 };
879 }; 892 };
880 893
881 gpio0: gpio@5d080000 { 894 gpio0: gpio@5d080000 {
882 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 895 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
883 reg = <0x0 0x5d080000 0x0 0x10000>; 896 reg = <0x0 0x5d080000 0x0 0x10000>;
884 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 897 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
885 gpio-controller; 898 gpio-controller;
886 #gpio-cells = <2>; 899 #gpio-cells = <2>;
887 interrupt-controller; 900 interrupt-controller;
888 #interrupt-cells = <2>; 901 #interrupt-cells = <2>;
889 power-domains = <&pd_lsio_gpio0>; 902 power-domains = <&pd_lsio_gpio0>;
890 }; 903 };
891 904
892 gpio1: gpio@5d090000 { 905 gpio1: gpio@5d090000 {
893 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 906 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
894 reg = <0x0 0x5d090000 0x0 0x10000>; 907 reg = <0x0 0x5d090000 0x0 0x10000>;
895 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 908 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
896 gpio-controller; 909 gpio-controller;
897 #gpio-cells = <2>; 910 #gpio-cells = <2>;
898 interrupt-controller; 911 interrupt-controller;
899 #interrupt-cells = <2>; 912 #interrupt-cells = <2>;
900 power-domains = <&pd_lsio_gpio1>; 913 power-domains = <&pd_lsio_gpio1>;
901 }; 914 };
902 915
903 gpio2: gpio@5d0a0000 { 916 gpio2: gpio@5d0a0000 {
904 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 917 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
905 reg = <0x0 0x5d0a0000 0x0 0x10000>; 918 reg = <0x0 0x5d0a0000 0x0 0x10000>;
906 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 919 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
907 gpio-controller; 920 gpio-controller;
908 #gpio-cells = <2>; 921 #gpio-cells = <2>;
909 interrupt-controller; 922 interrupt-controller;
910 #interrupt-cells = <2>; 923 #interrupt-cells = <2>;
911 power-domains = <&pd_lsio_gpio2>; 924 power-domains = <&pd_lsio_gpio2>;
912 }; 925 };
913 926
914 gpio3: gpio@5d0b0000 { 927 gpio3: gpio@5d0b0000 {
915 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 928 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
916 reg = <0x0 0x5d0b0000 0x0 0x10000>; 929 reg = <0x0 0x5d0b0000 0x0 0x10000>;
917 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 930 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
918 gpio-controller; 931 gpio-controller;
919 #gpio-cells = <2>; 932 #gpio-cells = <2>;
920 interrupt-controller; 933 interrupt-controller;
921 #interrupt-cells = <2>; 934 #interrupt-cells = <2>;
922 power-domains = <&pd_lsio_gpio3>; 935 power-domains = <&pd_lsio_gpio3>;
923 }; 936 };
924 937
925 gpio4: gpio@5d0c0000 { 938 gpio4: gpio@5d0c0000 {
926 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 939 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
927 reg = <0x0 0x5d0c0000 0x0 0x10000>; 940 reg = <0x0 0x5d0c0000 0x0 0x10000>;
928 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 941 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
929 gpio-controller; 942 gpio-controller;
930 #gpio-cells = <2>; 943 #gpio-cells = <2>;
931 interrupt-controller; 944 interrupt-controller;
932 #interrupt-cells = <2>; 945 #interrupt-cells = <2>;
933 power-domains = <&pd_lsio_gpio4>; 946 power-domains = <&pd_lsio_gpio4>;
934 }; 947 };
935 948
936 gpio5: gpio@5d0d0000 { 949 gpio5: gpio@5d0d0000 {
937 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 950 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
938 reg = <0x0 0x5d0d0000 0x0 0x10000>; 951 reg = <0x0 0x5d0d0000 0x0 0x10000>;
939 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 952 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
940 gpio-controller; 953 gpio-controller;
941 #gpio-cells = <2>; 954 #gpio-cells = <2>;
942 interrupt-controller; 955 interrupt-controller;
943 #interrupt-cells = <2>; 956 #interrupt-cells = <2>;
944 power-domains = <&pd_lsio_gpio5>; 957 power-domains = <&pd_lsio_gpio5>;
945 }; 958 };
946 959
947 gpio6: gpio@5d0e0000 { 960 gpio6: gpio@5d0e0000 {
948 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 961 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
949 reg = <0x0 0x5d0e0000 0x0 0x10000>; 962 reg = <0x0 0x5d0e0000 0x0 0x10000>;
950 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 963 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
951 gpio-controller; 964 gpio-controller;
952 #gpio-cells = <2>; 965 #gpio-cells = <2>;
953 interrupt-controller; 966 interrupt-controller;
954 #interrupt-cells = <2>; 967 #interrupt-cells = <2>;
955 power-domains = <&pd_lsio_gpio6>; 968 power-domains = <&pd_lsio_gpio6>;
956 }; 969 };
957 970
958 gpio7: gpio@5d0f0000 { 971 gpio7: gpio@5d0f0000 {
959 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 972 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
960 reg = <0x0 0x5d0f0000 0x0 0x10000>; 973 reg = <0x0 0x5d0f0000 0x0 0x10000>;
961 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 974 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
962 gpio-controller; 975 gpio-controller;
963 #gpio-cells = <2>; 976 #gpio-cells = <2>;
964 interrupt-controller; 977 interrupt-controller;
965 #interrupt-cells = <2>; 978 #interrupt-cells = <2>;
966 power-domains = <&pd_lsio_gpio7>; 979 power-domains = <&pd_lsio_gpio7>;
967 }; 980 };
968 981
969 irqsteer_csi: irqsteer@58220000 { 982 irqsteer_csi: irqsteer@58220000 {
970 compatible = "nxp,imx-irqsteer"; 983 compatible = "nxp,imx-irqsteer";
971 reg = <0x0 0x58220000 0x0 0x1000>; 984 reg = <0x0 0x58220000 0x0 0x1000>;
972 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 985 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
973 interrupt-controller; 986 interrupt-controller;
974 interrupt-parent = <&gic>; 987 interrupt-parent = <&gic>;
975 #interrupt-cells = <2>; 988 #interrupt-cells = <2>;
976 clocks = <&clk IMX8QXP_CSI0_IPG_CLK>; 989 clocks = <&clk IMX8QXP_CSI0_IPG_CLK>;
977 clock-names = "ipg"; 990 clock-names = "ipg";
978 power-domains = <&pd_mipi_csi>; 991 power-domains = <&pd_mipi_csi>;
979 }; 992 };
980 993
981 i2c0_csi0: i2c@58226000 { 994 i2c0_csi0: i2c@58226000 {
982 compatible = "fsl,imx8qm-lpi2c"; 995 compatible = "fsl,imx8qm-lpi2c";
983 reg = <0x0 0x58226000 0x0 0x1000>; 996 reg = <0x0 0x58226000 0x0 0x1000>;
984 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 997 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
985 interrupt-parent = <&irqsteer_csi>; 998 interrupt-parent = <&irqsteer_csi>;
986 clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, 999 clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>,
987 <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; 1000 <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>;
988 clock-names = "per", "ipg"; 1001 clock-names = "per", "ipg";
989 assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; 1002 assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>;
990 assigned-clock-rates = <24000000>; 1003 assigned-clock-rates = <24000000>;
991 power-domains = <&pd_mipi_csi_i2c0>; 1004 power-domains = <&pd_mipi_csi_i2c0>;
992 status = "disabled"; 1005 status = "disabled";
993 }; 1006 };
994 1007
995 intmux_cm40: intmux@37400000 { 1008 intmux_cm40: intmux@37400000 {
996 compatible = "nxp,imx-intmux"; 1009 compatible = "nxp,imx-intmux";
997 reg = <0x0 0x37400000 0x0 0x1000>; 1010 reg = <0x0 0x37400000 0x0 0x1000>;
998 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1011 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1018 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1006 interrupt-controller; 1019 interrupt-controller;
1007 interrupt-parent = <&gic>; 1020 interrupt-parent = <&gic>;
1008 #interrupt-cells = <2>; 1021 #interrupt-cells = <2>;
1009 clocks = <&clk IMX8QXP_CM40_IPG_CLK>; 1022 clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
1010 clock-names = "ipg"; 1023 clock-names = "ipg";
1011 power-domains = <&pd_cm40_intmux>; 1024 power-domains = <&pd_cm40_intmux>;
1012 status = "disabled"; 1025 status = "disabled";
1013 }; 1026 };
1014 1027
1015 i2c0_cm40: i2c@37230000 { 1028 i2c0_cm40: i2c@37230000 {
1016 compatible = "fsl,imx8qm-lpi2c"; 1029 compatible = "fsl,imx8qm-lpi2c";
1017 reg = <0x0 0x37230000 0x0 0x1000>; 1030 reg = <0x0 0x37230000 0x0 0x1000>;
1018 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 1031 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
1019 interrupt-parent = <&intmux_cm40>; 1032 interrupt-parent = <&intmux_cm40>;
1020 clocks = <&clk IMX8QXP_CM40_I2C_CLK>, 1033 clocks = <&clk IMX8QXP_CM40_I2C_CLK>,
1021 <&clk IMX8QXP_CM40_I2C_IPG_CLK>; 1034 <&clk IMX8QXP_CM40_I2C_IPG_CLK>;
1022 clock-names = "per", "ipg"; 1035 clock-names = "per", "ipg";
1023 assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; 1036 assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>;
1024 assigned-clock-rates = <24000000>; 1037 assigned-clock-rates = <24000000>;
1025 power-domains = <&pd_cm40_i2c>; 1038 power-domains = <&pd_cm40_i2c>;
1026 status = "disabled"; 1039 status = "disabled";
1027 }; 1040 };
1028 1041
1029 dpu_intsteer: dpu_intsteer@56000000 { 1042 dpu_intsteer: dpu_intsteer@56000000 {
1030 compatible = "fsl,imx8qxp-dpu-intsteer", "syscon"; 1043 compatible = "fsl,imx8qxp-dpu-intsteer", "syscon";
1031 reg = <0x0 0x56000000 0x0 0x10000>; 1044 reg = <0x0 0x56000000 0x0 0x10000>;
1032 }; 1045 };
1033 1046
1034 dpu1: dpu@56180000 { 1047 dpu1: dpu@56180000 {
1035 #address-cells = <1>; 1048 #address-cells = <1>;
1036 #size-cells = <0>; 1049 #size-cells = <0>;
1037 compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu"; 1050 compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu";
1038 reg = <0x0 0x56180000 0x0 0x40000>; 1051 reg = <0x0 0x56180000 0x0 0x40000>;
1039 intsteer = <&dpu_intsteer>; 1052 intsteer = <&dpu_intsteer>;
1040 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1053 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1060 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "irq_common", 1061 interrupt-names = "irq_common",
1049 "irq_stream0a", 1062 "irq_stream0a",
1050 "irq_stream0b", /* to M4? */ 1063 "irq_stream0b", /* to M4? */
1051 "irq_stream1a", 1064 "irq_stream1a",
1052 "irq_stream1b", /* to M4? */ 1065 "irq_stream1b", /* to M4? */
1053 "irq_reserved0", 1066 "irq_reserved0",
1054 "irq_reserved1", 1067 "irq_reserved1",
1055 "irq_blit"; 1068 "irq_blit";
1056 clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, 1069 clocks = <&clk IMX8QXP_DC0_PLL0_CLK>,
1057 <&clk IMX8QXP_DC0_PLL1_CLK>, 1070 <&clk IMX8QXP_DC0_PLL1_CLK>,
1058 <&clk IMX8QXP_DC0_DISP0_CLK>, 1071 <&clk IMX8QXP_DC0_DISP0_CLK>,
1059 <&clk IMX8QXP_DC0_DISP1_CLK>; 1072 <&clk IMX8QXP_DC0_DISP1_CLK>;
1060 clock-names = "pll0", "pll1", "disp0", "disp1"; 1073 clock-names = "pll0", "pll1", "disp0", "disp1";
1061 power-domains = <&pd_dc0_pll1>; 1074 power-domains = <&pd_dc0_pll1>;
1062 status = "disabled"; 1075 status = "disabled";
1063 1076
1064 dpu_disp0: port@0 { 1077 dpu_disp0: port@0 {
1065 reg = <0>; 1078 reg = <0>;
1066 1079
1067 dpu_disp0_lvds0_ch0: lvds0-endpoint { 1080 dpu_disp0_lvds0_ch0: lvds0-endpoint {
1068 remote-endpoint = <&ldb1_ch0>; 1081 remote-endpoint = <&ldb1_ch0>;
1069 }; 1082 };
1070 1083
1071 dpu_disp0_lvds0_ch1: lvds1-endpoint { 1084 dpu_disp0_lvds0_ch1: lvds1-endpoint {
1072 remote-endpoint = <&ldb1_ch1>; 1085 remote-endpoint = <&ldb1_ch1>;
1073 }; 1086 };
1074 1087
1075 dpu_disp0_mipi_dsi: mipi-dsi-endpoint { 1088 dpu_disp0_mipi_dsi: mipi-dsi-endpoint {
1076 }; 1089 };
1077 }; 1090 };
1078 1091
1079 dpu_disp1: port@1 { 1092 dpu_disp1: port@1 {
1080 reg = <1>; 1093 reg = <1>;
1081 1094
1082 dpu_disp1_lvds1_ch0: lvds0-endpoint { 1095 dpu_disp1_lvds1_ch0: lvds0-endpoint {
1083 remote-endpoint = <&ldb2_ch0>; 1096 remote-endpoint = <&ldb2_ch0>;
1084 }; 1097 };
1085 1098
1086 dpu_disp1_lvds1_ch1: lvds1-endpoint { 1099 dpu_disp1_lvds1_ch1: lvds1-endpoint {
1087 remote-endpoint = <&ldb2_ch1>; 1100 remote-endpoint = <&ldb2_ch1>;
1088 }; 1101 };
1089 1102
1090 dpu_disp1_mipi_dsi: mipi-dsi-endpoint { 1103 dpu_disp1_mipi_dsi: mipi-dsi-endpoint {
1091 }; 1104 };
1092 }; 1105 };
1093 }; 1106 };
1094 1107
1095 irqsteer_mipi_lvds0: irqsteer@56220000 { 1108 irqsteer_mipi_lvds0: irqsteer@56220000 {
1096 compatible = "nxp,imx-irqsteer"; 1109 compatible = "nxp,imx-irqsteer";
1097 reg = <0x0 0x56220000 0x0 0x1000>; 1110 reg = <0x0 0x56220000 0x0 0x1000>;
1098 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1111 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1099 interrupt-controller; 1112 interrupt-controller;
1100 interrupt-parent = <&gic>; 1113 interrupt-parent = <&gic>;
1101 #interrupt-cells = <2>; 1114 #interrupt-cells = <2>;
1102 clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; 1115 clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>;
1103 clock-names = "ipg"; 1116 clock-names = "ipg";
1104 power-domains = <&pd_mipi_dsi0>; 1117 power-domains = <&pd_mipi_dsi0>;
1105 }; 1118 };
1106 1119
1107 lvds_region1: lvds_region@56220000 { 1120 lvds_region1: lvds_region@56220000 {
1108 compatible = "fsl,imx8qxp-lvds-region", "syscon"; 1121 compatible = "fsl,imx8qxp-lvds-region", "syscon";
1109 reg = <0x0 0x56220000 0x0 0x10000>; 1122 reg = <0x0 0x56220000 0x0 0x10000>;
1110 }; 1123 };
1111 1124
1112 ldb1_phy: ldb_phy@56221000 { 1125 ldb1_phy: ldb_phy@56221000 {
1113 compatible = "mixel,lvds-combo-phy"; 1126 compatible = "mixel,lvds-combo-phy";
1114 reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; 1127 reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>;
1115 #phy-cells = <0>; 1128 #phy-cells = <0>;
1116 clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; 1129 clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>;
1117 clock-names = "phy"; 1130 clock-names = "phy";
1118 power-domains = <&pd_mipi_dsi_0_lvds>; 1131 power-domains = <&pd_mipi_dsi_0_lvds>;
1119 status = "disabled"; 1132 status = "disabled";
1120 }; 1133 };
1121 1134
1122 ldb1: ldb@562210e0 { 1135 ldb1: ldb@562210e0 {
1123 #address-cells = <1>; 1136 #address-cells = <1>;
1124 #size-cells = <0>; 1137 #size-cells = <0>;
1125 compatible = "fsl,imx8qxp-ldb"; 1138 compatible = "fsl,imx8qxp-ldb";
1126 clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, 1139 clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>,
1127 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; 1140 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>;
1128 clock-names = "pixel", "bypass"; 1141 clock-names = "pixel", "bypass";
1129 power-domains = <&pd_mipi_dsi_0_lvds>; 1142 power-domains = <&pd_mipi_dsi_0_lvds>;
1130 gpr = <&lvds_region1>; 1143 gpr = <&lvds_region1>;
1131 status = "disabled"; 1144 status = "disabled";
1132 1145
1133 lvds-channel@0 { 1146 lvds-channel@0 {
1134 #address-cells = <1>; 1147 #address-cells = <1>;
1135 #size-cells = <0>; 1148 #size-cells = <0>;
1136 reg = <0>; 1149 reg = <0>;
1137 phys = <&ldb1_phy>; 1150 phys = <&ldb1_phy>;
1138 phy-names = "ldb_phy"; 1151 phy-names = "ldb_phy";
1139 status = "disabled"; 1152 status = "disabled";
1140 1153
1141 port@0 { 1154 port@0 {
1142 reg = <0>; 1155 reg = <0>;
1143 1156
1144 ldb1_ch0: endpoint { 1157 ldb1_ch0: endpoint {
1145 remote-endpoint = <&dpu_disp0_lvds0_ch0>; 1158 remote-endpoint = <&dpu_disp0_lvds0_ch0>;
1146 }; 1159 };
1147 }; 1160 };
1148 }; 1161 };
1149 1162
1150 lvds-channel@1 { 1163 lvds-channel@1 {
1151 #address-cells = <1>; 1164 #address-cells = <1>;
1152 #size-cells = <0>; 1165 #size-cells = <0>;
1153 reg = <1>; 1166 reg = <1>;
1154 phys = <&ldb1_phy>; 1167 phys = <&ldb1_phy>;
1155 phy-names = "ldb_phy"; 1168 phy-names = "ldb_phy";
1156 status = "disabled"; 1169 status = "disabled";
1157 1170
1158 port@0 { 1171 port@0 {
1159 reg = <0>; 1172 reg = <0>;
1160 1173
1161 ldb1_ch1: endpoint { 1174 ldb1_ch1: endpoint {
1162 remote-endpoint = <&dpu_disp0_lvds0_ch1>; 1175 remote-endpoint = <&dpu_disp0_lvds0_ch1>;
1163 }; 1176 };
1164 }; 1177 };
1165 }; 1178 };
1166 }; 1179 };
1167 1180
1168 i2c0_mipi_lvds0: i2c@56226000 { 1181 i2c0_mipi_lvds0: i2c@56226000 {
1169 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; 1182 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
1170 reg = <0x0 0x56226000 0x0 0x1000>; 1183 reg = <0x0 0x56226000 0x0 0x1000>;
1171 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1184 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1172 interrupt-parent = <&irqsteer_mipi_lvds0>; 1185 interrupt-parent = <&irqsteer_mipi_lvds0>;
1173 clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, 1186 clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>,
1174 <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; 1187 <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>;
1175 clock-names = "per", "ipg"; 1188 clock-names = "per", "ipg";
1176 assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; 1189 assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>;
1177 assigned-clock-rates = <24000000>; 1190 assigned-clock-rates = <24000000>;
1178 power-domains = <&pd_mipi_dsi_0_i2c0>; 1191 power-domains = <&pd_mipi_dsi_0_i2c0>;
1179 status = "disabled"; 1192 status = "disabled";
1180 }; 1193 };
1181 1194
1182 irqsteer_mipi_lvds1: irqsteer@56240000 { 1195 irqsteer_mipi_lvds1: irqsteer@56240000 {
1183 compatible = "nxp,imx-irqsteer"; 1196 compatible = "nxp,imx-irqsteer";
1184 reg = <0x0 0x56240000 0x0 0x1000>; 1197 reg = <0x0 0x56240000 0x0 0x1000>;
1185 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1186 interrupt-controller; 1199 interrupt-controller;
1187 interrupt-parent = <&gic>; 1200 interrupt-parent = <&gic>;
1188 #interrupt-cells = <2>; 1201 #interrupt-cells = <2>;
1189 clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; 1202 clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>;
1190 clock-names = "ipg"; 1203 clock-names = "ipg";
1191 power-domains = <&pd_mipi_dsi1>; 1204 power-domains = <&pd_mipi_dsi1>;
1192 }; 1205 };
1193 1206
1194 lvds_region2: lvds_region@56240000 { 1207 lvds_region2: lvds_region@56240000 {
1195 compatible = "fsl,imx8qxp-lvds-region", "syscon"; 1208 compatible = "fsl,imx8qxp-lvds-region", "syscon";
1196 reg = <0x0 0x56240000 0x0 0x10000>; 1209 reg = <0x0 0x56240000 0x0 0x10000>;
1197 }; 1210 };
1198 1211
1199 ldb2_phy: ldb_phy@56241000 { 1212 ldb2_phy: ldb_phy@56241000 {
1200 compatible = "mixel,lvds-combo-phy"; 1213 compatible = "mixel,lvds-combo-phy";
1201 reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; 1214 reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>;
1202 #phy-cells = <0>; 1215 #phy-cells = <0>;
1203 clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; 1216 clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>;
1204 clock-names = "phy"; 1217 clock-names = "phy";
1205 power-domains = <&pd_mipi_dsi_1_lvds>; 1218 power-domains = <&pd_mipi_dsi_1_lvds>;
1206 status = "disabled"; 1219 status = "disabled";
1207 }; 1220 };
1208 1221
1209 ldb2: ldb@562410e0 { 1222 ldb2: ldb@562410e0 {
1210 #address-cells = <1>; 1223 #address-cells = <1>;
1211 #size-cells = <0>; 1224 #size-cells = <0>;
1212 compatible = "fsl,imx8qxp-ldb"; 1225 compatible = "fsl,imx8qxp-ldb";
1213 clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, 1226 clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>,
1214 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; 1227 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>;
1215 clock-names = "pixel", "bypass"; 1228 clock-names = "pixel", "bypass";
1216 power-domains = <&pd_mipi_dsi_1_lvds>; 1229 power-domains = <&pd_mipi_dsi_1_lvds>;
1217 gpr = <&lvds_region2>; 1230 gpr = <&lvds_region2>;
1218 status = "disabled"; 1231 status = "disabled";
1219 1232
1220 lvds-channel@0 { 1233 lvds-channel@0 {
1221 #address-cells = <1>; 1234 #address-cells = <1>;
1222 #size-cells = <0>; 1235 #size-cells = <0>;
1223 reg = <0>; 1236 reg = <0>;
1224 phys = <&ldb2_phy>; 1237 phys = <&ldb2_phy>;
1225 phy-names = "ldb_phy"; 1238 phy-names = "ldb_phy";
1226 status = "disabled"; 1239 status = "disabled";
1227 1240
1228 port@0 { 1241 port@0 {
1229 reg = <0>; 1242 reg = <0>;
1230 1243
1231 ldb2_ch0: endpoint { 1244 ldb2_ch0: endpoint {
1232 remote-endpoint = <&dpu_disp1_lvds1_ch0>; 1245 remote-endpoint = <&dpu_disp1_lvds1_ch0>;
1233 }; 1246 };
1234 }; 1247 };
1235 }; 1248 };
1236 1249
1237 lvds-channel@1 { 1250 lvds-channel@1 {
1238 #address-cells = <1>; 1251 #address-cells = <1>;
1239 #size-cells = <0>; 1252 #size-cells = <0>;
1240 reg = <1>; 1253 reg = <1>;
1241 phys = <&ldb2_phy>; 1254 phys = <&ldb2_phy>;
1242 phy-names = "ldb_phy"; 1255 phy-names = "ldb_phy";
1243 status = "disabled"; 1256 status = "disabled";
1244 1257
1245 port@0 { 1258 port@0 {
1246 reg = <0>; 1259 reg = <0>;
1247 1260
1248 ldb2_ch1: endpoint { 1261 ldb2_ch1: endpoint {
1249 remote-endpoint = <&dpu_disp1_lvds1_ch1>; 1262 remote-endpoint = <&dpu_disp1_lvds1_ch1>;
1250 }; 1263 };
1251 }; 1264 };
1252 }; 1265 };
1253 }; 1266 };
1254 1267
1255 camera { 1268 camera {
1256 compatible = "fsl,mxc-md", "simple-bus"; 1269 compatible = "fsl,mxc-md", "simple-bus";
1257 #address-cells = <2>; 1270 #address-cells = <2>;
1258 #size-cells = <2>; 1271 #size-cells = <2>;
1259 ranges; 1272 ranges;
1260 1273
1261 isi_0: isi@58100000 { 1274 isi_0: isi@58100000 {
1262 compatible = "fsl,imx8-isi"; 1275 compatible = "fsl,imx8-isi";
1263 reg = <0x0 0x58100000 0x0 0x10000>; 1276 reg = <0x0 0x58100000 0x0 0x10000>;
1264 interrupts = <0 297 0>; 1277 interrupts = <0 297 0>;
1265 interface = <2 0 2>; /* <Input MIPI_VCx Output> 1278 interface = <2 0 2>; /* <Input MIPI_VCx Output>
1266 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM 1279 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
1267 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only 1280 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
1268 Output: 0-DC0, 1-DC1, 2-MEM */ 1281 Output: 0-DC0, 1-DC1, 2-MEM */
1269 clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; 1282 clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>;
1270 clock-names = "per"; 1283 clock-names = "per";
1271 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; 1284 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>;
1272 assigned-clock-rates = <600000000>; 1285 assigned-clock-rates = <600000000>;
1273 power-domains =<&pd_isi_ch0>; 1286 power-domains =<&pd_isi_ch0>;
1274 status = "disabled"; 1287 status = "disabled";
1275 }; 1288 };
1276 1289
1277 isi_1: isi@58110000 { 1290 isi_1: isi@58110000 {
1278 compatible = "fsl,imx8-isi"; 1291 compatible = "fsl,imx8-isi";
1279 reg = <0x0 0x58110000 0x0 0x10000>; 1292 reg = <0x0 0x58110000 0x0 0x10000>;
1280 interrupts = <0 298 0>; 1293 interrupts = <0 298 0>;
1281 interface = <2 1 2>; 1294 interface = <2 1 2>;
1282 clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; 1295 clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>;
1283 clock-names = "per"; 1296 clock-names = "per";
1284 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; 1297 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>;
1285 assigned-clock-rates = <600000000>; 1298 assigned-clock-rates = <600000000>;
1286 power-domains =<&pd_isi_ch1>; 1299 power-domains =<&pd_isi_ch1>;
1287 status = "disabled"; 1300 status = "disabled";
1288 }; 1301 };
1289 1302
1290 isi_2: isi@58120000 { 1303 isi_2: isi@58120000 {
1291 compatible = "fsl,imx8-isi"; 1304 compatible = "fsl,imx8-isi";
1292 reg = <0x0 0x58120000 0x0 0x10000>; 1305 reg = <0x0 0x58120000 0x0 0x10000>;
1293 interrupts = <0 299 0>; 1306 interrupts = <0 299 0>;
1294 interface = <2 2 2>; 1307 interface = <2 2 2>;
1295 clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; 1308 clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>;
1296 clock-names = "per"; 1309 clock-names = "per";
1297 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; 1310 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>;
1298 assigned-clock-rates = <600000000>; 1311 assigned-clock-rates = <600000000>;
1299 power-domains =<&pd_isi_ch2>; 1312 power-domains =<&pd_isi_ch2>;
1300 status = "disabled"; 1313 status = "disabled";
1301 }; 1314 };
1302 1315
1303 isi_3: isi@58130000 { 1316 isi_3: isi@58130000 {
1304 compatible = "fsl,imx8-isi"; 1317 compatible = "fsl,imx8-isi";
1305 reg = <0x0 0x58130000 0x0 0x10000>; 1318 reg = <0x0 0x58130000 0x0 0x10000>;
1306 interrupts = <0 300 0>; 1319 interrupts = <0 300 0>;
1307 interface = <2 3 2>; 1320 interface = <2 3 2>;
1308 clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; 1321 clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>;
1309 clock-names = "per"; 1322 clock-names = "per";
1310 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; 1323 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>;
1311 assigned-clock-rates = <600000000>; 1324 assigned-clock-rates = <600000000>;
1312 power-domains =<&pd_isi_ch3>; 1325 power-domains =<&pd_isi_ch3>;
1313 status = "disabled"; 1326 status = "disabled";
1314 }; 1327 };
1315 1328
1316 isi_4: isi@58140000 { 1329 isi_4: isi@58140000 {
1317 compatible = "fsl,imx8-isi"; 1330 compatible = "fsl,imx8-isi";
1318 reg = <0x0 0x58140000 0x0 0x10000>; 1331 reg = <0x0 0x58140000 0x0 0x10000>;
1319 interrupts = <0 301 0>; 1332 interrupts = <0 301 0>;
1320 interface = <3 0 2>; 1333 interface = <3 0 2>;
1321 clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; 1334 clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>;
1322 clock-names = "per"; 1335 clock-names = "per";
1323 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; 1336 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>;
1324 assigned-clock-rates = <600000000>; 1337 assigned-clock-rates = <600000000>;
1325 power-domains =<&pd_isi_ch4>; 1338 power-domains =<&pd_isi_ch4>;
1326 status = "disabled"; 1339 status = "disabled";
1327 }; 1340 };
1328 1341
1329 isi_5: isi@58150000 { 1342 isi_5: isi@58150000 {
1330 compatible = "fsl,imx8-isi"; 1343 compatible = "fsl,imx8-isi";
1331 reg = <0x0 0x58150000 0x0 0x10000>; 1344 reg = <0x0 0x58150000 0x0 0x10000>;
1332 interrupts = <0 302 0>; 1345 interrupts = <0 302 0>;
1333 interface = <3 1 2>; 1346 interface = <3 1 2>;
1334 clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; 1347 clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>;
1335 clock-names = "per"; 1348 clock-names = "per";
1336 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; 1349 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>;
1337 assigned-clock-rates = <600000000>; 1350 assigned-clock-rates = <600000000>;
1338 power-domains =<&pd_isi_ch5>; 1351 power-domains =<&pd_isi_ch5>;
1339 status = "disabled"; 1352 status = "disabled";
1340 }; 1353 };
1341 1354
1342 isi_6: isi@58160000 { 1355 isi_6: isi@58160000 {
1343 compatible = "fsl,imx8-isi"; 1356 compatible = "fsl,imx8-isi";
1344 reg = <0x0 0x58160000 0x0 0x10000>; 1357 reg = <0x0 0x58160000 0x0 0x10000>;
1345 interrupts = <0 303 0>; 1358 interrupts = <0 303 0>;
1346 interface = <3 2 2>; 1359 interface = <3 2 2>;
1347 clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; 1360 clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>;
1348 clock-names = "per"; 1361 clock-names = "per";
1349 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; 1362 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>;
1350 assigned-clock-rates = <600000000>; 1363 assigned-clock-rates = <600000000>;
1351 power-domains =<&pd_isi_ch6>; 1364 power-domains =<&pd_isi_ch6>;
1352 status = "disabled"; 1365 status = "disabled";
1353 }; 1366 };
1354 1367
1355 isi_7: isi@58170000 { 1368 isi_7: isi@58170000 {
1356 compatible = "fsl,imx8-isi"; 1369 compatible = "fsl,imx8-isi";
1357 reg = <0x0 0x58170000 0x0 0x10000>; 1370 reg = <0x0 0x58170000 0x0 0x10000>;
1358 interrupts = <0 304 0>; 1371 interrupts = <0 304 0>;
1359 interface = <3 3 2>; 1372 interface = <3 3 2>;
1360 clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; 1373 clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>;
1361 clock-names = "per"; 1374 clock-names = "per";
1362 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; 1375 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>;
1363 assigned-clock-rates = <600000000>; 1376 assigned-clock-rates = <600000000>;
1364 power-domains =<&pd_isi_ch7>; 1377 power-domains =<&pd_isi_ch7>;
1365 status = "disabled"; 1378 status = "disabled";
1366 }; 1379 };
1367 1380
1368 mipi_csi_0: csi@58227000 { 1381 mipi_csi_0: csi@58227000 {
1369 compatible = "fsl,mxc-mipi-csi2"; 1382 compatible = "fsl,mxc-mipi-csi2";
1370 reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ 1383 reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */
1371 <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ 1384 <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */
1372 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 1385 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
1373 interrupt-parent = <&irqsteer_csi>; 1386 interrupt-parent = <&irqsteer_csi>;
1374 clocks = <&clk IMX8QXP_CSI0_APB_CLK>, 1387 clocks = <&clk IMX8QXP_CSI0_APB_CLK>,
1375 <&clk IMX8QXP_CSI0_CORE_CLK>, 1388 <&clk IMX8QXP_CSI0_CORE_CLK>,
1376 <&clk IMX8QXP_CSI0_ESC_CLK>, 1389 <&clk IMX8QXP_CSI0_ESC_CLK>,
1377 <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; 1390 <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>;
1378 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; 1391 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
1379 assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>, 1392 assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>,
1380 <&clk IMX8QXP_CSI0_ESC_CLK>; 1393 <&clk IMX8QXP_CSI0_ESC_CLK>;
1381 assigned-clock-rates = <360000000>, <72000000>; 1394 assigned-clock-rates = <360000000>, <72000000>;
1382 power-domains = <&pd_mipi_csi>; 1395 power-domains = <&pd_mipi_csi>;
1383 status = "disabled"; 1396 status = "disabled";
1384 }; 1397 };
1385 }; 1398 };
1386 1399
1387 i2c0_mipi_lvds1: i2c@56246000 { 1400 i2c0_mipi_lvds1: i2c@56246000 {
1388 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; 1401 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
1389 reg = <0x0 0x56246000 0x0 0x1000>; 1402 reg = <0x0 0x56246000 0x0 0x1000>;
1390 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1403 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1391 interrupt-parent = <&irqsteer_mipi_lvds1>; 1404 interrupt-parent = <&irqsteer_mipi_lvds1>;
1392 clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, 1405 clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>,
1393 <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; 1406 <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>;
1394 clock-names = "per", "ipg"; 1407 clock-names = "per", "ipg";
1395 assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; 1408 assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>;
1396 assigned-clock-rates = <24000000>; 1409 assigned-clock-rates = <24000000>;
1397 power-domains = <&pd_mipi_dsi_1_i2c0>; 1410 power-domains = <&pd_mipi_dsi_1_i2c0>;
1398 status = "disabled"; 1411 status = "disabled";
1399 }; 1412 };
1400 1413
1401 i2c0: i2c@5a800000 { 1414 i2c0: i2c@5a800000 {
1402 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1415 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1403 reg = <0x0 0x5a800000 0x0 0x4000>; 1416 reg = <0x0 0x5a800000 0x0 0x4000>;
1404 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1417 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1405 interrupt-parent = <&gic>; 1418 interrupt-parent = <&gic>;
1406 clocks = <&clk IMX8QXP_I2C0_CLK>; 1419 clocks = <&clk IMX8QXP_I2C0_CLK>;
1407 clock-names = "per"; 1420 clock-names = "per";
1408 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; 1421 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
1409 assigned-clock-rates = <24000000>; 1422 assigned-clock-rates = <24000000>;
1410 power-domains = <&pd_dma_lpi2c0>; 1423 power-domains = <&pd_dma_lpi2c0>;
1411 status = "disabled"; 1424 status = "disabled";
1412 }; 1425 };
1413 1426
1414 i2c1: i2c@5a810000 { 1427 i2c1: i2c@5a810000 {
1415 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1428 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1416 reg = <0x0 0x5a810000 0x0 0x4000>; 1429 reg = <0x0 0x5a810000 0x0 0x4000>;
1417 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1430 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1418 interrupt-parent = <&gic>; 1431 interrupt-parent = <&gic>;
1419 clocks = <&clk IMX8QXP_I2C1_CLK>, 1432 clocks = <&clk IMX8QXP_I2C1_CLK>,
1420 <&clk IMX8QXP_I2C1_IPG_CLK>; 1433 <&clk IMX8QXP_I2C1_IPG_CLK>;
1421 clock-names = "per", "ipg"; 1434 clock-names = "per", "ipg";
1422 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; 1435 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
1423 assigned-clock-rates = <24000000>; 1436 assigned-clock-rates = <24000000>;
1424 power-domains = <&pd_dma_lpi2c1>; 1437 power-domains = <&pd_dma_lpi2c1>;
1425 status = "disabled"; 1438 status = "disabled";
1426 }; 1439 };
1427 1440
1428 i2c2: i2c@5a820000 { 1441 i2c2: i2c@5a820000 {
1429 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1442 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1430 reg = <0x0 0x5a820000 0x0 0x4000>; 1443 reg = <0x0 0x5a820000 0x0 0x4000>;
1431 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1432 interrupt-parent = <&gic>; 1445 interrupt-parent = <&gic>;
1433 clocks = <&clk IMX8QXP_I2C2_CLK>; 1446 clocks = <&clk IMX8QXP_I2C2_CLK>;
1434 clock-names = "per"; 1447 clock-names = "per";
1435 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; 1448 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
1436 assigned-clock-rates = <24000000>; 1449 assigned-clock-rates = <24000000>;
1437 power-domains = <&pd_dma_lpi2c2>; 1450 power-domains = <&pd_dma_lpi2c2>;
1438 status = "disabled"; 1451 status = "disabled";
1439 }; 1452 };
1440 1453
1441 i2c3: i2c@5a830000 { 1454 i2c3: i2c@5a830000 {
1442 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1455 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1443 reg = <0x0 0x5a830000 0x0 0x4000>; 1456 reg = <0x0 0x5a830000 0x0 0x4000>;
1444 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1457 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1445 interrupt-parent = <&gic>; 1458 interrupt-parent = <&gic>;
1446 clocks = <&clk IMX8QXP_I2C3_CLK>, 1459 clocks = <&clk IMX8QXP_I2C3_CLK>,
1447 <&clk IMX8QXP_I2C3_IPG_CLK>; 1460 <&clk IMX8QXP_I2C3_IPG_CLK>;
1448 clock-names = "per", "ipg"; 1461 clock-names = "per", "ipg";
1449 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; 1462 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
1450 assigned-clock-rates = <24000000>; 1463 assigned-clock-rates = <24000000>;
1451 power-domains = <&pd_dma_lpi2c3>; 1464 power-domains = <&pd_dma_lpi2c3>;
1452 status = "disabled"; 1465 status = "disabled";
1453 }; 1466 };
1454 1467
1455 usbmisc1: usbmisc@5b0d0200 { 1468 usbmisc1: usbmisc@5b0d0200 {
1456 #index-cells = <1>; 1469 #index-cells = <1>;
1457 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1470 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1458 reg = <0x0 0x5b0d0200 0x0 0x200>; 1471 reg = <0x0 0x5b0d0200 0x0 0x200>;
1459 }; 1472 };
1460 1473
1461 usbphy1: usbphy@0x5b100000 { 1474 usbphy1: usbphy@0x5b100000 {
1462 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 1475 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
1463 reg = <0x0 0x5b100000 0x0 0x200>; 1476 reg = <0x0 0x5b100000 0x0 0x200>;
1464 clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; 1477 clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>;
1465 power-domains = <&pd_conn_usbotg0_phy>; 1478 power-domains = <&pd_conn_usbotg0_phy>;
1466 }; 1479 };
1467 1480
1468 usbotg1: usb@5b0d0000 { 1481 usbotg1: usb@5b0d0000 {
1469 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1482 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1470 reg = <0x0 0x5b0d0000 0x0 0x200>; 1483 reg = <0x0 0x5b0d0000 0x0 0x200>;
1471 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 1484 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1472 fsl,usbphy = <&usbphy1>; 1485 fsl,usbphy = <&usbphy1>;
1473 fsl,usbmisc = <&usbmisc1 0>; 1486 fsl,usbmisc = <&usbmisc1 0>;
1474 clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; 1487 clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>;
1475 phy-clkgate-delay-us = <400>; 1488 phy-clkgate-delay-us = <400>;
1476 status = "disabled"; 1489 status = "disabled";
1477 #stream-id-cells = <1>; 1490 #stream-id-cells = <1>;
1478 power-domains = <&pd_conn_usbotg0>; 1491 power-domains = <&pd_conn_usbotg0>;
1479 }; 1492 };
1480 1493
1481 usb2_phy: phy@0x5b160000 { 1494 usb2_phy: phy@0x5b160000 {
1482 compatible = "fsl,imx8-usb-phy"; 1495 compatible = "fsl,imx8-usb-phy";
1483 reg = <0x0 0x5b160000 0x0 0x10000>; 1496 reg = <0x0 0x5b160000 0x0 0x10000>;
1484 power-domains = <&pd_conn_usb2_phy>; 1497 power-domains = <&pd_conn_usb2_phy>;
1485 }; 1498 };
1486 1499
1487 usb2: usb@0x5b110000 { 1500 usb2: usb@0x5b110000 {
1488 compatible = "fsl,imx8-usb3"; 1501 compatible = "fsl,imx8-usb3";
1489 reg = <0x0 0x5b110000 0x0 0x38000>; 1502 reg = <0x0 0x5b110000 0x0 0x38000>;
1490 fsl,usbphy = <&usb2_phy>; 1503 fsl,usbphy = <&usb2_phy>;
1491 status = "disabled"; 1504 status = "disabled";
1492 power-domains = <&pd_conn_usb2>; 1505 power-domains = <&pd_conn_usb2>;
1493 }; 1506 };
1494 1507
1495 flexcan1: can@5a8d0000 { 1508 flexcan1: can@5a8d0000 {
1496 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 1509 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
1497 reg = <0x0 0x5a8d0000 0x0 0x10000>; 1510 reg = <0x0 0x5a8d0000 0x0 0x10000>;
1498 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1511 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 1512 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
1500 <&clk IMX8QXP_CAN0_CLK>; 1513 <&clk IMX8QXP_CAN0_CLK>;
1501 clock-names = "ipg", "per"; 1514 clock-names = "ipg", "per";
1502 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 1515 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
1503 assigned-clock-rates = <40000000>; 1516 assigned-clock-rates = <40000000>;
1504 power-domains = <&pd_dma_flexcan0>; 1517 power-domains = <&pd_dma_flexcan0>;
1505 status = "disabled"; 1518 status = "disabled";
1506 }; 1519 };
1507 1520
1508 flexcan2: can@5a8e0000 { 1521 flexcan2: can@5a8e0000 {
1509 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 1522 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
1510 reg = <0x0 0x5a8e0000 0x0 0x10000>; 1523 reg = <0x0 0x5a8e0000 0x0 0x10000>;
1511 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1524 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1512 /* CAN0 clock and PD is shared among all CAN instances */ 1525 /* CAN0 clock and PD is shared among all CAN instances */
1513 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 1526 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
1514 <&clk IMX8QXP_CAN0_CLK>; 1527 <&clk IMX8QXP_CAN0_CLK>;
1515 clock-names = "ipg", "per"; 1528 clock-names = "ipg", "per";
1516 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 1529 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
1517 assigned-clock-rates = <40000000>; 1530 assigned-clock-rates = <40000000>;
1518 power-domains = <&pd_dma_flexcan0>; 1531 power-domains = <&pd_dma_flexcan0>;
1519 status = "disabled"; 1532 status = "disabled";
1520 }; 1533 };
1521 1534
1522 flexcan3: can@5a8f0000 { 1535 flexcan3: can@5a8f0000 {
1523 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 1536 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
1524 reg = <0x0 0x5a8f0000 0x0 0x10000>; 1537 reg = <0x0 0x5a8f0000 0x0 0x10000>;
1525 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1538 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1526 /* CAN0 clock and PD is shared among all CAN instances */ 1539 /* CAN0 clock and PD is shared among all CAN instances */
1527 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 1540 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
1528 <&clk IMX8QXP_CAN0_CLK>; 1541 <&clk IMX8QXP_CAN0_CLK>;
1529 clock-names = "ipg", "per"; 1542 clock-names = "ipg", "per";
1530 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 1543 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
1531 assigned-clock-rates = <40000000>; 1544 assigned-clock-rates = <40000000>;
1532 power-domains = <&pd_dma_flexcan0>; 1545 power-domains = <&pd_dma_flexcan0>;
1533 status = "disabled"; 1546 status = "disabled";
1534 }; 1547 };
1535 1548
1536 dma_apbh: dma-apbh@5b810000 { 1549 dma_apbh: dma-apbh@5b810000 {
1537 compatible = "fsl,imx28-dma-apbh"; 1550 compatible = "fsl,imx28-dma-apbh";
1538 reg = <0x0 0x5b810000 0x0 0x2000>; 1551 reg = <0x0 0x5b810000 0x0 0x2000>;
1539 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1552 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 1555 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
1543 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1556 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1544 #dma-cells = <1>; 1557 #dma-cells = <1>;
1545 dma-channels = <4>; 1558 dma-channels = <4>;
1546 clocks = <&clk IMX8QXP_APBHDMA_CLK>; 1559 clocks = <&clk IMX8QXP_APBHDMA_CLK>;
1547 power-domains = <&pd_conn_nand>; 1560 power-domains = <&pd_conn_nand>;
1548 }; 1561 };
1549 1562
1550 gpmi: gpmi-nand@5b812000{ 1563 gpmi: gpmi-nand@5b812000{
1551 compatible = "fsl,imx8qxp-gpmi-nand"; 1564 compatible = "fsl,imx8qxp-gpmi-nand";
1552 #address-cells = <1>; 1565 #address-cells = <1>;
1553 #size-cells = <1>; 1566 #size-cells = <1>;
1554 reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; 1567 reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>;
1555 reg-names = "gpmi-nand", "bch"; 1568 reg-names = "gpmi-nand", "bch";
1556 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1569 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1557 interrupt-names = "bch"; 1570 interrupt-names = "bch";
1558 clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, 1571 clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>,
1559 <&clk IMX8QXP_GPMI_APB_CLK>, 1572 <&clk IMX8QXP_GPMI_APB_CLK>,
1560 <&clk IMX8QXP_GPMI_BCH_CLK>, 1573 <&clk IMX8QXP_GPMI_BCH_CLK>,
1561 <&clk IMX8QXP_GPMI_APB_BCH_CLK>; 1574 <&clk IMX8QXP_GPMI_APB_BCH_CLK>;
1562 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch"; 1575 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch";
1563 dmas = <&dma_apbh 0>; 1576 dmas = <&dma_apbh 0>;
1564 dma-names = "rx-tx"; 1577 dma-names = "rx-tx";
1565 power-domains = <&pd_conn_nand>; 1578 power-domains = <&pd_conn_nand>;
1566 status = "disabled"; 1579 status = "disabled";
1567 }; 1580 };
1568 1581
1569 gpu_3d0: gpu@53100000 { 1582 gpu_3d0: gpu@53100000 {
1570 compatible = "fsl,imx8-gpu"; 1583 compatible = "fsl,imx8-gpu";
1571 reg = <0x0 0x53100000 0 0x40000>; 1584 reg = <0x0 0x53100000 0 0x40000>;
1572 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1585 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1573 clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; 1586 clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
1574 clock-names = "core", "shader"; 1587 clock-names = "core", "shader";
1575 assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; 1588 assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
1576 assigned-clock-rates = <600000000>, <850000000>; 1589 assigned-clock-rates = <600000000>, <850000000>;
1577 power-domains = <&pd_gpu0>; 1590 power-domains = <&pd_gpu0>;
1578 status = "disabled"; 1591 status = "disabled";
1579 }; 1592 };
1580 1593
1581 imx8_gpu_ss: imx8_gpu_ss { 1594 imx8_gpu_ss: imx8_gpu_ss {
1582 compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; 1595 compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
1583 cores = <&gpu_3d0>; 1596 cores = <&gpu_3d0>;
1584 reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; 1597 reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>;
1585 reg-names = "phys_baseaddr", "contiguous_mem"; 1598 reg-names = "phys_baseaddr", "contiguous_mem";
1586 status = "disabled"; 1599 status = "disabled";
1587 }; 1600 };
1588 1601
1589 ddr_pmu0: ddr_pmu@5c020000 { 1602 ddr_pmu0: ddr_pmu@5c020000 {
1590 compatible = "fsl,imx8-ddr-pmu"; 1603 compatible = "fsl,imx8-ddr-pmu";
1591 reg = <0x0 0x5c020000 0x0 0x10000>; 1604 reg = <0x0 0x5c020000 0x0 0x10000>;
1592 interrupt-parent = <&gic>; 1605 interrupt-parent = <&gic>;
1593 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1606 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1594 }; 1607 };
1595 1608
1596 lpuart0: serial@5a060000 { 1609 lpuart0: serial@5a060000 {
1597 compatible = "fsl,imx8qm-lpuart"; 1610 compatible = "fsl,imx8qm-lpuart";
1598 reg = <0x0 0x5a060000 0x0 0x1000>; 1611 reg = <0x0 0x5a060000 0x0 0x1000>;
1599 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1612 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1600 interrupt-parent = <&gic>; 1613 interrupt-parent = <&gic>;
1601 clocks = <&clk IMX8QXP_UART0_CLK>, 1614 clocks = <&clk IMX8QXP_UART0_CLK>,
1602 <&clk IMX8QXP_UART0_IPG_CLK>; 1615 <&clk IMX8QXP_UART0_IPG_CLK>;
1603 clock-names = "per", "ipg"; 1616 clock-names = "per", "ipg";
1604 assigned-clocks = <&clk IMX8QXP_UART0_CLK>; 1617 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
1605 assigned-clock-rates = <80000000>; 1618 assigned-clock-rates = <80000000>;
1606 power-domains = <&pd_dma_lpuart0>; 1619 power-domains = <&pd_dma_lpuart0>;
1607 status = "disabled"; 1620 status = "disabled";
1608 }; 1621 };
1609 1622
1610 lpuart1: serial@5a070000 { 1623 lpuart1: serial@5a070000 {
1611 compatible = "fsl,imx8qm-lpuart"; 1624 compatible = "fsl,imx8qm-lpuart";
1612 reg = <0x0 0x5a070000 0x0 0x1000>; 1625 reg = <0x0 0x5a070000 0x0 0x1000>;
1613 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1626 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1614 interrupt-parent = <&gic>; 1627 interrupt-parent = <&gic>;
1615 clocks = <&clk IMX8QXP_UART1_CLK>, 1628 clocks = <&clk IMX8QXP_UART1_CLK>,
1616 <&clk IMX8QXP_UART1_IPG_CLK>; 1629 <&clk IMX8QXP_UART1_IPG_CLK>;
1617 clock-names = "per", "ipg"; 1630 clock-names = "per", "ipg";
1618 assigned-clocks = <&clk IMX8QXP_UART1_CLK>; 1631 assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
1619 assigned-clock-rates = <80000000>; 1632 assigned-clock-rates = <80000000>;
1620 power-domains = <&pd_dma_lpuart1>; 1633 power-domains = <&pd_dma_lpuart1>;
1621 dma-names = "tx","rx"; 1634 dma-names = "tx","rx";
1622 dmas = <&edma0 11 0 0>, 1635 dmas = <&edma0 11 0 0>,
1623 <&edma0 10 0 1>; 1636 <&edma0 10 0 1>;
1624 status = "disabled"; 1637 status = "disabled";
1625 }; 1638 };
1626 1639
1627 lpuart2: serial@5a080000 { 1640 lpuart2: serial@5a080000 {
1628 compatible = "fsl,imx8qm-lpuart"; 1641 compatible = "fsl,imx8qm-lpuart";
1629 reg = <0x0 0x5a080000 0x0 0x1000>; 1642 reg = <0x0 0x5a080000 0x0 0x1000>;
1630 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1643 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1631 interrupt-parent = <&gic>; 1644 interrupt-parent = <&gic>;
1632 clocks = <&clk IMX8QXP_UART2_CLK>, 1645 clocks = <&clk IMX8QXP_UART2_CLK>,
1633 <&clk IMX8QXP_UART2_IPG_CLK>; 1646 <&clk IMX8QXP_UART2_IPG_CLK>;
1634 clock-names = "per", "ipg"; 1647 clock-names = "per", "ipg";
1635 assigned-clocks = <&clk IMX8QXP_UART2_CLK>; 1648 assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
1636 assigned-clock-rates = <80000000>; 1649 assigned-clock-rates = <80000000>;
1637 power-domains = <&pd_dma_lpuart2>; 1650 power-domains = <&pd_dma_lpuart2>;
1638 dma-names = "tx","rx"; 1651 dma-names = "tx","rx";
1639 dmas = <&edma0 13 0 0>, 1652 dmas = <&edma0 13 0 0>,
1640 <&edma0 12 0 1>; 1653 <&edma0 12 0 1>;
1641 status = "disabled"; 1654 status = "disabled";
1642 }; 1655 };
1643 1656
1644 lpuart3: serial@5a090000 { 1657 lpuart3: serial@5a090000 {
1645 compatible = "fsl,imx8qm-lpuart"; 1658 compatible = "fsl,imx8qm-lpuart";
1646 reg = <0x0 0x5a090000 0x0 0x1000>; 1659 reg = <0x0 0x5a090000 0x0 0x1000>;
1647 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1660 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1648 interrupt-parent = <&gic>; 1661 interrupt-parent = <&gic>;
1649 clocks = <&clk IMX8QXP_UART3_CLK>, 1662 clocks = <&clk IMX8QXP_UART3_CLK>,
1650 <&clk IMX8QXP_UART3_IPG_CLK>; 1663 <&clk IMX8QXP_UART3_IPG_CLK>;
1651 clock-names = "per", "ipg"; 1664 clock-names = "per", "ipg";
1652 assigned-clocks = <&clk IMX8QXP_UART3_CLK>; 1665 assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
1653 assigned-clock-rates = <80000000>; 1666 assigned-clock-rates = <80000000>;
1654 power-domains = <&pd_dma_lpuart3>; 1667 power-domains = <&pd_dma_lpuart3>;
1655 dma-names = "tx","rx"; 1668 dma-names = "tx","rx";
1656 dmas = <&edma0 15 0 0>, 1669 dmas = <&edma0 15 0 0>,
1657 <&edma0 14 0 1>; 1670 <&edma0 14 0 1>;
1658 status = "disabled"; 1671 status = "disabled";
1659 }; 1672 };
1660 1673
1661 edma0: dma-controller@5a1f0000 { 1674 edma0: dma-controller@5a1f0000 {
1662 compatible = "fsl,imx8qm-edma"; 1675 compatible = "fsl,imx8qm-edma";
1663 reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ 1676 reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
1664 <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ 1677 <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
1665 <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ 1678 <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
1666 <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ 1679 <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
1667 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ 1680 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */
1668 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ 1681 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */
1669 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ 1682 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
1670 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ 1683 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
1671 #dma-cells = <3>; 1684 #dma-cells = <3>;
1672 dma-channels = <8>; 1685 dma-channels = <8>;
1673 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 1686 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1674 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1675 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
1676 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
1677 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
1680 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 1693 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
1681 interrupt-names = "edma-chan8-tx", "edma-chan9-tx", 1694 interrupt-names = "edma-chan8-tx", "edma-chan9-tx",
1682 "edma-chan10-tx", "edma-chan11-tx", 1695 "edma-chan10-tx", "edma-chan11-tx",
1683 "edma-chan12-tx", "edma-chan13-tx", 1696 "edma-chan12-tx", "edma-chan13-tx",
1684 "edma-chan14-tx", "edma-chan15-tx"; 1697 "edma-chan14-tx", "edma-chan15-tx";
1685 status = "okay"; 1698 status = "okay";
1686 }; 1699 };
1687 1700
1688 edma2: dma-controller@591F0000 { 1701 edma2: dma-controller@591F0000 {
1689 compatible = "fsl,imx8qm-edma"; 1702 compatible = "fsl,imx8qm-edma";
1690 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ 1703 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
1691 <0x0 0x59210000 0x0 0x10000>, 1704 <0x0 0x59210000 0x0 0x10000>,
1692 <0x0 0x59220000 0x0 0x10000>, 1705 <0x0 0x59220000 0x0 0x10000>,
1693 <0x0 0x59230000 0x0 0x10000>, 1706 <0x0 0x59230000 0x0 0x10000>,
1694 <0x0 0x59240000 0x0 0x10000>, 1707 <0x0 0x59240000 0x0 0x10000>,
1695 <0x0 0x59250000 0x0 0x10000>, 1708 <0x0 0x59250000 0x0 0x10000>,
1696 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ 1709 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
1697 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ 1710 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
1698 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ 1711 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
1699 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ 1712 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
1700 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ 1713 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
1701 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ 1714 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
1702 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ 1715 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
1703 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ 1716 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
1704 <0x0 0x59350000 0x0 0x10000>, 1717 <0x0 0x59350000 0x0 0x10000>,
1705 <0x0 0x59370000 0x0 0x10000>; 1718 <0x0 0x59370000 0x0 0x10000>;
1706 #dma-cells = <3>; 1719 #dma-cells = <3>;
1707 shared-interrupt; 1720 shared-interrupt;
1708 dma-channels = <16>; 1721 dma-channels = <16>;
1709 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ 1722 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
1710 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
1714 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
1715 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ 1728 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
1716 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1717 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 1730 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
1718 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
1719 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 1732 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
1720 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 1734 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
1722 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1737 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1725 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */ 1738 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc0 */
1726 "edma-chan2-tx", "edma-chan3-tx", 1739 "edma-chan2-tx", "edma-chan3-tx",
1727 "edma-chan4-tx", "edma-chan5-tx", 1740 "edma-chan4-tx", "edma-chan5-tx",
1728 "edma-chan6-tx", "edma-chan7-tx", /* esai0 */ 1741 "edma-chan6-tx", "edma-chan7-tx", /* esai0 */
1729 "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */ 1742 "edma-chan8-tx", "edma-chan9-tx", /* spdif0 */
1730 "edma-chan12-tx", "edma-chan13-tx", /* sai0 */ 1743 "edma-chan12-tx", "edma-chan13-tx", /* sai0 */
1731 "edma-chan14-tx", "edma-chan15-tx", /* sai1 */ 1744 "edma-chan14-tx", "edma-chan15-tx", /* sai1 */
1732 "edma-chan21-tx", /* gpt5 */ 1745 "edma-chan21-tx", /* gpt5 */
1733 "edma-chan23-tx"; /* gpt7 */ 1746 "edma-chan23-tx"; /* gpt7 */
1734 status = "okay"; 1747 status = "okay";
1735 }; 1748 };
1736 1749
1737 edma3: dma-controller@599F0000 { 1750 edma3: dma-controller@599F0000 {
1738 compatible = "fsl,imx8qm-edma"; 1751 compatible = "fsl,imx8qm-edma";
1739 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ 1752 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
1740 <0x0 0x59A10000 0x0 0x10000>, 1753 <0x0 0x59A10000 0x0 0x10000>,
1741 <0x0 0x59A20000 0x0 0x10000>, 1754 <0x0 0x59A20000 0x0 0x10000>,
1742 <0x0 0x59A30000 0x0 0x10000>, 1755 <0x0 0x59A30000 0x0 0x10000>,
1743 <0x0 0x59A40000 0x0 0x10000>, 1756 <0x0 0x59A40000 0x0 0x10000>,
1744 <0x0 0x59A50000 0x0 0x10000>, 1757 <0x0 0x59A50000 0x0 0x10000>,
1745 <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ 1758 <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */
1746 <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ 1759 <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */
1747 <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ 1760 <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */
1748 #dma-cells = <3>; 1761 #dma-cells = <3>;
1749 shared-interrupt; 1762 shared-interrupt;
1750 dma-channels = <9>; 1763 dma-channels = <9>;
1751 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ 1764 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
1752 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
1757 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 1770 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
1758 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 1772 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
1760 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */ 1773 interrupt-names = "edma-chan0-tx", "edma-chan1-tx", /* asrc1 */
1761 "edma-chan2-tx", "edma-chan3-tx", 1774 "edma-chan2-tx", "edma-chan3-tx",
1762 "edma-chan4-tx", "edma-chan5-tx", 1775 "edma-chan4-tx", "edma-chan5-tx",
1763 "edma-chan8-tx", "edma-chan9-tx", /* sai4 */ 1776 "edma-chan8-tx", "edma-chan9-tx", /* sai4 */
1764 "edma-chan10-tx"; /* sai5 */ 1777 "edma-chan10-tx"; /* sai5 */
1765 status = "okay"; 1778 status = "okay";
1766 }; 1779 };
1767 1780
1768 acm: acm@59e00000 { 1781 acm: acm@59e00000 {
1769 compatible = "nxp,imx8qm-acm"; 1782 compatible = "nxp,imx8qm-acm";
1770 reg = <0x0 0x59e00000 0x0 0x1D0000>; 1783 reg = <0x0 0x59e00000 0x0 0x1D0000>;
1771 status = "disabled"; 1784 status = "disabled";
1772 }; 1785 };
1773 1786
1774 sai0: sai@59040000 { 1787 sai0: sai@59040000 {
1775 compatible = "fsl,imx8qm-sai"; 1788 compatible = "fsl,imx8qm-sai";
1776 reg = <0x0 0x59040000 0x0 0x10000>; 1789 reg = <0x0 0x59040000 0x0 0x10000>;
1777 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 1790 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
1778 clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, 1791 clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>,
1779 <&clk IMX8QXP_CLK_DUMMY>, 1792 <&clk IMX8QXP_CLK_DUMMY>,
1780 <&clk IMX8QXP_AUD_SAI_0_MCLK>, 1793 <&clk IMX8QXP_AUD_SAI_0_MCLK>,
1781 <&clk IMX8QXP_CLK_DUMMY>, 1794 <&clk IMX8QXP_CLK_DUMMY>,
1782 <&clk IMX8QXP_CLK_DUMMY>; 1795 <&clk IMX8QXP_CLK_DUMMY>;
1783 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1796 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1784 dma-names = "rx", "tx"; 1797 dma-names = "rx", "tx";
1785 dmas = <&edma2 12 0 1>, <&edma2 13 0 0>; 1798 dmas = <&edma2 12 0 1>, <&edma2 13 0 0>;
1786 status = "disabled"; 1799 status = "disabled";
1787 power-domains = <&pd_sai0>; 1800 power-domains = <&pd_sai0>;
1788 }; 1801 };
1789 1802
1790 sai1: sai@59050000 { 1803 sai1: sai@59050000 {
1791 compatible = "fsl,imx8qm-sai"; 1804 compatible = "fsl,imx8qm-sai";
1792 reg = <0x0 0x59050000 0x0 0x10000>; 1805 reg = <0x0 0x59050000 0x0 0x10000>;
1793 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
1794 clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, 1807 clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>,
1795 <&clk IMX8QXP_CLK_DUMMY>, 1808 <&clk IMX8QXP_CLK_DUMMY>,
1796 <&clk IMX8QXP_AUD_SAI_1_MCLK>, 1809 <&clk IMX8QXP_AUD_SAI_1_MCLK>,
1797 <&clk IMX8QXP_CLK_DUMMY>, 1810 <&clk IMX8QXP_CLK_DUMMY>,
1798 <&clk IMX8QXP_CLK_DUMMY>; 1811 <&clk IMX8QXP_CLK_DUMMY>;
1799 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1812 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1800 dma-names = "rx", "tx"; 1813 dma-names = "rx", "tx";
1801 dmas = <&edma2 14 0 1>, <&edma2 15 0 0>; 1814 dmas = <&edma2 14 0 1>, <&edma2 15 0 0>;
1802 status = "disabled"; 1815 status = "disabled";
1803 power-domains = <&pd_sai1>; 1816 power-domains = <&pd_sai1>;
1804 }; 1817 };
1805 1818
1806 sai4: sai@59820000 { 1819 sai4: sai@59820000 {
1807 compatible = "fsl,imx8qm-sai"; 1820 compatible = "fsl,imx8qm-sai";
1808 reg = <0x0 0x59820000 0x0 0x10000>; 1821 reg = <0x0 0x59820000 0x0 0x10000>;
1809 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1822 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1810 clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, 1823 clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>,
1811 <&clk IMX8QXP_CLK_DUMMY>, 1824 <&clk IMX8QXP_CLK_DUMMY>,
1812 <&clk IMX8QXP_AUD_SAI_4_MCLK>, 1825 <&clk IMX8QXP_AUD_SAI_4_MCLK>,
1813 <&clk IMX8QXP_CLK_DUMMY>, 1826 <&clk IMX8QXP_CLK_DUMMY>,
1814 <&clk IMX8QXP_CLK_DUMMY>; 1827 <&clk IMX8QXP_CLK_DUMMY>;
1815 dmas = <&edma3 8 0 1>, <&edma3 9 0 0>; 1828 dmas = <&edma3 8 0 1>, <&edma3 9 0 0>;
1816 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1829 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1817 dma-names = "rx", "tx"; 1830 dma-names = "rx", "tx";
1818 status = "disabled"; 1831 status = "disabled";
1819 power-domains = <&pd_sai4>; 1832 power-domains = <&pd_sai4>;
1820 }; 1833 };
1821 1834
1822 sai5: sai@59830000 { 1835 sai5: sai@59830000 {
1823 compatible = "fsl,imx8qm-sai"; 1836 compatible = "fsl,imx8qm-sai";
1824 reg = <0x0 0x59830000 0x0 0x10000>; 1837 reg = <0x0 0x59830000 0x0 0x10000>;
1825 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1838 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, 1839 clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>,
1827 <&clk IMX8QXP_CLK_DUMMY>, 1840 <&clk IMX8QXP_CLK_DUMMY>,
1828 <&clk IMX8QXP_AUD_SAI_5_MCLK>, 1841 <&clk IMX8QXP_AUD_SAI_5_MCLK>,
1829 <&clk IMX8QXP_CLK_DUMMY>, 1842 <&clk IMX8QXP_CLK_DUMMY>,
1830 <&clk IMX8QXP_CLK_DUMMY>; 1843 <&clk IMX8QXP_CLK_DUMMY>;
1831 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1844 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1832 dma-names = "tx"; 1845 dma-names = "tx";
1833 dmas = <&edma3 10 0 0>; 1846 dmas = <&edma3 10 0 0>;
1834 status = "disabled"; 1847 status = "disabled";
1835 power-domains = <&pd_sai5>; 1848 power-domains = <&pd_sai5>;
1836 }; 1849 };
1837 1850
1838 amix: amix@59840000 { 1851 amix: amix@59840000 {
1839 compatible = "fsl,imx8qm-amix"; 1852 compatible = "fsl,imx8qm-amix";
1840 reg = <0x0 0x59840000 0x0 0x10000>; 1853 reg = <0x0 0x59840000 0x0 0x10000>;
1841 clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; 1854 clocks = <&clk IMX8QXP_AUD_AMIX_IPG>;
1842 clock-names = "ipg"; 1855 clock-names = "ipg";
1843 power-domains = <&pd_amix>; 1856 power-domains = <&pd_amix>;
1844 status = "disabled"; 1857 status = "disabled";
1845 }; 1858 };
1846 1859
1847 asrc0: asrc@59000000 { 1860 asrc0: asrc@59000000 {
1848 compatible = "fsl,imx8qm-asrc0"; 1861 compatible = "fsl,imx8qm-asrc0";
1849 reg = <0x0 0x59000000 0x0 0x10000>; 1862 reg = <0x0 0x59000000 0x0 0x10000>;
1850 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 1863 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1864 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, 1865 clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
1853 <&clk IMX8QXP_CLK_DUMMY>, 1866 <&clk IMX8QXP_CLK_DUMMY>,
1854 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, 1867 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
1855 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, 1868 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
1856 <&clk IMX8QXP_CLK_DUMMY>, 1869 <&clk IMX8QXP_CLK_DUMMY>,
1857 <&clk IMX8QXP_CLK_DUMMY>, 1870 <&clk IMX8QXP_CLK_DUMMY>,
1858 <&clk IMX8QXP_CLK_DUMMY>, 1871 <&clk IMX8QXP_CLK_DUMMY>,
1859 <&clk IMX8QXP_CLK_DUMMY>, 1872 <&clk IMX8QXP_CLK_DUMMY>,
1860 <&clk IMX8QXP_CLK_DUMMY>, 1873 <&clk IMX8QXP_CLK_DUMMY>,
1861 <&clk IMX8QXP_CLK_DUMMY>, 1874 <&clk IMX8QXP_CLK_DUMMY>,
1862 <&clk IMX8QXP_CLK_DUMMY>, 1875 <&clk IMX8QXP_CLK_DUMMY>,
1863 <&clk IMX8QXP_CLK_DUMMY>, 1876 <&clk IMX8QXP_CLK_DUMMY>,
1864 <&clk IMX8QXP_CLK_DUMMY>, 1877 <&clk IMX8QXP_CLK_DUMMY>,
1865 <&clk IMX8QXP_CLK_DUMMY>, 1878 <&clk IMX8QXP_CLK_DUMMY>,
1866 <&clk IMX8QXP_CLK_DUMMY>, 1879 <&clk IMX8QXP_CLK_DUMMY>,
1867 <&clk IMX8QXP_CLK_DUMMY>, 1880 <&clk IMX8QXP_CLK_DUMMY>,
1868 <&clk IMX8QXP_CLK_DUMMY>, 1881 <&clk IMX8QXP_CLK_DUMMY>,
1869 <&clk IMX8QXP_CLK_DUMMY>, 1882 <&clk IMX8QXP_CLK_DUMMY>,
1870 <&clk IMX8QXP_CLK_DUMMY>; 1883 <&clk IMX8QXP_CLK_DUMMY>;
1871 clock-names = "ipg", "mem", 1884 clock-names = "ipg", "mem",
1872 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 1885 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
1873 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 1886 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
1874 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 1887 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
1875 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 1888 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
1876 "spba"; 1889 "spba";
1877 dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>, 1890 dmas = <&edma2 0 0 0>, <&edma2 1 0 0>, <&edma2 2 0 0>,
1878 <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>; 1891 <&edma2 3 0 1>, <&edma2 4 0 1>, <&edma2 5 0 1>;
1879 dma-names = "rxa", "rxb", "rxc", 1892 dma-names = "rxa", "rxb", "rxc",
1880 "txa", "txb", "txc"; 1893 "txa", "txb", "txc";
1881 fsl,asrc-rate = <8000>; 1894 fsl,asrc-rate = <8000>;
1882 fsl,asrc-width = <16>; 1895 fsl,asrc-width = <16>;
1883 power-domains = <&pd_asrc0>; 1896 power-domains = <&pd_asrc0>;
1884 status = "disabled"; 1897 status = "disabled";
1885 }; 1898 };
1886 1899
1887 asrc1: asrc@59800000 { 1900 asrc1: asrc@59800000 {
1888 compatible = "fsl,imx8qm-asrc1"; 1901 compatible = "fsl,imx8qm-asrc1";
1889 reg = <0x0 0x59800000 0x0 0x10000>; 1902 reg = <0x0 0x59800000 0x0 0x10000>;
1890 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 1903 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1904 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1892 clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, 1905 clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>,
1893 <&clk IMX8QXP_CLK_DUMMY>, 1906 <&clk IMX8QXP_CLK_DUMMY>,
1894 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, 1907 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
1895 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, 1908 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
1896 <&clk IMX8QXP_CLK_DUMMY>, 1909 <&clk IMX8QXP_CLK_DUMMY>,
1897 <&clk IMX8QXP_CLK_DUMMY>, 1910 <&clk IMX8QXP_CLK_DUMMY>,
1898 <&clk IMX8QXP_CLK_DUMMY>, 1911 <&clk IMX8QXP_CLK_DUMMY>,
1899 <&clk IMX8QXP_CLK_DUMMY>, 1912 <&clk IMX8QXP_CLK_DUMMY>,
1900 <&clk IMX8QXP_CLK_DUMMY>, 1913 <&clk IMX8QXP_CLK_DUMMY>,
1901 <&clk IMX8QXP_CLK_DUMMY>, 1914 <&clk IMX8QXP_CLK_DUMMY>,
1902 <&clk IMX8QXP_CLK_DUMMY>, 1915 <&clk IMX8QXP_CLK_DUMMY>,
1903 <&clk IMX8QXP_CLK_DUMMY>, 1916 <&clk IMX8QXP_CLK_DUMMY>,
1904 <&clk IMX8QXP_CLK_DUMMY>, 1917 <&clk IMX8QXP_CLK_DUMMY>,
1905 <&clk IMX8QXP_CLK_DUMMY>, 1918 <&clk IMX8QXP_CLK_DUMMY>,
1906 <&clk IMX8QXP_CLK_DUMMY>, 1919 <&clk IMX8QXP_CLK_DUMMY>,
1907 <&clk IMX8QXP_CLK_DUMMY>, 1920 <&clk IMX8QXP_CLK_DUMMY>,
1908 <&clk IMX8QXP_CLK_DUMMY>, 1921 <&clk IMX8QXP_CLK_DUMMY>,
1909 <&clk IMX8QXP_CLK_DUMMY>, 1922 <&clk IMX8QXP_CLK_DUMMY>,
1910 <&clk IMX8QXP_CLK_DUMMY>; 1923 <&clk IMX8QXP_CLK_DUMMY>;
1911 clock-names = "ipg", "mem", 1924 clock-names = "ipg", "mem",
1912 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 1925 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
1913 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 1926 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
1914 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 1927 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
1915 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 1928 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
1916 "spba"; 1929 "spba";
1917 dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>, 1930 dmas = <&edma3 0 0 0>, <&edma3 1 0 0>, <&edma3 2 0 0>,
1918 <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>; 1931 <&edma3 3 0 1>, <&edma3 4 0 1>, <&edma3 5 0 1>;
1919 dma-names = "rxa", "rxb", "rxc", 1932 dma-names = "rxa", "rxb", "rxc",
1920 "txa", "txb", "txc"; 1933 "txa", "txb", "txc";
1921 fsl,asrc-rate = <8000>; 1934 fsl,asrc-rate = <8000>;
1922 fsl,asrc-width = <16>; 1935 fsl,asrc-width = <16>;
1923 power-domains = <&pd_asrc1>; 1936 power-domains = <&pd_asrc1>;
1924 status = "disabled"; 1937 status = "disabled";
1925 }; 1938 };
1926 1939
1927 mqs: mqs@59850000 { 1940 mqs: mqs@59850000 {
1928 compatible = "fsl,imx8qm-mqs"; 1941 compatible = "fsl,imx8qm-mqs";
1929 reg = <0x0 0x59850000 0x0 0x10000>; 1942 reg = <0x0 0x59850000 0x0 0x10000>;
1930 clocks = <&clk IMX8QXP_AUD_MQS_IPG>, 1943 clocks = <&clk IMX8QXP_AUD_MQS_IPG>,
1931 <&clk IMX8QXP_AUD_MQS_HMCLK>; 1944 <&clk IMX8QXP_AUD_MQS_HMCLK>;
1932 clock-names = "core", "mclk"; 1945 clock-names = "core", "mclk";
1933 power-domains = <&pd_mqs0>; 1946 power-domains = <&pd_mqs0>;
1934 status = "disabled"; 1947 status = "disabled";
1935 }; 1948 };
1936 1949
1937 usdhc1: usdhc@5b010000 { 1950 usdhc1: usdhc@5b010000 {
1938 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1951 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1939 interrupt-parent = <&gic>; 1952 interrupt-parent = <&gic>;
1940 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1953 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1941 reg = <0x0 0x5b010000 0x0 0x10000>; 1954 reg = <0x0 0x5b010000 0x0 0x10000>;
1942 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, 1955 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
1943 <&clk IMX8QXP_SDHC0_CLK>, 1956 <&clk IMX8QXP_SDHC0_CLK>,
1944 <&clk IMX8QXP_CLK_DUMMY>; 1957 <&clk IMX8QXP_CLK_DUMMY>;
1945 clock-names = "ipg", "per", "ahb"; 1958 clock-names = "ipg", "per", "ahb";
1946 assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>; 1959 assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>;
1947 assigned-clock-rates = <400000000>; 1960 assigned-clock-rates = <400000000>;
1948 power-domains = <&pd_conn_sdch0>; 1961 power-domains = <&pd_conn_sdch0>;
1949 fsl,tuning-start-tap = <20>; 1962 fsl,tuning-start-tap = <20>;
1950 fsl,tuning-step= <2>; 1963 fsl,tuning-step= <2>;
1951 status = "disabled"; 1964 status = "disabled";
1952 }; 1965 };
1953 1966
1954 usdhc2: usdhc@5b020000 { 1967 usdhc2: usdhc@5b020000 {
1955 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1968 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1956 interrupt-parent = <&gic>; 1969 interrupt-parent = <&gic>;
1957 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1958 reg = <0x0 0x5b020000 0x0 0x10000>; 1971 reg = <0x0 0x5b020000 0x0 0x10000>;
1959 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, 1972 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
1960 <&clk IMX8QXP_SDHC1_CLK>, 1973 <&clk IMX8QXP_SDHC1_CLK>,
1961 <&clk IMX8QXP_CLK_DUMMY>; 1974 <&clk IMX8QXP_CLK_DUMMY>;
1962 clock-names = "ipg", "per", "ahb"; 1975 clock-names = "ipg", "per", "ahb";
1963 assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>; 1976 assigned-clocks = <&clk IMX8QXP_SDHC1_DIV>;
1964 assigned-clock-rates = <200000000>; 1977 assigned-clock-rates = <200000000>;
1965 power-domains = <&pd_conn_sdch1>; 1978 power-domains = <&pd_conn_sdch1>;
1966 fsl,tuning-start-tap = <20>; 1979 fsl,tuning-start-tap = <20>;
1967 fsl,tuning-step= <2>; 1980 fsl,tuning-step= <2>;
1968 status = "disabled"; 1981 status = "disabled";
1969 }; 1982 };
1970 1983
1971 usdhc3: usdhc@5b030000 { 1984 usdhc3: usdhc@5b030000 {
1972 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1985 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1973 interrupt-parent = <&gic>; 1986 interrupt-parent = <&gic>;
1974 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1987 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1975 reg = <0x0 0x5b030000 0x0 0x10000>; 1988 reg = <0x0 0x5b030000 0x0 0x10000>;
1976 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, 1989 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
1977 <&clk IMX8QXP_SDHC2_CLK>, 1990 <&clk IMX8QXP_SDHC2_CLK>,
1978 <&clk IMX8QXP_CLK_DUMMY>; 1991 <&clk IMX8QXP_CLK_DUMMY>;
1979 clock-names = "ipg", "per", "ahb"; 1992 clock-names = "ipg", "per", "ahb";
1980 assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>; 1993 assigned-clocks = <&clk IMX8QXP_SDHC2_DIV>;
1981 assigned-clock-rates = <200000000>; 1994 assigned-clock-rates = <200000000>;
1982 power-domains = <&pd_conn_sdch2>; 1995 power-domains = <&pd_conn_sdch2>;
1983 fsl,tuning-start-tap = <20>; 1996 fsl,tuning-start-tap = <20>;
1984 fsl,tuning-step = <2>; 1997 fsl,tuning-step = <2>;
1985 status = "disabled"; 1998 status = "disabled";
1986 }; 1999 };
1987 2000
1988 fec1: ethernet@5b040000 { 2001 fec1: ethernet@5b040000 {
1989 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; 2002 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
1990 reg = <0x0 0x5b040000 0x0 0x10000>; 2003 reg = <0x0 0x5b040000 0x0 0x10000>;
1991 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2004 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1992 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 2007 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, 2008 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
1996 <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; 2009 <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
1997 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 2010 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
1998 assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, 2011 assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
1999 <&clk IMX8QXP_ENET0_REF_DIV>, 2012 <&clk IMX8QXP_ENET0_REF_DIV>,
2000 <&clk IMX8QXP_ENET0_PTP_CLK>; 2013 <&clk IMX8QXP_ENET0_PTP_CLK>;
2001 assigned-clock-rates = <250000000>, <125000000>, <125000000>; 2014 assigned-clock-rates = <250000000>, <125000000>, <125000000>;
2002 fsl,num-tx-queues=<3>; 2015 fsl,num-tx-queues=<3>;
2003 fsl,num-rx-queues=<3>; 2016 fsl,num-rx-queues=<3>;
2004 power-domains = <&pd_conn_enet0>; 2017 power-domains = <&pd_conn_enet0>;
2005 status = "disabled"; 2018 status = "disabled";
2006 }; 2019 };
2007 2020
2008 fec2: ethernet@5b050000 { 2021 fec2: ethernet@5b050000 {
2009 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; 2022 compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
2010 reg = <0x0 0x5b050000 0x0 0x10000>; 2023 reg = <0x0 0x5b050000 0x0 0x10000>;
2011 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2024 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2014 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2027 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2015 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, 2028 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>,
2016 <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; 2029 <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>;
2017 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 2030 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
2018 assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, 2031 assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>,
2019 <&clk IMX8QXP_ENET1_REF_DIV>, 2032 <&clk IMX8QXP_ENET1_REF_DIV>,
2020 <&clk IMX8QXP_ENET1_PTP_CLK>; 2033 <&clk IMX8QXP_ENET1_PTP_CLK>;
2021 assigned-clock-rates = <250000000>, <125000000>, <125000000>; 2034 assigned-clock-rates = <250000000>, <125000000>, <125000000>;
2022 fsl,num-tx-queues=<3>; 2035 fsl,num-tx-queues=<3>;
2023 fsl,num-rx-queues=<3>; 2036 fsl,num-rx-queues=<3>;
2024 power-domains = <&pd_conn_enet1>; 2037 power-domains = <&pd_conn_enet1>;
2025 status = "disabled"; 2038 status = "disabled";
2026 }; 2039 };
2027 2040
2028 mlb: mlb@5B060000 { 2041 mlb: mlb@5B060000 {
2029 compatible = "fsl,imx6q-mlb150"; 2042 compatible = "fsl,imx6q-mlb150";
2030 reg = <0x0 0x5B060000 0x0 0x10000>; 2043 reg = <0x0 0x5B060000 0x0 0x10000>;
2031 interrupt-parent = <&gic>; 2044 interrupt-parent = <&gic>;
2032 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, 2045 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
2033 <0 266 IRQ_TYPE_LEVEL_HIGH>; 2046 <0 266 IRQ_TYPE_LEVEL_HIGH>;
2034 clocks = <&clk IMX8QXP_MLB_CLK>, 2047 clocks = <&clk IMX8QXP_MLB_CLK>,
2035 <&clk IMX8QXP_MLB_HCLK>, 2048 <&clk IMX8QXP_MLB_HCLK>,
2036 <&clk IMX8QXP_MLB_IPG_CLK>; 2049 <&clk IMX8QXP_MLB_IPG_CLK>;
2037 clock-names = "mlb", "hclk", "ipg"; 2050 clock-names = "mlb", "hclk", "ipg";
2038 assigned-clocks = <&clk IMX8QXP_MLB_CLK>, 2051 assigned-clocks = <&clk IMX8QXP_MLB_CLK>,
2039 <&clk IMX8QXP_MLB_HCLK>, 2052 <&clk IMX8QXP_MLB_HCLK>,
2040 <&clk IMX8QXP_MLB_IPG_CLK>; 2053 <&clk IMX8QXP_MLB_IPG_CLK>;
2041 assigned-clock-rates = <333333333>, <333333333>, <83333333>; 2054 assigned-clock-rates = <333333333>, <333333333>, <83333333>;
2042 power-domains = <&pd_conn_mlb0>; 2055 power-domains = <&pd_conn_mlb0>;
2043 status = "disabled"; 2056 status = "disabled";
2044 }; 2057 };
2045 2058
2046 hifi4: hifi4@586e8000 { 2059 hifi4: hifi4@586e8000 {
2047 compatible = "fsl,imx8qxp-hifi4"; 2060 compatible = "fsl,imx8qxp-hifi4";
2048 reg = <0x0 0x596e8000 0x0 0x88000>; 2061 reg = <0x0 0x596e8000 0x0 0x88000>;
2049 clocks = <&clk IMX8QXP_AUD_HIFI_IPG>, 2062 clocks = <&clk IMX8QXP_AUD_HIFI_IPG>,
2050 <&clk IMX8QXP_AUD_OCRAM_IPG>, 2063 <&clk IMX8QXP_AUD_OCRAM_IPG>,
2051 <&clk IMX8QXP_AUD_HIFI_CORE_CLK>; 2064 <&clk IMX8QXP_AUD_HIFI_CORE_CLK>;
2052 clock-names = "ipg", "ocram", "core"; 2065 clock-names = "ipg", "ocram", "core";
2053 fsl,hifi4-firmware = "imx/hifi/hifi4.bin"; 2066 fsl,hifi4-firmware = "imx/hifi/hifi4.bin";
2054 power-domains = <&pd_hifi>; 2067 power-domains = <&pd_hifi>;
2055 }; 2068 };
2056 2069
2057 esai0: esai@59010000 { 2070 esai0: esai@59010000 {
2058 compatible = "fsl,imx6ull-esai"; 2071 compatible = "fsl,imx6ull-esai";
2059 reg = <0x0 0x59010000 0x0 0x10000>; 2072 reg = <0x0 0x59010000 0x0 0x10000>;
2060 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 2073 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
2061 clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, 2074 clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
2062 <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, 2075 <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
2063 <&clk IMX8QXP_AUD_ESAI_0_IPG>; 2076 <&clk IMX8QXP_AUD_ESAI_0_IPG>;
2064 clock-names = "core", "extal", "fsys"; 2077 clock-names = "core", "extal", "fsys";
2065 dmas = <&edma2 6 0 1>, <&edma2 7 0 0>; 2078 dmas = <&edma2 6 0 1>, <&edma2 7 0 0>;
2066 dma-names = "rx", "tx"; 2079 dma-names = "rx", "tx";
2067 power-domains = <&pd_esai0>; 2080 power-domains = <&pd_esai0>;
2068 status = "disabled"; 2081 status = "disabled";
2069 }; 2082 };
2070 2083
2071 spdif0: spdif@59020000 { 2084 spdif0: spdif@59020000 {
2072 compatible = "fsl,imx8qm-spdif"; 2085 compatible = "fsl,imx8qm-spdif";
2073 reg = <0x0 0x59020000 0x0 0x10000>; 2086 reg = <0x0 0x59020000 0x0 0x10000>;
2074 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 2087 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
2075 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 2088 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
2076 clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ 2089 clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */
2077 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ 2090 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */
2078 <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ 2091 <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
2079 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ 2092 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */
2080 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ 2093 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */
2081 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ 2094 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */
2082 <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ 2095 <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */
2083 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ 2096 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */
2084 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ 2097 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */
2085 <&clk IMX8QXP_CLK_DUMMY>; /* spba */ 2098 <&clk IMX8QXP_CLK_DUMMY>; /* spba */
2086 clock-names = "core", "rxtx0", 2099 clock-names = "core", "rxtx0",
2087 "rxtx1", "rxtx2", 2100 "rxtx1", "rxtx2",
2088 "rxtx3", "rxtx4", 2101 "rxtx3", "rxtx4",
2089 "rxtx5", "rxtx6", 2102 "rxtx5", "rxtx6",
2090 "rxtx7", "spba"; 2103 "rxtx7", "spba";
2091 dmas = <&edma2 8 0 5>, <&edma2 9 0 4>; 2104 dmas = <&edma2 8 0 5>, <&edma2 9 0 4>;
2092 dma-names = "rx", "tx"; 2105 dma-names = "rx", "tx";
2093 power-domains = <&pd_spdif0>; 2106 power-domains = <&pd_spdif0>;
2094 status = "disabled"; 2107 status = "disabled";
2095 }; 2108 };
2096 2109
2097 flexspi0: flexspi@05d120000 { 2110 flexspi0: flexspi@05d120000 {
2098 #address-cells = <1>; 2111 #address-cells = <1>;
2099 #size-cells = <0>; 2112 #size-cells = <0>;
2100 compatible = "fsl,imx8qm-flexspi"; 2113 compatible = "fsl,imx8qm-flexspi";
2101 reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>; 2114 reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x19ffffff>;
2102 reg-names = "FlexSPI", "FlexSPI-memory"; 2115 reg-names = "FlexSPI", "FlexSPI-memory";
2103 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2116 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2104 clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, 2117 clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>,
2105 <&clk IMX8QXP_LSIO_FSPI0_CLK>; 2118 <&clk IMX8QXP_LSIO_FSPI0_CLK>;
2106 assigned-clock-rates = <29000000>,<29000000>; 2119 assigned-clock-rates = <29000000>,<29000000>;
2107 clock-names = "qspi_en", "qspi"; 2120 clock-names = "qspi_en", "qspi";
2108 power-domains = <&pd_lsio_flexspi0>; 2121 power-domains = <&pd_lsio_flexspi0>;
2109 status = "disabled"; 2122 status = "disabled";
2110 }; 2123 };
2111 2124
2112 display-subsystem { 2125 display-subsystem {
2113 compatible = "fsl,imx-display-subsystem"; 2126 compatible = "fsl,imx-display-subsystem";
2114 ports = <&dpu_disp0>, <&dpu_disp1>; 2127 ports = <&dpu_disp0>, <&dpu_disp1>;
2115 }; 2128 };
2116 2129
2117 dma_cap: dma_cap { 2130 dma_cap: dma_cap {
2118 compatible = "dma-capability"; 2131 compatible = "dma-capability";
2119 only-dma-mask32 = <1>; 2132 only-dma-mask32 = <1>;
2120 }; 2133 };
2121 2134
2122 hsio: hsio@5f080000 { 2135 hsio: hsio@5f080000 {
2123 compatible = "fsl,imx8qm-hsio", "syscon"; 2136 compatible = "fsl,imx8qm-hsio", "syscon";
2124 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ 2137 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
2125 }; 2138 };
2126 2139
2127 pcieb: pcie@0x5f010000 { 2140 pcieb: pcie@0x5f010000 {
2128 /* 2141 /*
2129 * pcieb phyx1 lane1 in default, adjust it refer to the 2142 * pcieb phyx1 lane1 in default, adjust it refer to the
2130 * exact hw design. 2143 * exact hw design.
2131 */ 2144 */
2132 compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; 2145 compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
2133 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ 2146 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/
2134 <0x0 0x7ff00000 0x0 0x10000>; /* PCI cfg space */ 2147 <0x0 0x7ff00000 0x0 0x10000>; /* PCI cfg space */
2135 reg-names = "dbi", "config"; 2148 reg-names = "dbi", "config";
2136 #address-cells = <3>; 2149 #address-cells = <3>;
2137 #size-cells = <2>; 2150 #size-cells = <2>;
2138 device_type = "pci"; 2151 device_type = "pci";
2139 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 2152 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
2140 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ 2153 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
2141 num-lanes = <1>; 2154 num-lanes = <1>;
2142 2155
2143 #interrupt-cells = <1>; 2156 #interrupt-cells = <1>;
2144 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2157 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2145 interrupt-names = "msi"; 2158 interrupt-names = "msi";
2146 2159
2147 /* 2160 /*
2148 * Set these clocks in default, then clocks should be 2161 * Set these clocks in default, then clocks should be
2149 * refined for exact hw design of imx8 pcie. 2162 * refined for exact hw design of imx8 pcie.
2150 */ 2163 */
2151 clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, 2164 clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>,
2152 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, 2165 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
2153 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, 2166 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
2154 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; 2167 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>;
2155 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 2168 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
2156 2169
2157 interrupt-map-mask = <0 0 0 0x7>; 2170 interrupt-map-mask = <0 0 0 0x7>;
2158 interrupt-map = <0 0 0 1 &gic 0 105 4>, 2171 interrupt-map = <0 0 0 1 &gic 0 105 4>,
2159 <0 0 0 2 &gic 0 106 4>, 2172 <0 0 0 2 &gic 0 106 4>,
2160 <0 0 0 3 &gic 0 107 4>, 2173 <0 0 0 3 &gic 0 107 4>,
2161 <0 0 0 4 &gic 0 108 4>; 2174 <0 0 0 4 &gic 0 108 4>;
2162 power-domains = <&pd_pcie>; 2175 power-domains = <&pd_pcie>;
2163 fsl,max-link-speed = <3>; 2176 fsl,max-link-speed = <3>;
2164 hsio-cfg = <PCIEAX2PCIEBX1>; 2177 hsio-cfg = <PCIEAX2PCIEBX1>;
2165 hsio = <&hsio>; 2178 hsio = <&hsio>;
2166 ctrl-id = <1>; /* pcieb */ 2179 ctrl-id = <1>; /* pcieb */
2167 cpu-base-addr = <0x80000000>; 2180 cpu-base-addr = <0x80000000>;
2168 status = "disabled"; 2181 status = "disabled";
2169 }; 2182 };
2170 2183
2171 imx_ion { 2184 imx_ion {
2172 compatible = "fsl,mxc-ion"; 2185 compatible = "fsl,mxc-ion";
2173 fsl,heap-id = <0>; 2186 fsl,heap-id = <0>;
2174 }; 2187 };
2175 }; 2188 };
2176 2189
2177 &A35_0 { 2190 &A35_0 {
2178 operating-points = < 2191 operating-points = <
2179 /* kHz uV */ 2192 /* kHz uV */
2180 1200000 1150000 2193 1200000 1150000
2181 >; 2194 >;
2182 clocks = <&clk IMX8QXP_A35_DIV>; 2195 clocks = <&clk IMX8QXP_A35_DIV>;
2183 }; 2196 };
2184 2197
include/dt-bindings/soc/imx8_pd.h
Diff comments   View file @ 70fa29c
1 /* 1 /*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #ifndef __DT_BINDINGS_IMX8_PD_H 16 #ifndef __DT_BINDINGS_IMX8_PD_H
17 #define __DT_BINDINGS_IMX8_PD_H 17 #define __DT_BINDINGS_IMX8_PD_H
18 18
19 /*! 19 /*!
20 * These defines are used to indicate a resource. Resources include peripherals 20 * These defines are used to indicate a resource. Resources include peripherals
21 * and bus masters (but not memory regions). Note items from list should 21 * and bus masters (but not memory regions). Note items from list should
22 * never be changed or removed (only added to at the end of the list). 22 * never be changed or removed (only added to at the end of the list).
23 */ 23 */
24 #define PD_DC_0 dc0_power_domain 24 #define PD_DC_0 dc0_power_domain
25 #define PD_DC_0_PLL_0 dc0_pll0 25 #define PD_DC_0_PLL_0 dc0_pll0
26 #define PD_DC_0_PLL_1 dc0_pll1 26 #define PD_DC_0_PLL_1 dc0_pll1
27 #define PD_LVDS0 lvds0_power_domain 27 #define PD_LVDS0 lvds0_power_domain
28 #define PD_LVDS0_I2C0 lvds0_i2c0 28 #define PD_LVDS0_I2C0 lvds0_i2c0
29 #define PD_LVDS0_I2C1 lvds0_i2c1 29 #define PD_LVDS0_I2C1 lvds0_i2c1
30 #define PD_LVDS0_PWM lvds0_pwm 30 #define PD_LVDS0_PWM lvds0_pwm
31 #define PD_LVDS0_PWM lvds0_pwm 31 #define PD_LVDS0_PWM lvds0_pwm
32 #define PD_LVDS0_GPIO lvds0_gpio 32 #define PD_LVDS0_GPIO lvds0_gpio
33 #define PD_DC_1 dc1_power_domain 33 #define PD_DC_1 dc1_power_domain
34 #define PD_DC_1_PLL_0 dc1_pll0 34 #define PD_DC_1_PLL_0 dc1_pll0
35 #define PD_DC_1_PLL_1 dc1_pll1 35 #define PD_DC_1_PLL_1 dc1_pll1
36 #define PD_LVDS1 lvds1_power_domain 36 #define PD_LVDS1 lvds1_power_domain
37 #define PD_LVDS1_I2C0 lvds1_i2c0 37 #define PD_LVDS1_I2C0 lvds1_i2c0
38 #define PD_LVDS1_I2C1 lvds1_i2c1 38 #define PD_LVDS1_I2C1 lvds1_i2c1
39 #define PD_LVDS1_PWM lvds1_pwm 39 #define PD_LVDS1_PWM lvds1_pwm
40 #define PD_LVDS1_GPIO lvds1_gpio 40 #define PD_LVDS1_GPIO lvds1_gpio
41 41
42 #define PD_DMA dma_power_domain 42 #define PD_DMA dma_power_domain
43 #define PD_DMA_SPI_0 dma_spi0 43 #define PD_DMA_SPI_0 dma_spi0
44 #define PD_DMA_SPI_1 dma_spi1 44 #define PD_DMA_SPI_1 dma_spi1
45 #define PD_DMA_SPI_2 dma_spi2 45 #define PD_DMA_SPI_2 dma_spi2
46 #define PD_DMA_SPI_3 dma_spi3 46 #define PD_DMA_SPI_3 dma_spi3
47 #define PD_DMA_UART0 dma_lpuart0 47 #define PD_DMA_UART0 dma_lpuart0
48 #define PD_DMA_UART1 dma_lpuart1 48 #define PD_DMA_UART1 dma_lpuart1
49 #define PD_DMA_UART2 dma_lpuart2 49 #define PD_DMA_UART2 dma_lpuart2
50 #define PD_DMA_UART3 dma_lpuart3 50 #define PD_DMA_UART3 dma_lpuart3
51 #define PD_DMA_UART4 dma_lpuart4 51 #define PD_DMA_UART4 dma_lpuart4
52 #define PD_DMA_EMVSIM_0 dma_emvsim0 52 #define PD_DMA_EMVSIM_0 dma_emvsim0
53 #define PD_DMA_EMVSIM_1 dma_emvsim1 53 #define PD_DMA_EMVSIM_1 dma_emvsim1
54 #define PD_DMA_I2C_0 dma_lpi2c0 54 #define PD_DMA_I2C_0 dma_lpi2c0
55 #define PD_DMA_I2C_1 dma_lpi2c1 55 #define PD_DMA_I2C_1 dma_lpi2c1
56 #define PD_DMA_I2C_2 dma_lpi2c2 56 #define PD_DMA_I2C_2 dma_lpi2c2
57 #define PD_DMA_I2C_3 dma_lpi2c3 57 #define PD_DMA_I2C_3 dma_lpi2c3
58 #define PD_DMA_I2C_4 dma_lpi2c4 58 #define PD_DMA_I2C_4 dma_lpi2c4
59 #define PD_DMA_ADC_0 dma_adc0 59 #define PD_DMA_ADC_0 dma_adc0
60 #define PD_DMA_ADC_1 dma_adc1 60 #define PD_DMA_ADC_1 dma_adc1
61 #define PD_DMA_FTM_0 dma_ftm0 61 #define PD_DMA_FTM_0 dma_ftm0
62 #define PD_DMA_FTM_1 dma_ftm1 62 #define PD_DMA_FTM_1 dma_ftm1
63 #define PD_DMA_CAN_0 dma_flexcan0 63 #define PD_DMA_CAN_0 dma_flexcan0
64 #define PD_DMA_CAN_1 dma_flexcan1 64 #define PD_DMA_CAN_1 dma_flexcan1
65 #define PD_DMA_CAN_2 dma_flexcan2 65 #define PD_DMA_CAN_2 dma_flexcan2
66 #define PD_DMA_PWM_0 dma_pwm0 66 #define PD_DMA_PWM_0 dma_pwm0
67 #define PD_DMA_LCD_0 dma_lcd0 67 #define PD_DMA_LCD_0 dma_lcd0
68 68
69 #define PD_HSIO hsio_power_domain 69 #define PD_HSIO hsio_power_domain
70 #define PD_HSIO_PCIE_A hsio_pcie0 70 #define PD_HSIO_PCIE_A hsio_pcie0
71 #define PD_HSIO_PCIE_B hsio_pcie1 71 #define PD_HSIO_PCIE_B hsio_pcie1
72 #define PD_HSIO_SATA_0 hsio_sata0 72 #define PD_HSIO_SATA_0 hsio_sata0
73 #define PD_HSIO_GPIO hsio_gpio 73 #define PD_HSIO_GPIO hsio_gpio
74 74
75 #define PD_LCD_0 lcd0_power_domain 75 #define PD_LCD_0 lcd0_power_domain
76 #define PD_LCD_0_I2C_0 lcd0_i2c0 76 #define PD_LCD_0_I2C_0 lcd0_i2c0
77 #define PD_LCD_0_I2C_1 lcd0_i2c1 77 #define PD_LCD_0_I2C_1 lcd0_i2c1
78 #define PD_LCD_PWM_0 lcd0_pwm0 78 #define PD_LCD_PWM_0 lcd0_pwm0
79 79
80 #define PD_LSIO lsio_power_domain 80 #define PD_LSIO lsio_power_domain
81 #define PD_LSIO_GPIO_0 lsio_gpio0 81 #define PD_LSIO_GPIO_0 lsio_gpio0
82 #define PD_LSIO_GPIO_1 lsio_gpio1 82 #define PD_LSIO_GPIO_1 lsio_gpio1
83 #define PD_LSIO_GPIO_2 lsio_gpio2 83 #define PD_LSIO_GPIO_2 lsio_gpio2
84 #define PD_LSIO_GPIO_3 lsio_gpio3 84 #define PD_LSIO_GPIO_3 lsio_gpio3
85 #define PD_LSIO_GPIO_4 lsio_gpio4 85 #define PD_LSIO_GPIO_4 lsio_gpio4
86 #define PD_LSIO_GPIO_5 lsio_gpio5 86 #define PD_LSIO_GPIO_5 lsio_gpio5
87 #define PD_LSIO_GPIO_6 lsio_gpio6 87 #define PD_LSIO_GPIO_6 lsio_gpio6
88 #define PD_LSIO_GPIO_7 lsio_gpio7 88 #define PD_LSIO_GPIO_7 lsio_gpio7
89 #define PD_LSIO_GPT_0 lsio_gpt0 89 #define PD_LSIO_GPT_0 lsio_gpt0
90 #define PD_LSIO_GPT_1 lsio_gpt1 90 #define PD_LSIO_GPT_1 lsio_gpt1
91 #define PD_LSIO_GPT_2 lsio_gpt2 91 #define PD_LSIO_GPT_2 lsio_gpt2
92 #define PD_LSIO_GPT_3 lsio_gpt3 92 #define PD_LSIO_GPT_3 lsio_gpt3
93 #define PD_LSIO_GPT_4 lsio_gpt4 93 #define PD_LSIO_GPT_4 lsio_gpt4
94 #define PD_LSIO_KPP lsio_kpp 94 #define PD_LSIO_KPP lsio_kpp
95 #define PD_LSIO_FSPI_0 lsio_fspi0 95 #define PD_LSIO_FSPI_0 lsio_fspi0
96 #define PD_LSIO_FSPI_1 lsio_fspi1 96 #define PD_LSIO_FSPI_1 lsio_fspi1
97 #define PD_LSIO_PWM_0 lsio_pwm0 97 #define PD_LSIO_PWM_0 lsio_pwm0
98 #define PD_LSIO_PWM_1 lsio_pwm1 98 #define PD_LSIO_PWM_1 lsio_pwm1
99 #define PD_LSIO_PWM_2 lsio_pwm2 99 #define PD_LSIO_PWM_2 lsio_pwm2
100 #define PD_LSIO_PWM_3 lsio_pwm3 100 #define PD_LSIO_PWM_3 lsio_pwm3
101 #define PD_LSIO_PWM_4 lsio_pwm4 101 #define PD_LSIO_PWM_4 lsio_pwm4
102 #define PD_LSIO_PWM_5 lsio_pwm5 102 #define PD_LSIO_PWM_5 lsio_pwm5
103 #define PD_LSIO_PWM_6 lsio_pwm6 103 #define PD_LSIO_PWM_6 lsio_pwm6
104 #define PD_LSIO_PWM_7 lsio_pwm7 104 #define PD_LSIO_PWM_7 lsio_pwm7
105 #define PD_LSIO_MU8A lsio_mu8a
106 #define PD_LSIO_MU9A lsio_mu9a
105 107
106 #define PD_CONN connectivity_power_domain 108 #define PD_CONN connectivity_power_domain
107 #define PD_CONN_SDHC_0 conn_sdhc0 109 #define PD_CONN_SDHC_0 conn_sdhc0
108 #define PD_CONN_SDHC_1 conn_sdhc1 110 #define PD_CONN_SDHC_1 conn_sdhc1
109 #define PD_CONN_SDHC_2 conn_sdhc2 111 #define PD_CONN_SDHC_2 conn_sdhc2
110 #define PD_CONN_ENET_0 conn_enet0 112 #define PD_CONN_ENET_0 conn_enet0
111 #define PD_CONN_ENET_1 conn_enet1 113 #define PD_CONN_ENET_1 conn_enet1
112 #define PD_CONN_MLB_0 conn_mlb0 114 #define PD_CONN_MLB_0 conn_mlb0
113 #define PD_CONN_DMA_4_CH0 conn_dma4_ch0 115 #define PD_CONN_DMA_4_CH0 conn_dma4_ch0
114 #define PD_CONN_DMA_4_CH1 conn_dma4_ch1 116 #define PD_CONN_DMA_4_CH1 conn_dma4_ch1
115 #define PD_CONN_DMA_4_CH2 conn_dma4_ch2 117 #define PD_CONN_DMA_4_CH2 conn_dma4_ch2
116 #define PD_CONN_DMA_4_CH3 conn_dma4_ch3 118 #define PD_CONN_DMA_4_CH3 conn_dma4_ch3
117 #define PD_CONN_DMA_4_CH4 conn_dma4_ch4 119 #define PD_CONN_DMA_4_CH4 conn_dma4_ch4
118 #define PD_CONN_USB_0 conn_usb0 120 #define PD_CONN_USB_0 conn_usb0
119 #define PD_CONN_USB_1 conn_usb1 121 #define PD_CONN_USB_1 conn_usb1
120 #define PD_CONN_USB_0_PHY conn_usb0_phy 122 #define PD_CONN_USB_0_PHY conn_usb0_phy
121 #define PD_CONN_USB_2 conn_usb2 123 #define PD_CONN_USB_2 conn_usb2
122 #define PD_CONN_USB_2_PHY conn_usb2_phy 124 #define PD_CONN_USB_2_PHY conn_usb2_phy
123 #define PD_CONN_NAND conn_nand 125 #define PD_CONN_NAND conn_nand
124 126
125 #define PD_AUDIO audio_power_domain 127 #define PD_AUDIO audio_power_domain
126 #define PD_AUD_SAI_0 audio_sai0 128 #define PD_AUD_SAI_0 audio_sai0
127 #define PD_AUD_SAI_1 audio_sai1 129 #define PD_AUD_SAI_1 audio_sai1
128 #define PD_AUD_SAI_2 audio_sai2 130 #define PD_AUD_SAI_2 audio_sai2
129 #define PD_AUD_ASRC_0 audio_asrc0 131 #define PD_AUD_ASRC_0 audio_asrc0
130 #define PD_AUD_ASRC_1 audio_asrc1 132 #define PD_AUD_ASRC_1 audio_asrc1
131 #define PD_AUD_ESAI_0 audio_esai0 133 #define PD_AUD_ESAI_0 audio_esai0
132 #define PD_AUD_ESAI_1 audio_esai1 134 #define PD_AUD_ESAI_1 audio_esai1
133 #define PD_AUD_SPDIF_0 audio_spdif0 135 #define PD_AUD_SPDIF_0 audio_spdif0
134 #define PD_AUD_SPDIF_1 audio_spdif1 136 #define PD_AUD_SPDIF_1 audio_spdif1
135 #define PD_AUD_SAI_3 audio_sai3 137 #define PD_AUD_SAI_3 audio_sai3
136 #define PD_AUD_SAI_4 audio_sai4 138 #define PD_AUD_SAI_4 audio_sai4
137 #define PD_AUD_SAI_5 audio_sai5 139 #define PD_AUD_SAI_5 audio_sai5
138 #define PD_AUD_SAI_6 audio_sai6 140 #define PD_AUD_SAI_6 audio_sai6
139 #define PD_AUD_SAI_7 audio_sai7 141 #define PD_AUD_SAI_7 audio_sai7
140 #define PD_AUD_GPT_5 audio_gpt5 142 #define PD_AUD_GPT_5 audio_gpt5
141 #define PD_AUD_GPT_6 audio_gpt6 143 #define PD_AUD_GPT_6 audio_gpt6
142 #define PD_AUD_GPT_7 audio_gpt7 144 #define PD_AUD_GPT_7 audio_gpt7
143 #define PD_AUD_GPT_8 audio_gpt8 145 #define PD_AUD_GPT_8 audio_gpt8
144 #define PD_AUD_GPT_9 audio_gpt9 146 #define PD_AUD_GPT_9 audio_gpt9
145 #define PD_AUD_GPT_10 audio_gpt10 147 #define PD_AUD_GPT_10 audio_gpt10
146 #define PD_AUD_AMIX audio_amix 148 #define PD_AUD_AMIX audio_amix
147 #define PD_AUD_MQS_0 audio_mqs0 149 #define PD_AUD_MQS_0 audio_mqs0
148 #define PD_AUD_HIFI audio_hifi 150 #define PD_AUD_HIFI audio_hifi
149 #define PD_AUD_OCRAM audio_ocram 151 #define PD_AUD_OCRAM audio_ocram
150 #define PD_AUD_MCLK_OUT_0 audio_mclkout0 152 #define PD_AUD_MCLK_OUT_0 audio_mclkout0
151 #define PD_AUD_MCLK_OUT_1 audio_mclkout1 153 #define PD_AUD_MCLK_OUT_1 audio_mclkout1
152 #define PD_AUD_AUDIO_PLL_0 audio_audiopll0 154 #define PD_AUD_AUDIO_PLL_0 audio_audiopll0
153 #define PD_AUD_AUDIO_PLL_1 audio_audiopll1 155 #define PD_AUD_AUDIO_PLL_1 audio_audiopll1
154 #define PD_AUD_AUDIO_CLK_0 audio_audioclk0 156 #define PD_AUD_AUDIO_CLK_0 audio_audioclk0
155 #define PD_AUD_AUDIO_CLK_1 audio_audioclk1 157 #define PD_AUD_AUDIO_CLK_1 audio_audioclk1
156 158
157 #define PD_IMAGING imaging_power_domain 159 #define PD_IMAGING imaging_power_domain
158 #define PD_IMAGING_JPEG_DEC imaging_jpeg_dec 160 #define PD_IMAGING_JPEG_DEC imaging_jpeg_dec
159 #define PD_IMAGING_JPEG_ENC imaging_jpeg_enc 161 #define PD_IMAGING_JPEG_ENC imaging_jpeg_enc
160 #define PD_IMAGING_PDMA0 PD_IMAGING 162 #define PD_IMAGING_PDMA0 PD_IMAGING
161 #define PD_IMAGING_PDMA1 imaging_pdma1 163 #define PD_IMAGING_PDMA1 imaging_pdma1
162 #define PD_IMAGING_PDMA2 imaging_pdma2 164 #define PD_IMAGING_PDMA2 imaging_pdma2
163 #define PD_IMAGING_PDMA3 imaging_pdma3 165 #define PD_IMAGING_PDMA3 imaging_pdma3
164 #define PD_IMAGING_PDMA4 imaging_pdma4 166 #define PD_IMAGING_PDMA4 imaging_pdma4
165 #define PD_IMAGING_PDMA5 imaging_pdma5 167 #define PD_IMAGING_PDMA5 imaging_pdma5
166 #define PD_IMAGING_PDMA6 imaging_pdma6 168 #define PD_IMAGING_PDMA6 imaging_pdma6
167 #define PD_IMAGING_PDMA7 imaging_pdma7 169 #define PD_IMAGING_PDMA7 imaging_pdma7
168 170
169 #define PD_MIPI_0_DSI mipi0_dsi_power_domain 171 #define PD_MIPI_0_DSI mipi0_dsi_power_domain
170 #define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0 172 #define PD_MIPI_0_DSI_I2C0 mipi0_dsi_i2c0
171 #define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1 173 #define PD_MIPI_0_DSI_I2C1 mipi0_dsi_i2c1
172 #define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0 174 #define PD_MIPI_0_DSI_PWM0 mipi0_dsi_pwm0
173 #define PD_MIPI_1_DSI mipi1_dsi_power_domain 175 #define PD_MIPI_1_DSI mipi1_dsi_power_domain
174 #define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0 176 #define PD_MIPI_1_DSI_I2C0 mipi1_dsi_i2c0
175 #define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1 177 #define PD_MIPI_1_DSI_I2C1 mipi1_dsi_i2c1
176 #define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0 178 #define PD_MIPI_1_DSI_PWM0 mipi1_dsi_pwm0
177 179
178 #define PD_MIPI_CSI0 mipi_csi0_power_domain 180 #define PD_MIPI_CSI0 mipi_csi0_power_domain
179 #define PD_MIPI_CSI0_PWM mipi_csi0_pwm 181 #define PD_MIPI_CSI0_PWM mipi_csi0_pwm
180 #define PD_MIPI_CSI0_I2C mipi_csi0_i2c 182 #define PD_MIPI_CSI0_I2C mipi_csi0_i2c
181 #define PD_MIPI_CSI1 mipi_csi1_power_domain 183 #define PD_MIPI_CSI1 mipi_csi1_power_domain
182 #define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm 184 #define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm
183 #define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c 185 #define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c
184 186
185 #define PD_HDMI hdmi_power_domain 187 #define PD_HDMI hdmi_power_domain
186 #define PD_HDMI_I2C_0 hdmi_i2c 188 #define PD_HDMI_I2C_0 hdmi_i2c
187 #define PD_HDMI_PWM_0 hdmi_pwm 189 #define PD_HDMI_PWM_0 hdmi_pwm
188 #define PD_HDMI_GPIO_0 hdmi_gpio 190 #define PD_HDMI_GPIO_0 hdmi_gpio
189 191
190 #define PD_HDMI_RX hdmi_rx_power_domain 192 #define PD_HDMI_RX hdmi_rx_power_domain
191 #define PD_HDMI_RX_I2C hdmi_rx_i2c 193 #define PD_HDMI_RX_I2C hdmi_rx_i2c
192 #define PD_HDMI_RX_PWM hdmi_rx_pwm 194 #define PD_HDMI_RX_PWM hdmi_rx_pwm
193 195
194 #define PD_CM40 cm40_power_domain 196 #define PD_CM40 cm40_power_domain
195 #define PD_CM40_I2C cm40_i2c 197 #define PD_CM40_I2C cm40_i2c
196 #define PD_CM40_INTMUX cm40_intmux 198 #define PD_CM40_INTMUX cm40_intmux
197 199
198 #endif /* __DT_BINDINGS_IMX8_PD_H */ 200 #endif /* __DT_BINDINGS_IMX8_PD_H */
199 201
200 202