Commit 70fa29c71663e1c0882c263c6fd5c089d4d90e0b
1 parent
c882f43aef
Exists in
smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga
and in
4 other branches
MLK-20886-7 DTS: imx8qm/qxp: Add MU8 and MU9 nodes
We use MU8 and MU9 to communicate with M4_0 and M4_1 in u-boot. Add relevant nodes for the MU driver. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b06674a91991fe3bfe5a2f6000195cb8546c72a6)
Showing 3 changed files with 41 additions and 0 deletions Side-by-side Diff
arch/arm/dts/fsl-imx8qm.dtsi
| ... | ... | @@ -104,6 +104,22 @@ |
| 104 | 104 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; |
| 105 | 105 | }; |
| 106 | 106 | |
| 107 | + mu8: mu@5d230000 { | |
| 108 | + compatible = "fsl,imx-m4-mu"; | |
| 109 | + reg = <0x0 0x5d230000 0x0 0x10000>; | |
| 110 | + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 111 | + power-domains = <&pd_lsio_mu8a>; | |
| 112 | + status = "okay"; | |
| 113 | + }; | |
| 114 | + | |
| 115 | + mu9: mu@5d240000 { | |
| 116 | + compatible = "fsl,imx-m4-mu"; | |
| 117 | + reg = <0x0 0x5d240000 0x0 0x10000>; | |
| 118 | + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
| 119 | + power-domains = <&pd_lsio_mu9a>; | |
| 120 | + status = "okay"; | |
| 121 | + }; | |
| 122 | + | |
| 107 | 123 | mu: mu@5d1b0000 { |
| 108 | 124 | compatible = "fsl,imx8-mu"; |
| 109 | 125 | reg = <0x0 0x5d1b0000 0x0 0x10000>; |
| ... | ... | @@ -450,6 +466,16 @@ |
| 450 | 466 | }; |
| 451 | 467 | pd_lsio_flexspi1: PD_LSIO_FSPI_1{ |
| 452 | 468 | reg = <SC_R_FSPI_1>; |
| 469 | + #power-domain-cells = <0>; | |
| 470 | + power-domains = <&pd_lsio>; | |
| 471 | + }; | |
| 472 | + pd_lsio_mu8a: PD_LSIO_MU8A { | |
| 473 | + reg = <SC_R_MU_8A>; | |
| 474 | + #power-domain-cells = <0>; | |
| 475 | + power-domains = <&pd_lsio>; | |
| 476 | + }; | |
| 477 | + pd_lsio_mu9a: PD_LSIO_MU9A { | |
| 478 | + reg = <SC_R_MU_9A>; | |
| 453 | 479 | #power-domain-cells = <0>; |
| 454 | 480 | power-domains = <&pd_lsio>; |
| 455 | 481 | }; |
arch/arm/dts/fsl-imx8qxp.dtsi
| ... | ... | @@ -99,6 +99,14 @@ |
| 99 | 99 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; |
| 100 | 100 | }; |
| 101 | 101 | |
| 102 | + mu8: mu@5d230000 { | |
| 103 | + compatible = "fsl,imx-m4-mu"; | |
| 104 | + reg = <0x0 0x5d230000 0x0 0x10000>; | |
| 105 | + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 106 | + power-domains = <&pd_lsio_mu8a>; | |
| 107 | + status = "okay"; | |
| 108 | + }; | |
| 109 | + | |
| 102 | 110 | mu: mu@5d1b0000 { |
| 103 | 111 | compatible = "fsl,imx8-mu"; |
| 104 | 112 | reg = <0x0 0x5d1b0000 0x0 0x10000>; |
| ... | ... | @@ -267,6 +275,11 @@ |
| 267 | 275 | }; |
| 268 | 276 | pd_lsio_flexspi1: PD_LSIO_FSPI_1{ |
| 269 | 277 | reg = <SC_R_FSPI_1>; |
| 278 | + #power-domain-cells = <0>; | |
| 279 | + power-domains = <&pd_lsio>; | |
| 280 | + }; | |
| 281 | + pd_lsio_mu8a: PD_LSIO_MU8A { | |
| 282 | + reg = <SC_R_MU_8A>; | |
| 270 | 283 | #power-domain-cells = <0>; |
| 271 | 284 | power-domains = <&pd_lsio>; |
| 272 | 285 | }; |
include/dt-bindings/soc/imx8_pd.h
| ... | ... | @@ -102,6 +102,8 @@ |
| 102 | 102 | #define PD_LSIO_PWM_5 lsio_pwm5 |
| 103 | 103 | #define PD_LSIO_PWM_6 lsio_pwm6 |
| 104 | 104 | #define PD_LSIO_PWM_7 lsio_pwm7 |
| 105 | +#define PD_LSIO_MU8A lsio_mu8a | |
| 106 | +#define PD_LSIO_MU9A lsio_mu9a | |
| 105 | 107 | |
| 106 | 108 | #define PD_CONN connectivity_power_domain |
| 107 | 109 | #define PD_CONN_SDHC_0 conn_sdhc0 |