Eric Lee / smarc-uboot

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Commit 711b534120c0a5f73cdb9a25eb91f9aa0c5e09ab

Authored by Tom Rini
2 parents 8435179271 76379dfb7e
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge git://git.denx.de/u-boot-fsl-qoriq 

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1021aqds.h
	include/configs/ls1021atwr.h

Showing 60 changed files Side-by-side Diff

... ... @@ -656,6 +656,7 @@
656 656  
657 657 config TARGET_LS2080A_EMU
658 658 bool "Support ls2080a_emu"
  659 + select ARCH_LS2080A
659 660 select ARM64
660 661 select ARMV8_MULTIENTRY
661 662 help
... ... @@ -666,6 +667,7 @@
666 667  
667 668 config TARGET_LS2080A_SIMU
668 669 bool "Support ls2080a_simu"
  670 + select ARCH_LS2080A
669 671 select ARM64
670 672 select ARMV8_MULTIENTRY
671 673 help
... ... @@ -676,6 +678,7 @@
676 678  
677 679 config TARGET_LS2080AQDS
678 680 bool "Support ls2080aqds"
  681 + select ARCH_LS2080A
679 682 select ARM64
680 683 select ARMV8_MULTIENTRY
681 684 select SUPPORT_SPL
... ... @@ -687,6 +690,7 @@
687 690  
688 691 config TARGET_LS2080ARDB
689 692 bool "Support ls2080ardb"
  693 + select ARCH_LS2080A
690 694 select ARM64
691 695 select ARMV8_MULTIENTRY
692 696 select SUPPORT_SPL
... ... @@ -740,6 +744,8 @@
740 744 config TARGET_LS1021AQDS
741 745 bool "Support ls1021aqds"
742 746 select CPU_V7
  747 + select CPU_V7_HAS_NONSEC
  748 + select CPU_V7_HAS_VIRT
743 749 select SUPPORT_SPL
744 750 select ARCH_LS1021A
745 751 select ARCH_SUPPORT_PSCI
... ... @@ -748,6 +754,8 @@
748 754 config TARGET_LS1021ATWR
749 755 bool "Support ls1021atwr"
750 756 select CPU_V7
  757 + select CPU_V7_HAS_NONSEC
  758 + select CPU_V7_HAS_VIRT
751 759 select SUPPORT_SPL
752 760 select ARCH_LS1021A
753 761 select ARCH_SUPPORT_PSCI
arch/arm/cpu/armv7/Makefile
Diff comments   View file @ 711b534
... ... @@ -12,7 +12,7 @@
12 12 obj-y += cpu.o cp15.o
13 13 obj-y += syslib.o
14 14  
15   -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
  15 +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
16 16 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
17 17 obj-y += lowlevel_init.o
18 18 endif
arch/arm/cpu/armv7/ls102xa/Kconfig
Diff comments   View file @ 711b534
1 1 config ARCH_LS1021A
2   - bool "Freescale Layerscape LS1021A SoC"
  2 + bool
3 3 select SYS_FSL_ERRATUM_A010315
  4 + select SYS_FSL_SRDS_1
  5 + select SYS_HAS_SERDES
  6 + select SYS_FSL_DDR_BE
  7 + select SYS_FSL_DDR_VER_50
4 8  
  9 +menu "LS102xA architecture"
  10 + depends on ARCH_LS1021A
  11 +
5 12 config LS1_DEEP_SLEEP
6   - bool "Freescale Layerscape 1 deep sleep"
  13 + bool "Deep sleep"
  14 + depends on ARCH_LS1021A
  15 +
  16 +config MAX_CPUS
  17 + int "Maximum number of CPUs permitted for LS102xA"
  18 + depends on ARCH_LS1021A
  19 + default 2
  20 + help
  21 + Set this number to the maximum number of possible CPUs in the SoC.
  22 + SoCs may have multiple clusters with each cluster may have multiple
  23 + ports. If some ports are reserved but higher ports are used for
  24 + cores, count the reserved ports. This will allocate enough memory
  25 + in spin table to properly handle all cores.
  26 +
  27 +config NUM_DDR_CONTROLLERS
  28 + int "Maximum DDR controllers"
  29 + default 1
  30 +
  31 +config SYS_FSL_ERRATUM_A010315
  32 + bool "Workaround for PCIe erratum A010315"
  33 +
  34 +config SYS_FSL_SRDS_1
  35 + bool
  36 +
  37 +config SYS_FSL_SRDS_2
  38 + bool
  39 +
  40 +config SYS_HAS_SERDES
  41 + bool
  42 +
  43 +config SYS_FSL_DDR
  44 + bool "Freescale DDR driver"
  45 + help
  46 + Select Freescale General DDR driver, shared between most Freescale
  47 + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
  48 + based Layerscape SoCs (such as ls2080a).
  49 +
  50 +config SYS_FSL_DDR_BE
  51 + bool
  52 + default y
  53 + help
  54 + Access DDR registers in big-endian.
  55 +
  56 +config SYS_FSL_DDR_VER
  57 + int
  58 + default 50 if SYS_FSL_DDR_VER_50
  59 +
  60 +config SYS_FSL_DDR_VER_50
  61 + bool
  62 +
  63 +config SYS_FSL_DDRC_ARM_GEN3
  64 + bool
  65 +
  66 +config SYS_FSL_DDRC_GEN4
  67 + bool
  68 +
  69 +config SYS_FSL_DDR3
  70 + bool "Freescale DDR3 controller"
  71 + depends on !SYS_FSL_DDR4
  72 + select SYS_FSL_DDR
  73 + select SYS_FSL_DDRC_ARM_GEN3
  74 + help
  75 + Enable Freescale DDR3 controller on ARM-based SoCs.
  76 +
  77 +config SYS_FSL_DDR4
  78 + bool "Freescale DDR4 controller"
  79 + select SYS_FSL_DDR
  80 + select SYS_FSL_DDRC_GEN4
  81 + help
  82 + Enable Freescale DDR4 controller.
  83 +
  84 +config SYS_FSL_IFC_BANK_COUNT
  85 + int "Maximum banks of Integrated flash controller"
  86 + depends on ARCH_LS1021A
  87 + default 8
  88 +
  89 +endmenu
arch/arm/cpu/armv7/ls102xa/soc.c
Diff comments   View file @ 711b534
... ... @@ -60,6 +60,10 @@
60 60 return major;
61 61 }
62 62  
  63 +void s_init(void)
  64 +{
  65 +}
  66 +
63 67 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
64 68 void erratum_a010315(void)
65 69 {
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 711b534
1 1 config ARCH_LS1012A
2   - bool "Freescale Layerscape LS1012A SoC"
  2 + bool
  3 + select FSL_LSCH2
  4 + select SYS_FSL_DDR_BE
3 5 select SYS_FSL_MMDC
4 6 select SYS_FSL_ERRATUM_A010315
5 7  
6 8 config ARCH_LS1043A
7   - bool "Freescale Layerscape LS1043A SoC"
  9 + bool
  10 + select FSL_LSCH2
  11 + select SYS_FSL_DDR_BE
  12 + select SYS_FSL_DDR_VER_50
8 13 select SYS_FSL_ERRATUM_A010315
  14 + select SYS_FSL_ERRATUM_A010539
9 15  
10 16 config ARCH_LS1046A
11   - bool "Freescale Layerscape LS1046A SoC"
  17 + bool
  18 + select FSL_LSCH2
  19 + select SYS_FSL_DDR_BE
  20 + select SYS_FSL_DDR4
  21 + select SYS_FSL_DDR_VER_50
  22 + select SYS_FSL_ERRATUM_A010539
  23 + select SYS_FSL_SRDS_2
12 24  
  25 +config ARCH_LS2080A
  26 + bool
  27 + select FSL_LSCH3
  28 + select SYS_FSL_DDR4
  29 + select SYS_FSL_DDR_LE
  30 + select SYS_FSL_DDR_VER_50
  31 + select SYS_FSL_HAS_DP_DDR
  32 + select SYS_FSL_SRDS_2
  33 +
  34 +config FSL_LSCH2
  35 + bool
  36 + select SYS_FSL_SRDS_1
  37 + select SYS_HAS_SERDES
  38 +
  39 +config FSL_LSCH3
  40 + bool
  41 + select SYS_FSL_SRDS_1
  42 + select SYS_HAS_SERDES
  43 +
  44 +menu "Layerscape architecture"
  45 + depends on FSL_LSCH2 || FSL_LSCH3
  46 +
13 47 config SYS_FSL_MMDC
14   - bool "Freescale Multi Mode DDR Controller"
  48 + bool
15 49  
16 50 config SYS_FSL_ERRATUM_A010315
17 51 bool "Workaround for PCIe erratum A010315"
  52 +
  53 +config SYS_FSL_ERRATUM_A010539
  54 + bool "Workaround for PIN MUX erratum A010539"
  55 +
  56 +config MAX_CPUS
  57 + int "Maximum number of CPUs permitted for Layerscape"
  58 + default 4 if ARCH_LS1043A
  59 + default 4 if ARCH_LS1046A
  60 + default 16 if ARCH_LS2080A
  61 + default 1
  62 + help
  63 + Set this number to the maximum number of possible CPUs in the SoC.
  64 + SoCs may have multiple clusters with each cluster may have multiple
  65 + ports. If some ports are reserved but higher ports are used for
  66 + cores, count the reserved ports. This will allocate enough memory
  67 + in spin table to properly handle all cores.
  68 +
  69 +config NUM_DDR_CONTROLLERS
  70 + int "Maximum DDR controllers"
  71 + default 3 if ARCH_LS2080A
  72 + default 1
  73 +
  74 +config SYS_FSL_IFC_BANK_COUNT
  75 + int "Maximum banks of Integrated flash controller"
  76 + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
  77 + default 4 if ARCH_LS1043A
  78 + default 4 if ARCH_LS1046A
  79 + default 8 if ARCH_LS2080A
  80 +
  81 +config SYS_FSL_HAS_DP_DDR
  82 + bool
  83 +
  84 +config SYS_FSL_SRDS_1
  85 + bool
  86 +
  87 +config SYS_FSL_SRDS_2
  88 + bool
  89 +
  90 +config SYS_HAS_SERDES
  91 + bool
  92 +
  93 +config SYS_FSL_DDR
  94 + bool "Freescale DDR driver"
  95 + help
  96 + Select Freescale General DDR driver, shared between most Freescale
  97 + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
  98 + based Layerscape SoCs (such as ls2080a).
  99 +
  100 +config SYS_FSL_DDR_BE
  101 + bool
  102 + help
  103 + Access DDR registers in big-endian.
  104 +
  105 +config SYS_FSL_DDR_LE
  106 + bool
  107 + help
  108 + Access DDR registers in little-endian.
  109 +
  110 +config SYS_FSL_DDR_VER
  111 + int
  112 + default 50 if SYS_FSL_DDR_VER_50
  113 +
  114 +config SYS_FSL_DDR_VER_50
  115 + bool
  116 +
  117 +config SYS_FSL_DDRC_ARM_GEN3
  118 + bool
  119 +
  120 +config SYS_FSL_DDRC_GEN4
  121 + bool
  122 +
  123 +config SYS_FSL_DDR3
  124 + bool "Freescale DDR3 controller"
  125 + depends on !SYS_FSL_DDR4
  126 + select SYS_FSL_DDR
  127 + select SYS_FSL_DDRC_ARM_GEN3
  128 + help
  129 + Enable Freescale DDR3 controller on ARM-based SoCs.
  130 +
  131 +config SYS_FSL_DDR4
  132 + bool "Freescale DDR4 controller"
  133 + select SYS_FSL_DDR
  134 + select SYS_FSL_DDRC_GEN4
  135 + help
  136 + Enable Freescale DDR4 controller.
  137 +
  138 +endmenu
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 711b534
... ... @@ -44,6 +44,9 @@
44 44  
45 45 if (IS_E_PROCESSOR(svr))
46 46 strcat(name, "E");
  47 +
  48 + sprintf(name + strlen(name), " Rev%d.%d",
  49 + SVR_MAJ(svr), SVR_MIN(svr));
47 50 break;
48 51 }
49 52  
... ... @@ -198,6 +201,27 @@
198 201 return type;
199 202  
200 203 return 0;
  204 +}
  205 +
  206 +u32 cpu_pos_mask(void)
  207 +{
  208 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  209 + int i = 0;
  210 + u32 cluster, type, mask = 0;
  211 +
  212 + do {
  213 + int j;
  214 +
  215 + cluster = gur_in32(&gur->tp_cluster[i].lower);
  216 + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  217 + type = initiator_type(cluster, j);
  218 + if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
  219 + mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
  220 + }
  221 + i++;
  222 + } while ((cluster & TP_CLUSTER_EOC) == 0x0);
  223 +
  224 + return mask;
201 225 }
202 226  
203 227 u32 cpu_mask(void)
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
Diff comments   View file @ 711b534
... ... @@ -108,6 +108,24 @@
108 108 }
109 109 #endif
110 110  
  111 +void fsl_fdt_disable_usb(void *blob)
  112 +{
  113 + int off;
  114 + /*
  115 + * SYSCLK is used as a reference clock for USB. When the USB
  116 + * controller is used, SYSCLK must meet the additional requirement
  117 + * of 100 MHz.
  118 + */
  119 + if (CONFIG_SYS_CLK_FREQ != 100000000) {
  120 + off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
  121 + while (off != -FDT_ERR_NOTFOUND) {
  122 + fdt_status_disabled(blob, off);
  123 + off = fdt_node_offset_by_compatible(blob, off,
  124 + "snps,dwc3");
  125 + }
  126 + }
  127 +}
  128 +
111 129 void ft_cpu_setup(void *blob, bd_t *bd)
112 130 {
113 131 #ifdef CONFIG_FSL_LSCH2
... ... @@ -150,5 +168,7 @@
150 168 #ifdef CONFIG_SYS_DPAA_FMAN
151 169 fdt_fixup_fman_firmware(blob);
152 170 #endif
  171 + fsl_fdt_disable_usb(blob);
  172 +
153 173 }
arch/arm/cpu/armv8/fsl-layerscape/mp.c
Diff comments   View file @ 711b534
... ... @@ -104,6 +104,11 @@
104 104 return !!((1 << core) & cpu_mask());
105 105 }
106 106  
  107 +static int is_pos_valid(unsigned int pos)
  108 +{
  109 + return !!((1 << pos) & cpu_pos_mask());
  110 +}
  111 +
107 112 int is_core_online(u64 cpu_id)
108 113 {
109 114 u64 *table;
110 115  
... ... @@ -126,9 +131,9 @@
126 131 return 0;
127 132 }
128 133  
129   -int core_to_pos(int nr)
  134 +static int core_to_pos(int nr)
130 135 {
131   - u32 cores = cpu_mask();
  136 + u32 cores = cpu_pos_mask();
132 137 int i, count = 0;
133 138  
134 139 if (nr == 0) {
135 140  
... ... @@ -139,14 +144,17 @@
139 144 }
140 145  
141 146 for (i = 1; i < 32; i++) {
142   - if (is_core_valid(i)) {
  147 + if (is_pos_valid(i)) {
143 148 count++;
144 149 if (count == nr)
145 150 break;
146 151 }
147 152 }
148 153  
149   - return count;
  154 + if (count != nr)
  155 + return -1;
  156 +
  157 + return i;
150 158 }
151 159  
152 160 int cpu_status(int nr)
arch/arm/cpu/armv8/fsl-layerscape/soc.c
Diff comments   View file @ 711b534
... ... @@ -233,9 +233,8 @@
233 233 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
234 234 #endif
235 235 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
236   - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
237   - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
238 236 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
  237 + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
239 238  
240 239 ahci_init((void __iomem *)CONFIG_SYS_SATA);
241 240 scsi_scan(0);
... ... @@ -321,6 +320,19 @@
321 320 }
322 321 #endif
323 322  
  323 +static void erratum_a010539(void)
  324 +{
  325 +#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  326 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  327 + u32 porsr1;
  328 +
  329 + porsr1 = in_be32(&gur->porsr1);
  330 + porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  331 + out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  332 + porsr1);
  333 +#endif
  334 +}
  335 +
324 336 void fsl_lsch2_early_init_f(void)
325 337 {
326 338 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
... ... @@ -339,7 +351,9 @@
339 351 #endif
340 352 /* Make SEC reads and writes snoopable */
341 353 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
342   - SCFG_SNPCNFGCR_SECWRSNP);
  354 + SCFG_SNPCNFGCR_SECWRSNP |
  355 + SCFG_SNPCNFGCR_SATARDSNP |
  356 + SCFG_SNPCNFGCR_SATAWRSNP);
343 357  
344 358 /*
345 359 * Enable snoop requests and DVM message requests for
... ... @@ -352,6 +366,7 @@
352 366 erratum_a008850_early(); /* part 1 of 2 */
353 367 erratum_a009929();
354 368 erratum_a009660();
  369 + erratum_a010539();
355 370 }
356 371 #endif
357 372  
arch/arm/dts/fsl-ls1043a.dtsi
Diff comments   View file @ 711b534
... ... @@ -215,6 +215,27 @@
215 215 big-endian;
216 216 status = "disabled";
217 217 };
  218 +
  219 + usb0: usb3@2f00000 {
  220 + compatible = "fsl,layerscape-dwc3";
  221 + reg = <0x0 0x2f00000 0x0 0x10000>;
  222 + interrupts = <0 60 0x4>;
  223 + dr_mode = "host";
  224 + };
  225 +
  226 + usb1: usb3@3000000 {
  227 + compatible = "fsl,layerscape-dwc3";
  228 + reg = <0x0 0x3000000 0x0 0x10000>;
  229 + interrupts = <0 61 0x4>;
  230 + dr_mode = "host";
  231 + };
  232 +
  233 + usb2: usb3@3100000 {
  234 + compatible = "fsl,layerscape-dwc3";
  235 + reg = <0x0 0x3100000 0x0 0x10000>;
  236 + interrupts = <0 63 0x4>;
  237 + dr_mode = "host";
  238 + };
218 239 };
219 240 };
arch/arm/dts/fsl-ls2080a.dtsi
Diff comments   View file @ 711b534
... ... @@ -75,5 +75,19 @@
75 75 reg-names = "QuadSPI", "QuadSPI-memory";
76 76 num-cs = <4>;
77 77 };
  78 +
  79 + usb0: usb3@3100000 {
  80 + compatible = "fsl,layerscape-dwc3";
  81 + reg = <0x0 0x3100000 0x0 0x10000>;
  82 + interrupts = <0 80 0x4>; /* Level high type */
  83 + dr_mode = "host";
  84 + };
  85 +
  86 + usb1: usb3@3110000 {
  87 + compatible = "fsl,layerscape-dwc3";
  88 + reg = <0x0 0x3110000 0x0 0x10000>;
  89 + interrupts = <0 81 0x4>; /* Level high type */
  90 + dr_mode = "host";
  91 + };
78 92 };
arch/arm/include/asm/arch-fsl-layerscape/config.h
Diff comments   View file @ 711b534
... ... @@ -12,17 +12,6 @@
12 12  
13 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
14 14  
15   -#ifdef CONFIG_SYS_FSL_DDR4
16   -#define CONFIG_SYS_FSL_DDRC_GEN4
17   -#else
18   -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
19   -#endif
20   -
21   -#ifndef CONFIG_ARCH_LS1012A
22   -#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
23   -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
24   -#endif
25   -
26 15 /*
27 16 * Reserve secure memory
28 17 * To be aligned with MMU block size
29 18  
... ... @@ -30,14 +19,8 @@
30 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
31 20  
32 21 #ifdef CONFIG_LS2080A
33   -#define CONFIG_MAX_CPUS 16
34   -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
35   -#define CONFIG_NUM_DDR_CONTROLLERS 3
36   -#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
37 22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
38 23 #define SRDS_MAX_LANES 8
39   -#define CONFIG_SYS_FSL_SRDS_1
40   -#define CONFIG_SYS_FSL_SRDS_2
41 24 #define CONFIG_SYS_PAGE_SIZE 0x10000
42 25 #ifndef L1_CACHE_BYTES
43 26 #define L1_CACHE_SHIFT 6
... ... @@ -48,7 +31,6 @@
48 31 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
49 32  
50 33 /* DDR */
51   -#define CONFIG_SYS_FSL_DDR_LE
52 34 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
53 35 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
54 36  
... ... @@ -152,7 +134,6 @@
152 134  
153 135 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
154 136 #elif defined(CONFIG_FSL_LSCH2)
155   -#define CONFIG_NUM_DDR_CONTROLLERS 1
156 137 #define CONFIG_SYS_FSL_SEC_COMPAT 5
157 138 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
158 139 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
159 140  
160 141  
... ... @@ -167,17 +148,12 @@
167 148 #define CONFIG_SYS_FSL_PEX_LUT_BE
168 149 #define CONFIG_SYS_FSL_SEC_BE
169 150  
170   -#define CONFIG_SYS_FSL_SRDS_1
171   -
172 151 /* SoC related */
173 152 #ifdef CONFIG_LS1043A
174   -#define CONFIG_MAX_CPUS 4
175 153 #define CONFIG_SYS_FMAN_V3
176 154 #define CONFIG_SYS_NUM_FMAN 1
177 155 #define CONFIG_SYS_NUM_FM1_DTSEC 7
178 156 #define CONFIG_SYS_NUM_FM1_10GEC 1
179   -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
180   -#define CONFIG_SYS_FSL_DDR_BE
181 157 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
182 158 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
183 159  
184 160  
185 161  
186 162  
... ... @@ -206,23 +182,18 @@
206 182 #define CONFIG_SYS_FSL_ERRATUM_A009660
207 183 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
208 184 #elif defined(CONFIG_ARCH_LS1012A)
209   -#define CONFIG_MAX_CPUS 1
210 185 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
211 186  
212 187 #define GICD_BASE 0x01401000
213 188 #define GICC_BASE 0x01402000
214 189 #elif defined(CONFIG_ARCH_LS1046A)
215   -#define CONFIG_MAX_CPUS 4
216 190 #define CONFIG_SYS_FMAN_V3
217 191 #define CONFIG_SYS_NUM_FMAN 1
218 192 #define CONFIG_SYS_NUM_FM1_DTSEC 8
219 193 #define CONFIG_SYS_NUM_FM1_10GEC 2
220   -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
221   -#define CONFIG_SYS_FSL_DDR_BE
222 194 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
223 195 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
224 196  
225   -#define CONFIG_SYS_FSL_SRDS_2
226 197 #define CONFIG_SYS_FSL_IFC_BE
227 198 #define CONFIG_SYS_FSL_SFP_VER_3_2
228 199 #define CONFIG_SYS_FSL_SNVS_LE
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Diff comments   View file @ 711b534
... ... @@ -168,6 +168,8 @@
168 168 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
169 169  
170 170 /* Device Configuration and Pin Control */
  171 +#define DCFG_DCSR_PORCR1 0x0
  172 +
171 173 struct ccsr_gur {
172 174 u32 porsr1; /* POR status 1 */
173 175 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
... ... @@ -335,6 +337,8 @@
335 337  
336 338 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
337 339 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
  340 +#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
  341 +#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
338 342  
339 343 /* Supplemental Configuration Unit */
340 344 struct ccsr_scfg {
arch/arm/include/asm/arch-fsl-layerscape/mp.h
Diff comments   View file @ 711b534
... ... @@ -34,6 +34,7 @@
34 34 phys_addr_t determine_mp_bootpg(void);
35 35 void secondary_boot_func(void);
36 36 int is_core_online(u64 cpu_id);
  37 +u32 cpu_pos_mask(void);
37 38 #endif
38 39 #endif /* _FSL_LAYERSCAPE_MP_H */
arch/arm/include/asm/arch-fsl-layerscape/soc.h
Diff comments   View file @ 711b534
... ... @@ -60,9 +60,8 @@
60 60  
61 61 /* ahci port register default value */
62 62 #define AHCI_PORT_PHY_1_CFG 0xa003fffe
63   -#define AHCI_PORT_PHY_2_CFG 0x28184d1f
64   -#define AHCI_PORT_PHY_3_CFG 0x0e081509
65 63 #define AHCI_PORT_TRANS_CFG 0x08000029
  64 +#define AHCI_PORT_AXICC_CFG 0x3fffffff
66 65  
67 66 /* AHCI (sata) register map */
68 67 struct ccsr_ahci {
arch/arm/include/asm/arch-ls102xa/config.h
Diff comments   View file @ 711b534
... ... @@ -94,14 +94,7 @@
94 94 #define CONFIG_SYS_FSL_ERRATUM_A008407
95 95  
96 96 #ifdef CONFIG_DDR_SPD
97   -#define CONFIG_SYS_FSL_DDR_BE
98 97 #define CONFIG_VERY_BIG_RAM
99   -#ifdef CONFIG_SYS_FSL_DDR4
100   -#define CONFIG_SYS_FSL_DDRC_GEN4
101   -#else
102   -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
103   -#endif
104   -#define CONFIG_SYS_FSL_DDR
105 98 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
106 99 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
107 100 #endif
108 101  
... ... @@ -120,13 +113,7 @@
120 113  
121 114 #define DCU_LAYER_MAX_NUM 16
122 115  
123   -#define CONFIG_SYS_FSL_SRDS_1
124   -
125 116 #ifdef CONFIG_LS102XA
126   -#define CONFIG_MAX_CPUS 2
127   -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
128   -#define CONFIG_NUM_DDR_CONTROLLERS 1
129   -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
130 117 #define CONFIG_SYS_FSL_SEC_COMPAT 5
131 118 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
132 119 #define CONFIG_SYS_FSL_ERRATUM_A008378
board/freescale/common/fsl_validate.c
Diff comments   View file @ 711b534
... ... @@ -301,27 +301,15 @@
301 301 */
302 302 static void fsl_secboot_header_verification_failure(void)
303 303 {
304   - struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
305   - (CONFIG_SYS_SEC_MON_ADDR);
306 304 struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
307   - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
308 305  
309 306 /* 29th bit of OSPR is ITS */
310 307 u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
311 308  
312   - /*
313   - * Read the SEC_MON status register
314   - * Read SSM_ST field
315   - */
316   - sts = sec_mon_in32(&sec_mon_regs->hp_stat);
317   - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
318   - if (its == 1)
319   - change_sec_mon_state(HPSR_SSM_ST_TRUST,
320   - HPSR_SSM_ST_SOFT_FAIL);
321   - else
322   - change_sec_mon_state(HPSR_SSM_ST_TRUST,
323   - HPSR_SSM_ST_NON_SECURE);
324   - }
  309 + if (its == 1)
  310 + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
  311 + else
  312 + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
325 313  
326 314 printf("Generating reset request\n");
327 315 do_reset(NULL, 0, 0, NULL);
328 316  
329 317  
330 318  
331 319  
... ... @@ -338,32 +326,20 @@
338 326 */
339 327 static void fsl_secboot_image_verification_failure(void)
340 328 {
341   - struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
342   - (CONFIG_SYS_SEC_MON_ADDR);
343 329 struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
344   - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
345 330  
346 331 u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
347 332  
348   - /*
349   - * Read the SEC_MON status register
350   - * Read SSM_ST field
351   - */
352   - sts = sec_mon_in32(&sec_mon_regs->hp_stat);
353   - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
354   - if (its == 1) {
355   - change_sec_mon_state(HPSR_SSM_ST_TRUST,
356   - HPSR_SSM_ST_SOFT_FAIL);
  333 + if (its == 1) {
  334 + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
357 335  
358   - printf("Generating reset request\n");
359   - do_reset(NULL, 0, 0, NULL);
360   - /* If reset doesn't coocur, halt execution */
361   - do_esbc_halt(NULL, 0, 0, NULL);
  336 + printf("Generating reset request\n");
  337 + do_reset(NULL, 0, 0, NULL);
  338 + /* If reset doesn't coocur, halt execution */
  339 + do_esbc_halt(NULL, 0, 0, NULL);
362 340  
363   - } else {
364   - change_sec_mon_state(HPSR_SSM_ST_TRUST,
365   - HPSR_SSM_ST_NON_SECURE);
366   - }
  341 + } else {
  342 + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
367 343 }
368 344 }
369 345  
board/freescale/ls1021aqds/README
Diff comments   View file @ 711b534
... ... @@ -110,4 +110,10 @@
110 110 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
111 111 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
112 112 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
  113 +
  114 +LS1021a rev1.0 Soc specific Options/Settings
  115 +--------------------------------------------
  116 +If the LS1021a Soc is rev1.0, you need modify the configure file.
  117 +Add the following define in include/configs/ls1021aqds.h:
  118 +#define CONFIG_SKIP_LOWLEVEL_INIT
board/freescale/ls1021atwr/README
Diff comments   View file @ 711b534
... ... @@ -107,4 +107,10 @@
107 107 0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
108 108 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
109 109 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
  110 +
  111 +LS1021a rev1.0 Soc specific Options/Settings
  112 +--------------------------------------------
  113 +If the LS1021a Soc is rev1.0, you need modify the configure file.
  114 +Add the following define in include/configs/ls1021atwr.h:
  115 +#define CONFIG_SKIP_LOWLEVEL_INIT
configs/ls1021aqds_ddr4_nor_defconfig
Diff comments   View file @ 711b534
... ... @@ -5,7 +5,7 @@
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7 7 CONFIG_OF_STDOUT_VIA_ALIAS=y
8   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
  8 +CONFIG_SYS_FSL_DDR4=y
9 9 CONFIG_BOOTDELAY=3
10 10 CONFIG_HUSH_PARSER=y
11 11 CONFIG_CMD_BOOTZ=y
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
Diff comments   View file @ 711b534
... ... @@ -5,7 +5,8 @@
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7 7 CONFIG_OF_STDOUT_VIA_ALIAS=y
8   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
  8 +CONFIG_SYS_EXTRA_OPTIONS="LPUART"
  9 +CONFIG_SYS_FSL_DDR4=y
9 10 CONFIG_BOOTDELAY=3
10 11 CONFIG_HUSH_PARSER=y
11 12 CONFIG_CMD_BOOTZ=y
configs/ls1021aqds_nand_defconfig
Diff comments   View file @ 711b534
... ... @@ -13,6 +13,7 @@
13 13 CONFIG_OF_BOARD_SETUP=y
14 14 CONFIG_OF_STDOUT_VIA_ALIAS=y
15 15 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
  16 +CONFIG_SYS_FSL_DDR3=y
16 17 CONFIG_NAND_BOOT=y
17 18 CONFIG_BOOTDELAY=3
18 19 CONFIG_SPL=y
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
Diff comments   View file @ 711b534
... ... @@ -6,6 +6,7 @@
6 6 CONFIG_OF_BOARD_SETUP=y
7 7 CONFIG_OF_STDOUT_VIA_ALIAS=y
8 8 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
  9 +CONFIG_SYS_FSL_DDR3=y
9 10 CONFIG_BOOTDELAY=3
10 11 CONFIG_HUSH_PARSER=y
11 12 CONFIG_CMD_BOOTZ=y
configs/ls1021aqds_nor_defconfig
Diff comments   View file @ 711b534
... ... @@ -25,6 +25,7 @@
25 25 CONFIG_NETDEVICES=y
26 26 CONFIG_E1000=y
27 27 CONFIG_DM_SERIAL=y
  28 +CONFIG_SYS_FSL_DDR3=y
28 29 CONFIG_SYS_NS16550=y
29 30 CONFIG_USB=y
30 31 CONFIG_DM_USB=y
configs/ls1021aqds_nor_lpuart_defconfig
Diff comments   View file @ 711b534
... ... @@ -6,6 +6,7 @@
6 6 CONFIG_OF_BOARD_SETUP=y
7 7 CONFIG_OF_STDOUT_VIA_ALIAS=y
8 8 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
  9 +CONFIG_SYS_FSL_DDR3=y
9 10 CONFIG_BOOTDELAY=3
10 11 CONFIG_HUSH_PARSER=y
11 12 CONFIG_CMD_BOOTZ=y
configs/ls1021aqds_qspi_defconfig
Diff comments   View file @ 711b534
... ... @@ -6,6 +6,7 @@
6 6 CONFIG_OF_BOARD_SETUP=y
7 7 CONFIG_OF_STDOUT_VIA_ALIAS=y
8 8 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
  9 +CONFIG_SYS_FSL_DDR3=y
9 10 CONFIG_QSPI_BOOT=y
10 11 CONFIG_BOOTDELAY=3
11 12 CONFIG_HUSH_PARSER=y
configs/ls1021aqds_sdcard_ifc_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,6 +12,7 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
  15 +CONFIG_SYS_FSL_DDR3=y
15 16 CONFIG_SD_BOOT=y
16 17 CONFIG_BOOTDELAY=3
17 18 CONFIG_SPL=y
configs/ls1021aqds_sdcard_qspi_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,6 +12,7 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
  15 +CONFIG_SYS_FSL_DDR3=y
15 16 CONFIG_SD_BOOT=y
16 17 CONFIG_BOOTDELAY=3
17 18 CONFIG_SPL=y
configs/ls1043aqds_defconfig
Diff comments   View file @ 711b534
... ... @@ -4,7 +4,7 @@
4 4 CONFIG_FIT=y
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
  7 +CONFIG_SYS_FSL_DDR4=y
8 8 CONFIG_BOOTDELAY=10
9 9 CONFIG_HUSH_PARSER=y
10 10 CONFIG_CMD_BOOTZ=y
... ... @@ -29,5 +29,6 @@
29 29 CONFIG_USB=y
30 30 CONFIG_USB_XHCI_HCD=y
31 31 CONFIG_USB_XHCI_DWC3=y
  32 +CONFIG_DM_USB=y
32 33 CONFIG_USB_STORAGE=y
configs/ls1043aqds_lpuart_defconfig
Diff comments   View file @ 711b534
... ... @@ -4,7 +4,8 @@
4 4 CONFIG_FIT=y
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
  7 +CONFIG_SYS_EXTRA_OPTIONS="LPUART"
  8 +CONFIG_SYS_FSL_DDR4=y
8 9 CONFIG_BOOTDELAY=10
9 10 CONFIG_HUSH_PARSER=y
10 11 CONFIG_CMD_BOOTZ=y
... ... @@ -30,5 +31,6 @@
30 31 CONFIG_USB=y
31 32 CONFIG_USB_XHCI_HCD=y
32 33 CONFIG_USB_XHCI_DWC3=y
  34 +CONFIG_DM_USB=y
33 35 CONFIG_USB_STORAGE=y
configs/ls1043aqds_nand_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,7 +12,8 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_OF_BOARD_SETUP=y
15   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
  15 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
  16 +CONFIG_SYS_FSL_DDR4=y
16 17 CONFIG_NAND_BOOT=y
17 18 CONFIG_BOOTDELAY=10
18 19 CONFIG_SPL=y
... ... @@ -40,5 +41,6 @@
40 41 CONFIG_USB=y
41 42 CONFIG_USB_XHCI_HCD=y
42 43 CONFIG_USB_XHCI_DWC3=y
  44 +CONFIG_DM_USB=y
43 45 CONFIG_USB_STORAGE=y
configs/ls1043aqds_nor_ddr3_defconfig
Diff comments   View file @ 711b534
... ... @@ -23,10 +23,12 @@
23 23 CONFIG_OF_CONTROL=y
24 24 CONFIG_DM=y
25 25 CONFIG_SPI_FLASH=y
  26 +CONFIG_SYS_FSL_DDR3=y
26 27 CONFIG_SYS_NS16550=y
27 28 CONFIG_DM_SPI=y
28 29 CONFIG_USB=y
29 30 CONFIG_USB_XHCI_HCD=y
30 31 CONFIG_USB_XHCI_DWC3=y
  32 +CONFIG_DM_USB=y
31 33 CONFIG_USB_STORAGE=y
configs/ls1043aqds_qspi_defconfig
Diff comments   View file @ 711b534
... ... @@ -4,7 +4,8 @@
4 4 CONFIG_FIT=y
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
  7 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
  8 +CONFIG_SYS_FSL_DDR4=y
8 9 CONFIG_QSPI_BOOT=y
9 10 CONFIG_BOOTDELAY=10
10 11 CONFIG_HUSH_PARSER=y
... ... @@ -31,5 +32,6 @@
31 32 CONFIG_USB=y
32 33 CONFIG_USB_XHCI_HCD=y
33 34 CONFIG_USB_XHCI_DWC3=y
  35 +CONFIG_DM_USB=y
34 36 CONFIG_USB_STORAGE=y
configs/ls1043aqds_sdcard_ifc_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,7 +12,8 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_OF_BOARD_SETUP=y
15   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
  15 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
  16 +CONFIG_SYS_FSL_DDR4=y
16 17 CONFIG_SD_BOOT=y
17 18 CONFIG_BOOTDELAY=10
18 19 CONFIG_SPL=y
... ... @@ -40,5 +41,6 @@
40 41 CONFIG_USB=y
41 42 CONFIG_USB_XHCI_HCD=y
42 43 CONFIG_USB_XHCI_DWC3=y
  44 +CONFIG_DM_USB=y
43 45 CONFIG_USB_STORAGE=y
configs/ls1043aqds_sdcard_qspi_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,7 +12,8 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_OF_BOARD_SETUP=y
15   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
  15 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
  16 +CONFIG_SYS_FSL_DDR4=y
16 17 CONFIG_SD_BOOT=y
17 18 CONFIG_BOOTDELAY=10
18 19 CONFIG_SPL=y
... ... @@ -41,5 +42,6 @@
41 42 CONFIG_USB=y
42 43 CONFIG_USB_XHCI_HCD=y
43 44 CONFIG_USB_XHCI_DWC3=y
  45 +CONFIG_DM_USB=y
44 46 CONFIG_USB_STORAGE=y
configs/ls1043ardb_SECURE_BOOT_defconfig
Diff comments   View file @ 711b534
... ... @@ -4,7 +4,8 @@
4 4 CONFIG_FIT=y
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
  7 +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
  8 +CONFIG_SYS_FSL_DDR4=y
8 9 CONFIG_BOOTDELAY=10
9 10 CONFIG_HUSH_PARSER=y
10 11 CONFIG_CMD_MMC=y
... ... @@ -25,6 +26,7 @@
25 26 CONFIG_USB=y
26 27 CONFIG_USB_XHCI_HCD=y
27 28 CONFIG_USB_XHCI_DWC3=y
  29 +CONFIG_DM_USB=y
28 30 CONFIG_USB_STORAGE=y
29 31 CONFIG_RSA=y
30 32 CONFIG_SPL_RSA=y
configs/ls1043ardb_defconfig
Diff comments   View file @ 711b534
... ... @@ -4,7 +4,7 @@
4 4 CONFIG_FIT=y
5 5 CONFIG_FIT_VERBOSE=y
6 6 CONFIG_OF_BOARD_SETUP=y
7   -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
  7 +CONFIG_SYS_FSL_DDR4=y
8 8 CONFIG_BOOTDELAY=10
9 9 CONFIG_HUSH_PARSER=y
10 10 CONFIG_CMD_MMC=y
... ... @@ -25,5 +25,6 @@
25 25 CONFIG_USB=y
26 26 CONFIG_USB_XHCI_HCD=y
27 27 CONFIG_USB_XHCI_DWC3=y
  28 +CONFIG_DM_USB=y
28 29 CONFIG_USB_STORAGE=y
configs/ls1043ardb_nand_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,7 +12,8 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_OF_BOARD_SETUP=y
15   -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
  15 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
  16 +CONFIG_SYS_FSL_DDR4=y
16 17 CONFIG_NAND_BOOT=y
17 18 CONFIG_BOOTDELAY=10
18 19 CONFIG_SPL=y
... ... @@ -36,5 +37,6 @@
36 37 CONFIG_USB=y
37 38 CONFIG_USB_XHCI_HCD=y
38 39 CONFIG_USB_XHCI_DWC3=y
  40 +CONFIG_DM_USB=y
39 41 CONFIG_USB_STORAGE=y
configs/ls1043ardb_sdcard_defconfig
Diff comments   View file @ 711b534
... ... @@ -12,7 +12,8 @@
12 12 CONFIG_FIT=y
13 13 CONFIG_FIT_VERBOSE=y
14 14 CONFIG_OF_BOARD_SETUP=y
15   -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
  15 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
  16 +CONFIG_SYS_FSL_DDR4=y
16 17 CONFIG_SD_BOOT=y
17 18 CONFIG_BOOTDELAY=10
18 19 CONFIG_SPL=y
... ... @@ -36,5 +37,6 @@
36 37 CONFIG_USB=y
37 38 CONFIG_USB_XHCI_HCD=y
38 39 CONFIG_USB_XHCI_DWC3=y
  40 +CONFIG_DM_USB=y
39 41 CONFIG_USB_STORAGE=y
configs/ls2080aqds_SECURE_BOOT_defconfig
Diff comments   View file @ 711b534
... ... @@ -33,6 +33,7 @@
33 33 CONFIG_USB=y
34 34 CONFIG_USB_XHCI_HCD=y
35 35 CONFIG_USB_XHCI_DWC3=y
  36 +CONFIG_DM_USB=y
36 37 CONFIG_USB_STORAGE=y
37 38 CONFIG_RSA=y
38 39 CONFIG_SPL_RSA=y
configs/ls2080aqds_defconfig
Diff comments   View file @ 711b534
... ... @@ -33,6 +33,7 @@
33 33 CONFIG_USB=y
34 34 CONFIG_USB_XHCI_HCD=y
35 35 CONFIG_USB_XHCI_DWC3=y
  36 +CONFIG_DM_USB=y
36 37 CONFIG_USB_STORAGE=y
37 38 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/ls2080aqds_nand_defconfig
Diff comments   View file @ 711b534
... ... @@ -42,6 +42,7 @@
42 42 CONFIG_USB=y
43 43 CONFIG_USB_XHCI_HCD=y
44 44 CONFIG_USB_XHCI_DWC3=y
  45 +CONFIG_DM_USB=y
45 46 CONFIG_USB_STORAGE=y
46 47 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/ls2080aqds_qspi_defconfig
Diff comments   View file @ 711b534
... ... @@ -34,6 +34,7 @@
34 34 CONFIG_USB=y
35 35 CONFIG_USB_XHCI_HCD=y
36 36 CONFIG_USB_XHCI_DWC3=y
  37 +CONFIG_DM_USB=y
37 38 CONFIG_USB_STORAGE=y
38 39 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/ls2080ardb_SECURE_BOOT_defconfig
Diff comments   View file @ 711b534
... ... @@ -33,6 +33,7 @@
33 33 CONFIG_USB=y
34 34 CONFIG_USB_XHCI_HCD=y
35 35 CONFIG_USB_XHCI_DWC3=y
  36 +CONFIG_DM_USB=y
36 37 CONFIG_USB_STORAGE=y
37 38 CONFIG_RSA=y
38 39 CONFIG_SPL_RSA=y
configs/ls2080ardb_defconfig
Diff comments   View file @ 711b534
... ... @@ -33,6 +33,7 @@
33 33 CONFIG_USB=y
34 34 CONFIG_USB_XHCI_HCD=y
35 35 CONFIG_USB_XHCI_DWC3=y
  36 +CONFIG_DM_USB=y
36 37 CONFIG_USB_STORAGE=y
37 38 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/ls2080ardb_nand_defconfig
Diff comments   View file @ 711b534
1 1 CONFIG_ARM=y
2 2 CONFIG_TARGET_LS2080ARDB=y
  3 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
3 4 CONFIG_SPL_LIBCOMMON_SUPPORT=y
4 5 CONFIG_SPL_LIBGENERIC_SUPPORT=y
5 6 CONFIG_SPL_I2C_SUPPORT=y
6 7  
7 8  
... ... @@ -27,13 +28,16 @@
27 28 CONFIG_CMD_CACHE=y
28 29 CONFIG_CMD_EXT2=y
29 30 CONFIG_CMD_FAT=y
  31 +CONFIG_OF_CONTROL=y
30 32 CONFIG_NET_RANDOM_ETHADDR=y
31 33 CONFIG_NETDEVICES=y
32 34 CONFIG_E1000=y
33 35 CONFIG_SYS_NS16550=y
  36 +CONFIG_DM=y
34 37 CONFIG_USB=y
35 38 CONFIG_USB_XHCI_HCD=y
36 39 CONFIG_USB_XHCI_DWC3=y
  40 +CONFIG_DM_USB=y
37 41 CONFIG_USB_STORAGE=y
38 42 CONFIG_OF_LIBFDT=y
39 43 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
drivers/misc/fsl_sec_mon.c
Diff comments   View file @ 711b534
... ... @@ -7,141 +7,159 @@
7 7 #include <common.h>
8 8 #include <fsl_sec_mon.h>
9 9  
10   -int change_sec_mon_state(u32 initial_state, u32 final_state)
  10 +static u32 get_sec_mon_state(void)
11 11 {
12 12 struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
13 13 (CONFIG_SYS_SEC_MON_ADDR);
14   - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
  14 + return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK;
  15 +}
  16 +
  17 +static int set_sec_mon_state_non_sec(void)
  18 +{
  19 + u32 sts;
15 20 int timeout = 10;
  21 + struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
  22 + (CONFIG_SYS_SEC_MON_ADDR);
16 23  
17   - if ((sts & HPSR_SSM_ST_MASK) != initial_state)
18   - return -1;
  24 + sts = get_sec_mon_state();
19 25  
20   - if (initial_state == HPSR_SSM_ST_TRUST) {
21   - switch (final_state) {
22   - case HPSR_SSM_ST_NON_SECURE:
23   - printf("SEC_MON state transitioning to Soft Fail.\n");
24   - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
  26 + switch (sts) {
  27 + /*
  28 + * If initial state is check or Non-Secure, then set the Software
  29 + * Security Violation Bit and transition to Non-Secure State.
  30 + */
  31 + case HPSR_SSM_ST_CHECK:
  32 + printf("SEC_MON state transitioning to Non Secure.\n");
  33 + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
25 34  
26   - /*
27   - * poll till SEC_MON is in
28   - * Soft Fail state
29   - */
30   - while (((sts & HPSR_SSM_ST_MASK) !=
31   - HPSR_SSM_ST_SOFT_FAIL)) {
32   - while (timeout) {
33   - sts = sec_mon_in32
34   - (&sec_mon_regs->hp_stat);
  35 + /* polling loop till SEC_MON is in Non Secure state */
  36 + while (timeout) {
  37 + sts = get_sec_mon_state();
35 38  
36   - if ((sts & HPSR_SSM_ST_MASK) ==
37   - HPSR_SSM_ST_SOFT_FAIL)
38   - break;
  39 + if ((sts & HPSR_SSM_ST_MASK) ==
  40 + HPSR_SSM_ST_NON_SECURE)
  41 + break;
39 42  
40   - udelay(10);
41   - timeout--;
42   - }
43   - }
  43 + udelay(10);
  44 + timeout--;
  45 + }
44 46  
45   - if (timeout == 0) {
46   - printf("SEC_MON state transition timeout.\n");
47   - return -1;
48   - }
  47 + if (timeout == 0) {
  48 + printf("SEC_MON state transition timeout.\n");
  49 + return -1;
  50 + }
  51 + break;
49 52  
50   - timeout = 10;
  53 + /*
  54 + * If initial state is Trusted, Secure or Soft-Fail, then first set
  55 + * the Software Security Violation Bit and transition to Soft-Fail
  56 + * State.
  57 + */
  58 + case HPSR_SSM_ST_TRUST:
  59 + case HPSR_SSM_ST_SECURE:
  60 + case HPSR_SSM_ST_SOFT_FAIL:
  61 + printf("SEC_MON state transitioning to Soft Fail.\n");
  62 + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV);
51 63  
52   - printf("SEC_MON state transitioning to Non Secure.\n");
53   - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
  64 + /* polling loop till SEC_MON is in Soft-Fail state */
  65 + while (timeout) {
  66 + sts = get_sec_mon_state();
54 67  
55   - /*
56   - * poll till SEC_MON is in
57   - * Non Secure state
58   - */
59   - while (((sts & HPSR_SSM_ST_MASK) !=
60   - HPSR_SSM_ST_NON_SECURE)) {
61   - while (timeout) {
62   - sts = sec_mon_in32
63   - (&sec_mon_regs->hp_stat);
  68 + if ((sts & HPSR_SSM_ST_MASK) ==
  69 + HPSR_SSM_ST_SOFT_FAIL)
  70 + break;
64 71  
65   - if ((sts & HPSR_SSM_ST_MASK) ==
66   - HPSR_SSM_ST_NON_SECURE)
67   - break;
  72 + udelay(10);
  73 + timeout--;
  74 + }
68 75  
69   - udelay(10);
70   - timeout--;
71   - }
72   - }
  76 + if (timeout == 0) {
  77 + printf("SEC_MON state transition timeout.\n");
  78 + return -1;
  79 + }
73 80  
74   - if (timeout == 0) {
75   - printf("SEC_MON state transition timeout.\n");
76   - return -1;
77   - }
78   - break;
79   - case HPSR_SSM_ST_SOFT_FAIL:
80   - printf("SEC_MON state transitioning to Soft Fail.\n");
81   - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
  81 + timeout = 10;
82 82  
83   - /*
84   - * polling loop till SEC_MON is in
85   - * Soft Fail state
86   - */
87   - while (((sts & HPSR_SSM_ST_MASK) !=
88   - HPSR_SSM_ST_SOFT_FAIL)) {
89   - while (timeout) {
90   - sts = sec_mon_in32
91   - (&sec_mon_regs->hp_stat);
  83 + /*
  84 + * If SSM Soft Fail to Non-Secure State Transition
  85 + * disable is not set, then set SSM_ST bit and
  86 + * transition to Non-Secure State.
  87 + */
  88 + if ((sec_mon_in32(&sec_mon_regs->hp_com) &
  89 + HPCOMR_SSM_SFNS_DIS) == 0) {
  90 + printf("SEC_MON state transitioning to Non Secure.\n");
  91 + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST);
92 92  
93   - if ((sts & HPSR_SSM_ST_MASK) ==
94   - HPSR_SSM_ST_SOFT_FAIL)
95   - break;
  93 + /* polling loop till SEC_MON is in Non Secure*/
  94 + while (timeout) {
  95 + sts = get_sec_mon_state();
96 96  
97   - udelay(10);
98   - timeout--;
99   - }
  97 + if ((sts & HPSR_SSM_ST_MASK) ==
  98 + HPSR_SSM_ST_NON_SECURE)
  99 + break;
  100 +
  101 + udelay(10);
  102 + timeout--;
100 103 }
101 104  
102 105 if (timeout == 0) {
103 106 printf("SEC_MON state transition timeout.\n");
104 107 return -1;
105 108 }
106   - break;
107   - default:
108   - return -1;
109 109 }
110   - } else if (initial_state == HPSR_SSM_ST_NON_SECURE) {
111   - switch (final_state) {
112   - case HPSR_SSM_ST_SOFT_FAIL:
113   - printf("SEC_MON state transitioning to Soft Fail.\n");
114   - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
  110 + break;
  111 + default:
  112 + printf("SEC_MON already in Non Secure state.\n");
  113 + return 0;
  114 + }
  115 + return 0;
  116 +}
115 117  
116   - /*
117   - * polling loop till SEC_MON is in
118   - * Soft Fail state
119   - */
120   - while (((sts & HPSR_SSM_ST_MASK) !=
121   - HPSR_SSM_ST_SOFT_FAIL)) {
122   - while (timeout) {
123   - sts = sec_mon_in32
124   - (&sec_mon_regs->hp_stat);
  118 +static int set_sec_mon_state_soft_fail(void)
  119 +{
  120 + u32 sts;
  121 + int timeout = 10;
  122 + struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
  123 + (CONFIG_SYS_SEC_MON_ADDR);
125 124  
126   - if ((sts & HPSR_SSM_ST_MASK) ==
127   - HPSR_SSM_ST_SOFT_FAIL)
128   - break;
  125 + printf("SEC_MON state transitioning to Soft Fail.\n");
  126 + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
129 127  
130   - udelay(10);
131   - timeout--;
132   - }
133   - }
  128 + /* polling loop till SEC_MON is in Soft-Fail state */
  129 + while (timeout) {
  130 + sts = get_sec_mon_state();
134 131  
135   - if (timeout == 0) {
136   - printf("SEC_MON state transition timeout.\n");
137   - return -1;
138   - }
  132 + if ((sts & HPSR_SSM_ST_MASK) ==
  133 + HPSR_SSM_ST_SOFT_FAIL)
139 134 break;
140   - default:
141   - return -1;
142   - }
  135 +
  136 + udelay(10);
  137 + timeout--;
143 138 }
144 139  
  140 + if (timeout == 0) {
  141 + printf("SEC_MON state transition timeout.\n");
  142 + return -1;
  143 + }
145 144 return 0;
  145 +}
  146 +
  147 +int set_sec_mon_state(u32 state)
  148 +{
  149 + int ret = -1;
  150 +
  151 + switch (state) {
  152 + case HPSR_SSM_ST_NON_SECURE:
  153 + ret = set_sec_mon_state_non_sec();
  154 + break;
  155 + case HPSR_SSM_ST_SOFT_FAIL:
  156 + ret = set_sec_mon_state_soft_fail();
  157 + break;
  158 + default:
  159 + printf("SEC_MON state transition not supported.\n");
  160 + return 0;
  161 + }
  162 +
  163 + return ret;
146 164 }
drivers/spi/fsl_qspi.c
Diff comments   View file @ 711b534
... ... @@ -865,6 +865,7 @@
865 865 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
866 866 unsigned int max_hz, unsigned int mode)
867 867 {
  868 + u32 mcr_val;
868 869 struct fsl_qspi *qspi;
869 870 struct fsl_qspi_regs *regs;
870 871 u32 total_size;
871 872  
... ... @@ -896,8 +897,10 @@
896 897  
897 898 qspi->slave.max_write_size = TX_BUFFER_SIZE;
898 899  
  900 + mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
899 901 qspi_write32(qspi->priv.flags, &regs->mcr,
900   - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
  902 + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
  903 + (mcr_val & QSPI_MCR_END_CFD_MASK));
901 904  
902 905 qspi_cfg_smpr(&qspi->priv,
903 906 ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
... ... @@ -975,6 +978,7 @@
975 978  
976 979 static int fsl_qspi_probe(struct udevice *bus)
977 980 {
  981 + u32 mcr_val;
978 982 u32 amba_size_per_chip;
979 983 struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
980 984 struct fsl_qspi_priv *priv = dev_get_priv(bus);
981 985  
... ... @@ -999,8 +1003,10 @@
999 1003 priv->flash_num = plat->flash_num;
1000 1004 priv->num_chipselect = plat->num_chipselect;
1001 1005  
  1006 + mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
1002 1007 qspi_write32(priv->flags, &priv->regs->mcr,
1003   - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
  1008 + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
  1009 + (mcr_val & QSPI_MCR_END_CFD_MASK));
1004 1010  
1005 1011 qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1006 1012 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
include/configs/ls1012a_common.h
Diff comments   View file @ 711b534
... ... @@ -8,11 +8,8 @@
8 8 #define __LS1012A_COMMON_H
9 9  
10 10 #define CONFIG_FSL_LAYERSCAPE
11   -#define CONFIG_FSL_LSCH2
12 11 #define CONFIG_GICV2
13 12  
14   -#define CONFIG_SYS_HAS_SERDES
15   -
16 13 #include <asm/arch/config.h>
17 14 #define CONFIG_SYS_NO_FLASH
18 15  
19 16  
20 17  
21 18  
... ... @@ -103,19 +100,14 @@
103 100  
104 101 /* Initial environment variables */
105 102 #define CONFIG_EXTRA_ENV_SETTINGS \
106   - "initrd_high=0xffffffff\0" \
107 103 "verify=no\0" \
108   - "hwconfig=fsl_ddr:bank_intlv=auto\0" \
109 104 "loadaddr=0x80100000\0" \
110 105 "kernel_addr=0x100000\0" \
111   - "ramdisk_addr=0x800000\0" \
112   - "ramdisk_size=0x2000000\0" \
113 106 "fdt_high=0xffffffffffffffff\0" \
114 107 "initrd_high=0xffffffffffffffff\0" \
115 108 "kernel_start=0xa00000\0" \
116 109 "kernel_load=0xa0000000\0" \
117 110 "kernel_size=0x2800000\0" \
118   - "console=ttyAMA0,38400n8\0"
119 111  
120 112 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
121 113 "earlycon=uart8250,mmio,0x21c0500"
include/configs/ls1012afrdm.h
Diff comments   View file @ 711b534
... ... @@ -20,6 +20,17 @@
20 20 #define CONFIG_SYS_MEMTEST_START 0x80000000
21 21 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
22 22  
  23 +#undef CONFIG_EXTRA_ENV_SETTINGS
  24 +#define CONFIG_EXTRA_ENV_SETTINGS \
  25 + "verify=no\0" \
  26 + "loadaddr=0x80100000\0" \
  27 + "kernel_addr=0x100000\0" \
  28 + "fdt_high=0xffffffffffffffff\0" \
  29 + "initrd_high=0xffffffffffffffff\0" \
  30 + "kernel_start=0xa00000\0" \
  31 + "kernel_load=0x96000000\0" \
  32 + "kernel_size=0x2800000\0"
  33 +
23 34 /*
24 35 * USB
25 36 */
include/configs/ls1021aqds.h
Diff comments   View file @ 711b534
... ... @@ -125,7 +125,6 @@
125 125  
126 126 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
127 127 #ifndef CONFIG_SYS_FSL_DDR4
128   -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
129 128 #define CONFIG_SYS_DDR_RAW_TIMING
130 129 #endif
131 130 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
... ... @@ -140,8 +139,6 @@
140 139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
141 140 #endif
142 141  
143   -#define CONFIG_SYS_HAS_SERDES
144   -
145 142 #define CONFIG_FSL_CAAM /* Enable CAAM */
146 143  
147 144 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
... ... @@ -541,8 +538,6 @@
541 538 #define CONFIG_CMDLINE_TAG
542 539 #define CONFIG_CMDLINE_EDITING
543 540  
544   -#define CONFIG_ARMV7_NONSEC
545   -#define CONFIG_ARMV7_VIRT
546 541 #define CONFIG_PEN_ADDR_BIG_ENDIAN
547 542 #define CONFIG_LAYERSCAPE_NS_ACCESS
548 543 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
include/configs/ls1021atwr.h
Diff comments   View file @ 711b534
... ... @@ -167,8 +167,6 @@
167 167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
168 168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
169 169  
170   -#define CONFIG_SYS_HAS_SERDES
171   -
172 170 #define CONFIG_FSL_CAAM /* Enable CAAM */
173 171  
174 172 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
... ... @@ -413,8 +411,6 @@
413 411 #define CONFIG_CMDLINE_TAG
414 412 #define CONFIG_CMDLINE_EDITING
415 413  
416   -#define CONFIG_ARMV7_NONSEC
417   -#define CONFIG_ARMV7_VIRT
418 414 #define CONFIG_PEN_ADDR_BIG_ENDIAN
419 415 #define CONFIG_LAYERSCAPE_NS_ACCESS
420 416 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
include/configs/ls1043a_common.h
Diff comments   View file @ 711b534
... ... @@ -9,16 +9,12 @@
9 9  
10 10 #define CONFIG_REMAKE_ELF
11 11 #define CONFIG_FSL_LAYERSCAPE
12   -#define CONFIG_FSL_LSCH2
13 12 #define CONFIG_LS1043A
14 13 #define CONFIG_MP
15 14 #define CONFIG_SYS_FSL_CLK
16 15 #define CONFIG_GICV2
17 16  
18 17 #include <asm/arch/config.h>
19   -#ifdef CONFIG_SYS_FSL_SRDS_1
20   -#define CONFIG_SYS_HAS_SERDES
21   -#endif
22 18  
23 19 /* Link Definitions */
24 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
... ... @@ -27,10 +23,6 @@
27 23  
28 24 #define CONFIG_SKIP_LOWLEVEL_INIT
29 25 #define CONFIG_BOARD_EARLY_INIT_F 1
30   -
31   -#ifndef CONFIG_SYS_FSL_DDR4
32   -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
33   -#endif
34 26  
35 27 #define CONFIG_VERY_BIG_RAM
36 28 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
include/configs/ls1043aqds.h
Diff comments   View file @ 711b534
... ... @@ -39,17 +39,12 @@
39 39 #define CONFIG_SYS_SPD_BUS_NUM 0
40 40  
41 41 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
42   -#ifndef CONFIG_SYS_FSL_DDR4
43   -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
44   -#endif
45 42  
46 43 #define CONFIG_DDR_ECC
47 44 #ifdef CONFIG_DDR_ECC
48 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
49 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
50 47 #endif
51   -
52   -#define CONFIG_SYS_HAS_SERDES
53 48  
54 49 #ifdef CONFIG_SYS_DPAA_FMAN
55 50 #define CONFIG_FMAN_ENET
include/configs/ls1046a_common.h
Diff comments   View file @ 711b534
... ... @@ -9,15 +9,11 @@
9 9  
10 10 #define CONFIG_REMAKE_ELF
11 11 #define CONFIG_FSL_LAYERSCAPE
12   -#define CONFIG_FSL_LSCH2
13 12 #define CONFIG_MP
14 13 #define CONFIG_SYS_FSL_CLK
15 14 #define CONFIG_GICV2
16 15  
17 16 #include <asm/arch/config.h>
18   -#ifdef CONFIG_SYS_FSL_SRDS_1
19   -#define CONFIG_SYS_HAS_SERDES
20   -#endif
21 17  
22 18 /* Link Definitions */
23 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
include/configs/ls1046aqds.h
Diff comments   View file @ 711b534
... ... @@ -46,8 +46,6 @@
46 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 47 #endif
48 48  
49   -#define CONFIG_SYS_HAS_SERDES
50   -
51 49 /* DSPI */
52 50 #ifdef CONFIG_FSL_DSPI
53 51 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
include/configs/ls2080a_common.h
Diff comments   View file @ 711b534
... ... @@ -9,16 +9,12 @@
9 9  
10 10 #define CONFIG_REMAKE_ELF
11 11 #define CONFIG_FSL_LAYERSCAPE
12   -#define CONFIG_FSL_LSCH3
13 12 #define CONFIG_MP
14 13 #define CONFIG_GICV3
15 14 #define CONFIG_FSL_TZPC_BP147
16 15  
17 16 #include <asm/arch/ls2080a_stream_id.h>
18 17 #include <asm/arch/config.h>
19   -#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
20   -#define CONFIG_SYS_HAS_SERDES
21   -#endif
22 18  
23 19 /* Link Definitions */
24 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
... ... @@ -50,7 +46,6 @@
50 46 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
51 47 #endif
52 48 #ifndef CONFIG_SYS_FSL_DDR4
53   -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
54 49 #define CONFIG_SYS_DDR_RAW_TIMING
55 50 #endif
56 51  
include/fsl_sec_mon.h
Diff comments   View file @ 711b534
... ... @@ -34,13 +34,16 @@
34 34 u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
35 35 };
36 36  
37   -#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
38   -#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
39   -#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
  37 +#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
  38 +#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
  39 +#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
  40 +#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
  41 +#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
40 42 #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
41 43 #define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
42 44 #define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
43 45 #define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
  46 +#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */
44 47 #define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
45 48  
46 49 /*
... ... @@ -53,7 +56,8 @@
53 56 SEC_MON_SW_SV,
54 57 };
55 58  
56   -int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
  59 +/* Transition SEC_MON state */
  60 +int set_sec_mon_state(u32 state);
57 61  
58 62 #endif /* __FSL_SEC_MON_H */
... ... @@ -78,10 +78,17 @@
78 78 u32 fsl_uid; /* 0xB0 FSL Unique ID */
79 79 };
80 80 #endif
  81 +
81 82 #define ITS_MASK 0x00000004
82 83 #define ITS_BIT 2
83   -#define OSPR_KEY_REVOC_SHIFT 13
84   -#define OSPR_KEY_REVOC_MASK 0x0000e000
  84 +
  85 +#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
  86 +#define OSPR_KEY_REVOC_SHIFT 9
  87 +#define OSPR_KEY_REVOC_MASK 0x0000fe00
  88 +#else
  89 +#define OSPR_KEY_REVOC_SHIFT 13
  90 +#define OSPR_KEY_REVOC_MASK 0x0000e000
  91 +#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
85 92  
86 93 #endif
scripts/config_whitelist.txt
Diff comments   View file @ 711b534
... ... @@ -1294,8 +1294,6 @@
1294 1294 CONFIG_FSL_LAYERSCAPE
1295 1295 CONFIG_FSL_LBC
1296 1296 CONFIG_FSL_LINFLEXUART
1297   -CONFIG_FSL_LSCH2
1298   -CONFIG_FSL_LSCH3
1299 1297 CONFIG_FSL_LS_PPA
1300 1298 CONFIG_FSL_MC9SDZ60
1301 1299 CONFIG_FSL_MC_ENET