Commit 71bd860cce4493c5def07804723661e75271052b
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f6970d0c54
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mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c
commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Showing 1 changed file with 18 additions and 18 deletions Side-by-side Diff
arch/powerpc/cpu/mpc83xx/cpu_init.c
| ... | ... | @@ -65,16 +65,16 @@ |
| 65 | 65 | { |
| 66 | 66 | __be32 acr_mask = |
| 67 | 67 | #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ |
| 68 | - (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | | |
| 68 | + ACR_PIPE_DEP | | |
| 69 | 69 | #endif |
| 70 | 70 | #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ |
| 71 | - (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | | |
| 71 | + ACR_RPTCNT | | |
| 72 | 72 | #endif |
| 73 | 73 | #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ |
| 74 | - (ACR_APARK << ACR_APARK_SHIFT) | | |
| 74 | + ACR_APARK | | |
| 75 | 75 | #endif |
| 76 | 76 | #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ |
| 77 | - (ACR_PARKM << ACR_PARKM_SHIFT) | | |
| 77 | + ACR_PARKM | | |
| 78 | 78 | #endif |
| 79 | 79 | 0; |
| 80 | 80 | __be32 acr_val = |
| 81 | 81 | |
| 82 | 82 | |
| 83 | 83 | |
| ... | ... | @@ -93,16 +93,16 @@ |
| 93 | 93 | 0; |
| 94 | 94 | __be32 spcr_mask = |
| 95 | 95 | #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ |
| 96 | - (SPCR_OPT << SPCR_OPT_SHIFT) | | |
| 96 | + SPCR_OPT | | |
| 97 | 97 | #endif |
| 98 | 98 | #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ |
| 99 | - (SPCR_TSECEP << SPCR_TSECEP_SHIFT) | | |
| 99 | + SPCR_TSECEP | | |
| 100 | 100 | #endif |
| 101 | 101 | #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ |
| 102 | - (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | | |
| 102 | + SPCR_TSEC1EP | | |
| 103 | 103 | #endif |
| 104 | 104 | #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ |
| 105 | - (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | | |
| 105 | + SPCR_TSEC2EP | | |
| 106 | 106 | #endif |
| 107 | 107 | 0; |
| 108 | 108 | __be32 spcr_val = |
| 109 | 109 | |
| 110 | 110 | |
| 111 | 111 | |
| 112 | 112 | |
| 113 | 113 | |
| 114 | 114 | |
| 115 | 115 | |
| 116 | 116 | |
| 117 | 117 | |
| ... | ... | @@ -121,34 +121,34 @@ |
| 121 | 121 | 0; |
| 122 | 122 | __be32 sccr_mask = |
| 123 | 123 | #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ |
| 124 | - (SCCR_ENCCM << SCCR_ENCCM_SHIFT) | | |
| 124 | + SCCR_ENCCM | | |
| 125 | 125 | #endif |
| 126 | 126 | #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ |
| 127 | - (SCCR_PCICM << SCCR_PCICM_SHIFT) | | |
| 127 | + SCCR_PCICM | | |
| 128 | 128 | #endif |
| 129 | 129 | #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ |
| 130 | - (SCCR_TSECCM << SCCR_TSECCM_SHIFT) | | |
| 130 | + SCCR_TSECCM | | |
| 131 | 131 | #endif |
| 132 | 132 | #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ |
| 133 | - (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | | |
| 133 | + SCCR_TSEC1CM | | |
| 134 | 134 | #endif |
| 135 | 135 | #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ |
| 136 | - (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | | |
| 136 | + SCCR_TSEC2CM | | |
| 137 | 137 | #endif |
| 138 | 138 | #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ |
| 139 | - (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | | |
| 139 | + SCCR_TSEC1ON | | |
| 140 | 140 | #endif |
| 141 | 141 | #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ |
| 142 | - (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | | |
| 142 | + SCCR_TSEC2ON | | |
| 143 | 143 | #endif |
| 144 | 144 | #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ |
| 145 | - (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | | |
| 145 | + SCCR_USBMPHCM | | |
| 146 | 146 | #endif |
| 147 | 147 | #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ |
| 148 | - (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | | |
| 148 | + SCCR_USBDRCM | | |
| 149 | 149 | #endif |
| 150 | 150 | #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ |
| 151 | - (SCCR_SATACM << SCCR_SATACM_SHIFT) | | |
| 151 | + SCCR_SATACM | | |
| 152 | 152 | #endif |
| 153 | 153 | 0; |
| 154 | 154 | __be32 sccr_val = |