Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* Author: Fabio Estevam <fabio.estevam@freescale.com>

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* Author: Fabio Estevam <fabio.estevam@freescale.com>

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*/

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*/

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#include <asm/arch/clock.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/iomux.h>

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#include <asm/arch/iomux.h>

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#include <asm/arch/mx6-pins.h>

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#include <asm/arch/mx6-pins.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <asm/gpio.h>

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#include <asm/gpio.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/imx-common/video.h>

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#include <asm/imx-common/video.h>

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#include <mmc.h>

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#include <mmc.h>

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#include <fsl_esdhc.h>

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#include <fsl_esdhc.h>

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#include <miiphy.h>

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#include <miiphy.h>

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#include <netdev.h>

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#include <netdev.h>

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#include <asm/arch/mxc_hdmi.h>

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#include <asm/arch/mxc_hdmi.h>

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#include <asm/arch/crm_regs.h>

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#include <asm/arch/crm_regs.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/arch/sys_proto.h>

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#include <asm/arch/sys_proto.h>

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#include <i2c.h>

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#include <i2c.h>

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#include <power/pmic.h>

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#include <power/pmic.h>

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#include <power/pfuze100_pmic.h>

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#include <power/pfuze100_pmic.h>

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#include "../common/pfuze.h"

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#include "../common/pfuze.h"

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#include <asm/arch/mx6-ddr.h>

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#include <asm/arch/mx6-ddr.h>

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#include <usb.h>

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#include <usb.h>

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#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

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#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

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#include <lcd.h>

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#include <lcd.h>

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#include <mxc_epdc_fb.h>

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#include <mxc_epdc_fb.h>

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#endif

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#endif

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#ifdef CONFIG_CMD_SATA

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#ifdef CONFIG_CMD_SATA

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#include <asm/imx-common/sata.h>

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#include <asm/imx-common/sata.h>

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#endif

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#endif

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#ifdef CONFIG_FSL_FASTBOOT

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#ifdef CONFIG_FSL_FASTBOOT

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#include <fsl_fastboot.h>

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#include <fsl_fastboot.h>

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#ifdef CONFIG_ANDROID_RECOVERY

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#ifdef CONFIG_ANDROID_RECOVERY

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#include <recovery.h>

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#include <recovery.h>

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#endif

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#endif

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#endif /*CONFIG_FSL_FASTBOOT*/

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#endif /*CONFIG_FSL_FASTBOOT*/

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DECLARE_GLOBAL_DATA_PTR;

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DECLARE_GLOBAL_DATA_PTR;

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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \

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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \

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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \

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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \

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PAD_CTL_ODE | PAD_CTL_SRE_FAST)

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PAD_CTL_ODE | PAD_CTL_SRE_FAST)

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#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \

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#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \

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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \

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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \

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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \

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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \

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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define I2C_PMIC 1

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#define I2C_PMIC 1

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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)

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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)

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#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)

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#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)

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#define KEY_VOL_UP IMX_GPIO_NR(1, 4)

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#define KEY_VOL_UP IMX_GPIO_NR(1, 4)

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int dram_init(void)

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int dram_init(void)

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{

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{

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gd->ram_size = imx_ddr_size();

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gd->ram_size = imx_ddr_size();

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return 0;

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return 0;

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}

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}

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static iomux_v3_cfg_t const uart1_pads[] = {

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static iomux_v3_cfg_t const uart1_pads[] = {

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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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static iomux_v3_cfg_t const enet_pads[] = {

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static iomux_v3_cfg_t const enet_pads[] = {

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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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/* AR8031 PHY Reset */

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/* AR8031 PHY Reset */

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MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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static void setup_iomux_enet(void)

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static void fec_phy_reset(void)

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{

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{

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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

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/* Reset AR8031 PHY */

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/* Reset AR8031 PHY */

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gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");

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gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");

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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);

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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);

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mdelay(10);

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mdelay(10);

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gpio_set_value(IMX_GPIO_NR(1, 25), 1);

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gpio_set_value(IMX_GPIO_NR(1, 25), 1);

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udelay(100);

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udelay(100);

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}

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}

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static void setup_iomux_enet(void)

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{

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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

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fec_phy_reset();

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}

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static iomux_v3_cfg_t const usdhc2_pads[] = {

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static iomux_v3_cfg_t const usdhc2_pads[] = {

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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

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MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

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};

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};

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static iomux_v3_cfg_t const usdhc3_pads[] = {

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static iomux_v3_cfg_t const usdhc3_pads[] = {

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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

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MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

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};

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};

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static iomux_v3_cfg_t const usdhc4_pads[] = {

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static iomux_v3_cfg_t const usdhc4_pads[] = {

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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

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};

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};

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#ifdef CONFIG_MXC_SPI

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#ifdef CONFIG_MXC_SPI

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static iomux_v3_cfg_t const ecspi1_pads[] = {

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static iomux_v3_cfg_t const ecspi1_pads[] = {

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MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

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MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

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MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

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MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

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MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

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MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

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MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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static void setup_spi(void)

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static void setup_spi(void)

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{

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{

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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

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gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS");

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gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS");

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}

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}

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int board_spi_cs_gpio(unsigned bus, unsigned cs)

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int board_spi_cs_gpio(unsigned bus, unsigned cs)

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{

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{

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return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;

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return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;

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}

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}

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#endif

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#endif

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static iomux_v3_cfg_t const rgb_pads[] = {

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static iomux_v3_cfg_t const rgb_pads[] = {

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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),

191

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),

195

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),

192

MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),

196

MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),

193

MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),

197

MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),

194

MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),

198

MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),

195

MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),

199

MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),

196

MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),

200

MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),

197

MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),

201

MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),

198

MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),

202

MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),

199

MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),

203

MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),

200

MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),

204

MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),

201

MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),

205

MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),

202

MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),

206

MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),

203

MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),

207

MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),

204

MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),

208

MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),

205

MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),

209

MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),

206

MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),

210

MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),

207

MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),

211

MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),

208

MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),

212

MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),

209

MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),

213

MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),

210

MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),

214

MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),

211

MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),

215

MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),

212

MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),

216

MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),

213

MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),

217

MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),

214

MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),

218

MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),

215

MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),

219

MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),

216

MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),

220

MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),

217

};

221

};

218

222

219

static iomux_v3_cfg_t const bl_pads[] = {

223

static iomux_v3_cfg_t const bl_pads[] = {

220

MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),

224

MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),

221

};

225

};

222

226

223

static void enable_backlight(void)

227

static void enable_backlight(void)

224

{

228

{

225

imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));

229

imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));

226

gpio_request(DISP0_PWR_EN, "Display Power Enable");

230

gpio_request(DISP0_PWR_EN, "Display Power Enable");

227

gpio_direction_output(DISP0_PWR_EN, 1);

231

gpio_direction_output(DISP0_PWR_EN, 1);

228

}

232

}

229

233

230

static void enable_rgb(struct display_info_t const *dev)

234

static void enable_rgb(struct display_info_t const *dev)

231

{

235

{

232

imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));

236

imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));

233

enable_backlight();

237

enable_backlight();

234

}

238

}

235

239

236

static void enable_lvds(struct display_info_t const *dev)

240

static void enable_lvds(struct display_info_t const *dev)

237

{

241

{

238

enable_backlight();

242

enable_backlight();

239

}

243

}

240

244

241

#ifdef CONFIG_SYS_I2C

245

#ifdef CONFIG_SYS_I2C

242

static struct i2c_pads_info i2c_pad_info1 = {

246

static struct i2c_pads_info i2c_pad_info1 = {

243

.scl = {

247

.scl = {

244

.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,

248

.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,

245

.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,

249

.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,

246

.gp = IMX_GPIO_NR(4, 12)

250

.gp = IMX_GPIO_NR(4, 12)

247

},

251

},

248

.sda = {

252

.sda = {

249

.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,

253

.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,

250

.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,

254

.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,

251

.gp = IMX_GPIO_NR(4, 13)

255

.gp = IMX_GPIO_NR(4, 13)

252

}

256

}

253

};

257

};

254

#endif

258

#endif

255

259

256

#ifdef CONFIG_PCIE_IMX

260

#ifdef CONFIG_PCIE_IMX

257

iomux_v3_cfg_t const pcie_pads[] = {

261

iomux_v3_cfg_t const pcie_pads[] = {

258

MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */

262

MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */

259

MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */

263

MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */

260

};

264

};

261

265

262

static void setup_pcie(void)

266

static void setup_pcie(void)

263

{

267

{

264

imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));

268

imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));

265

gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");

269

gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");

266

gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");

270

gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");

267

}

271

}

268

#endif

272

#endif

269

273

270

iomux_v3_cfg_t const di0_pads[] = {

274

iomux_v3_cfg_t const di0_pads[] = {

271

MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */

275

MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */

272

MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */

276

MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */

273

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */

277

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */

274

};

278

};

275

279

276

static void setup_iomux_uart(void)

280

static void setup_iomux_uart(void)

277

{

281

{

278

imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));

282

imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));

279

}

283

}

280

284

281

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

285

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

282

static iomux_v3_cfg_t const epdc_enable_pads[] = {

286

static iomux_v3_cfg_t const epdc_enable_pads[] = {

283

MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

287

MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

284

MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

288

MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

285

MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

289

MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

286

MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

290

MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

287

MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

291

MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

288

MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

292

MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

289

MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

293

MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

290

MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

294

MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

291

MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

295

MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

292

MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

296

MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

293

MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

297

MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

294

MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

298

MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

295

MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),

299

MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),

296

MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

300

MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

297

MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

301

MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

298

MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

302

MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

299

MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

303

MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

300

MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

304

MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

301

MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

305

MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

302

MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

306

MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

303

};

307

};

304

308

305

static iomux_v3_cfg_t const epdc_disable_pads[] = {

309

static iomux_v3_cfg_t const epdc_disable_pads[] = {

306

MX6_PAD_EIM_A16__GPIO2_IO22,

310

MX6_PAD_EIM_A16__GPIO2_IO22,

307

MX6_PAD_EIM_DA10__GPIO3_IO10,

311

MX6_PAD_EIM_DA10__GPIO3_IO10,

308

MX6_PAD_EIM_DA12__GPIO3_IO12,

312

MX6_PAD_EIM_DA12__GPIO3_IO12,

309

MX6_PAD_EIM_DA11__GPIO3_IO11,

313

MX6_PAD_EIM_DA11__GPIO3_IO11,

310

MX6_PAD_EIM_LBA__GPIO2_IO27,

314

MX6_PAD_EIM_LBA__GPIO2_IO27,

311

MX6_PAD_EIM_EB2__GPIO2_IO30,

315

MX6_PAD_EIM_EB2__GPIO2_IO30,

312

MX6_PAD_EIM_CS0__GPIO2_IO23,

316

MX6_PAD_EIM_CS0__GPIO2_IO23,

313

MX6_PAD_EIM_RW__GPIO2_IO26,

317

MX6_PAD_EIM_RW__GPIO2_IO26,

314

MX6_PAD_EIM_A21__GPIO2_IO17,

318

MX6_PAD_EIM_A21__GPIO2_IO17,

315

MX6_PAD_EIM_A22__GPIO2_IO16,

319

MX6_PAD_EIM_A22__GPIO2_IO16,

316

MX6_PAD_EIM_A23__GPIO6_IO06,

320

MX6_PAD_EIM_A23__GPIO6_IO06,

317

MX6_PAD_EIM_A24__GPIO5_IO04,

321

MX6_PAD_EIM_A24__GPIO5_IO04,

318

MX6_PAD_EIM_D31__GPIO3_IO31,

322

MX6_PAD_EIM_D31__GPIO3_IO31,

319

MX6_PAD_EIM_D27__GPIO3_IO27,

323

MX6_PAD_EIM_D27__GPIO3_IO27,

320

MX6_PAD_EIM_DA1__GPIO3_IO01,

324

MX6_PAD_EIM_DA1__GPIO3_IO01,

321

MX6_PAD_EIM_EB1__GPIO2_IO29,

325

MX6_PAD_EIM_EB1__GPIO2_IO29,

322

MX6_PAD_EIM_DA2__GPIO3_IO02,

326

MX6_PAD_EIM_DA2__GPIO3_IO02,

323

MX6_PAD_EIM_DA4__GPIO3_IO04,

327

MX6_PAD_EIM_DA4__GPIO3_IO04,

324

MX6_PAD_EIM_DA5__GPIO3_IO05,

328

MX6_PAD_EIM_DA5__GPIO3_IO05,

325

MX6_PAD_EIM_DA6__GPIO3_IO06,

329

MX6_PAD_EIM_DA6__GPIO3_IO06,

326

};

330

};

327

#endif

331

#endif

328

332

329

#ifdef CONFIG_FSL_ESDHC

333

#ifdef CONFIG_FSL_ESDHC

330

struct fsl_esdhc_cfg usdhc_cfg[3] = {

334

struct fsl_esdhc_cfg usdhc_cfg[3] = {

331

{USDHC2_BASE_ADDR},

335

{USDHC2_BASE_ADDR},

332

{USDHC3_BASE_ADDR},

336

{USDHC3_BASE_ADDR},

333

{USDHC4_BASE_ADDR},

337

{USDHC4_BASE_ADDR},

334

};

338

};

335

339

336

#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)

340

#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)

337

#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)

341

#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)

338

342

339

int board_mmc_get_env_dev(int devno)

343

int board_mmc_get_env_dev(int devno)

340

{

344

{

341

return devno - 1;

345

return devno - 1;

342

}

346

}

343

347

344

int mmc_map_to_kernel_blk(int devno)

348

int mmc_map_to_kernel_blk(int devno)

345

{

349

{

346

return devno + 1;

350

return devno + 1;

347

}

351

}

348

352

349

int board_mmc_getcd(struct mmc *mmc)

353

int board_mmc_getcd(struct mmc *mmc)

350

{

354

{

351

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

355

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

352

int ret = 0;

356

int ret = 0;

353

357

354

switch (cfg->esdhc_base) {

358

switch (cfg->esdhc_base) {

355

case USDHC2_BASE_ADDR:

359

case USDHC2_BASE_ADDR:

356

ret = !gpio_get_value(USDHC2_CD_GPIO);

360

ret = !gpio_get_value(USDHC2_CD_GPIO);

357

break;

361

break;

358

case USDHC3_BASE_ADDR:

362

case USDHC3_BASE_ADDR:

359

ret = !gpio_get_value(USDHC3_CD_GPIO);

363

ret = !gpio_get_value(USDHC3_CD_GPIO);

360

break;

364

break;

361

case USDHC4_BASE_ADDR:

365

case USDHC4_BASE_ADDR:

362

ret = 1; /* eMMC/uSDHC4 is always present */

366

ret = 1; /* eMMC/uSDHC4 is always present */

363

break;

367

break;

364

}

368

}

365

369

366

return ret;

370

return ret;

367

}

371

}

368

372

369

int board_mmc_init(bd_t *bis)

373

int board_mmc_init(bd_t *bis)

370

{

374

{

371

#ifndef CONFIG_SPL_BUILD

375

#ifndef CONFIG_SPL_BUILD

372

int ret;

376

int ret;

373

int i;

377

int i;

374

378

375

/*

379

/*

376

* According to the board_mmc_init() the following map is done:

380

* According to the board_mmc_init() the following map is done:

377

* (U-Boot device node) (Physical Port)

381

* (U-Boot device node) (Physical Port)

378

* mmc0 SD2

382

* mmc0 SD2

379

* mmc1 SD3

383

* mmc1 SD3

380

* mmc2 eMMC

384

* mmc2 eMMC

381

*/

385

*/

382

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

386

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

383

switch (i) {

387

switch (i) {

384

case 0:

388

case 0:

385

imx_iomux_v3_setup_multiple_pads(

389

imx_iomux_v3_setup_multiple_pads(

386

usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

390

usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

387

gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");

391

gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");

388

gpio_direction_input(USDHC2_CD_GPIO);

392

gpio_direction_input(USDHC2_CD_GPIO);

389

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

393

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

390

break;

394

break;

391

case 1:

395

case 1:

392

imx_iomux_v3_setup_multiple_pads(

396

imx_iomux_v3_setup_multiple_pads(

393

usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

397

usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

394

gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");

398

gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");

395

gpio_direction_input(USDHC3_CD_GPIO);

399

gpio_direction_input(USDHC3_CD_GPIO);

396

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

400

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

397

break;

401

break;

398

case 2:

402

case 2:

399

imx_iomux_v3_setup_multiple_pads(

403

imx_iomux_v3_setup_multiple_pads(

400

usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

404

usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

401

usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

405

usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

402

break;

406

break;

403

default:

407

default:

404

printf("Warning: you configured more USDHC controllers"

408

printf("Warning: you configured more USDHC controllers"

405

"(%d) then supported by the board (%d)\n",

409

"(%d) then supported by the board (%d)\n",

406

i + 1, CONFIG_SYS_FSL_USDHC_NUM);

410

i + 1, CONFIG_SYS_FSL_USDHC_NUM);

407

return -EINVAL;

411

return -EINVAL;

408

}

412

}

409

413

410

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

414

ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

411

if (ret)

415

if (ret)

412

return ret;

416

return ret;

413

}

417

}

414

418

415

return 0;

419

return 0;

416

#else

420

#else

417

struct src *psrc = (struct src *)SRC_BASE_ADDR;

421

struct src *psrc = (struct src *)SRC_BASE_ADDR;

418

unsigned reg = readl(&psrc->sbmr1) >> 11;

422

unsigned reg = readl(&psrc->sbmr1) >> 11;

419

/*

423

/*

420

* Upon reading BOOT_CFG register the following map is done:

424

* Upon reading BOOT_CFG register the following map is done:

421

* Bit 11 and 12 of BOOT_CFG register can determine the current

425

* Bit 11 and 12 of BOOT_CFG register can determine the current

422

* mmc port

426

* mmc port

423

* 0x1 SD1

427

* 0x1 SD1

424

* 0x2 SD2

428

* 0x2 SD2

425

* 0x3 SD4

429

* 0x3 SD4

426

*/

430

*/

427

431

428

switch (reg & 0x3) {

432

switch (reg & 0x3) {

429

case 0x1:

433

case 0x1:

430

imx_iomux_v3_setup_multiple_pads(

434

imx_iomux_v3_setup_multiple_pads(

431

usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

435

usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

432

usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;

436

usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;

433

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

437

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

434

gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

438

gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

435

break;

439

break;

436

case 0x2:

440

case 0x2:

437

imx_iomux_v3_setup_multiple_pads(

441

imx_iomux_v3_setup_multiple_pads(

438

usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

442

usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

439

usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;

443

usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;

440

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

444

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

441

gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

445

gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

442

break;

446

break;

443

case 0x3:

447

case 0x3:

444

imx_iomux_v3_setup_multiple_pads(

448

imx_iomux_v3_setup_multiple_pads(

445

usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

449

usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

446

usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;

450

usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;

447

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

451

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

448

gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

452

gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

449

break;

453

break;

450

}

454

}

451

455

452

return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);

456

return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);

453

#endif

457

#endif

454

}

458

}

455

#endif

459

#endif

456

460

457

static int ar8031_phy_fixup(struct phy_device *phydev)

461

static int ar8031_phy_fixup(struct phy_device *phydev)

458

{

462

{

459

unsigned short val;

463

unsigned short val;

460

464

461

/* To enable AR8031 ouput a 125MHz clk from CLK_25M */

465

/* To enable AR8031 ouput a 125MHz clk from CLK_25M */

462

phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);

466

if (!is_mx6dqp()) {

463

phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);

467

phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);

464

phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

468

phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);

469

phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

465

470

466

val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);

471

val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);

467

val &= 0xffe3;

472

val &= 0xffe3;

468

val |= 0x18;

473

val |= 0x18;

469

phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

474

phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

475

}

470

476

477

/* set the IO voltage to 1.8v */

478

phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);

479

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);

480

471

/* introduce tx clock delay */

481

/* introduce tx clock delay */

472

phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);

482

phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);

473

val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);

483

val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);

474

val |= 0x0100;

484

val |= 0x0100;

475

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

485

phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

476

486

477

return 0;

487

return 0;

478

}

488

}

479

489

480

int board_phy_config(struct phy_device *phydev)

490

int board_phy_config(struct phy_device *phydev)

481

{

491

{

482

ar8031_phy_fixup(phydev);

492

ar8031_phy_fixup(phydev);

483

493

484

if (phydev->drv->config)

494

if (phydev->drv->config)

485

phydev->drv->config(phydev);

495

phydev->drv->config(phydev);

486

496

487

return 0;

497

return 0;

488

}

498

}

489

499

490

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

500

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

491

vidinfo_t panel_info = {

501

vidinfo_t panel_info = {

492

.vl_refresh = 85,

502

.vl_refresh = 85,

493

.vl_col = 800,

503

.vl_col = 800,

494

.vl_row = 600,

504

.vl_row = 600,

495

.vl_pixclock = 26666667,

505

.vl_pixclock = 26666667,

496

.vl_left_margin = 8,

506

.vl_left_margin = 8,

497

.vl_right_margin = 100,

507

.vl_right_margin = 100,

498

.vl_upper_margin = 4,

508

.vl_upper_margin = 4,

499

.vl_lower_margin = 8,

509

.vl_lower_margin = 8,

500

.vl_hsync = 4,

510

.vl_hsync = 4,

501

.vl_vsync = 1,

511

.vl_vsync = 1,

502

.vl_sync = 0,

512

.vl_sync = 0,

503

.vl_mode = 0,

513

.vl_mode = 0,

504

.vl_flag = 0,

514

.vl_flag = 0,

505

.vl_bpix = 3,

515

.vl_bpix = 3,

506

.cmap = 0,

516

.cmap = 0,

507

};

517

};

508

518

509

struct epdc_timing_params panel_timings = {

519

struct epdc_timing_params panel_timings = {

510

.vscan_holdoff = 4,

520

.vscan_holdoff = 4,

511

.sdoed_width = 10,

521

.sdoed_width = 10,

512

.sdoed_delay = 20,

522

.sdoed_delay = 20,

513

.sdoez_width = 10,

523

.sdoez_width = 10,

514

.sdoez_delay = 20,

524

.sdoez_delay = 20,

515

.gdclk_hp_offs = 419,

525

.gdclk_hp_offs = 419,

516

.gdsp_offs = 20,

526

.gdsp_offs = 20,

517

.gdoe_offs = 0,

527

.gdoe_offs = 0,

518

.gdclk_offs = 5,

528

.gdclk_offs = 5,

519

.num_ce = 1,

529

.num_ce = 1,

520

};

530

};

521

531

522

static void setup_epdc_power(void)

532

static void setup_epdc_power(void)

523

{

533

{

524

/* Setup epdc voltage */

534

/* Setup epdc voltage */

525

535

526

/* EIM_A17 - GPIO2[21] for PWR_GOOD status */

536

/* EIM_A17 - GPIO2[21] for PWR_GOOD status */

527

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |

537

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |

528

MUX_PAD_CTRL(EPDC_PAD_CTRL));

538

MUX_PAD_CTRL(EPDC_PAD_CTRL));

529

/* Set as input */

539

/* Set as input */

530

gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT");

540

gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT");

531

gpio_direction_input(IMX_GPIO_NR(2, 21));

541

gpio_direction_input(IMX_GPIO_NR(2, 21));

532

542

533

/* EIM_D17 - GPIO3[17] for VCOM control */

543

/* EIM_D17 - GPIO3[17] for VCOM control */

534

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |

544

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |

535

MUX_PAD_CTRL(EPDC_PAD_CTRL));

545

MUX_PAD_CTRL(EPDC_PAD_CTRL));

536

546

537

/* Set as output */

547

/* Set as output */

538

gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0");

548

gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0");

539

gpio_direction_output(IMX_GPIO_NR(3, 17), 1);

549

gpio_direction_output(IMX_GPIO_NR(3, 17), 1);

540

550

541

/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */

551

/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */

542

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |

552

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |

543

MUX_PAD_CTRL(EPDC_PAD_CTRL));

553

MUX_PAD_CTRL(EPDC_PAD_CTRL));

544

/* Set as output */

554

/* Set as output */

545

gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP");

555

gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP");

546

gpio_direction_output(IMX_GPIO_NR(3, 20), 1);

556

gpio_direction_output(IMX_GPIO_NR(3, 20), 1);

547

557

548

/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */

558

/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */

549

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |

559

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |

550

MUX_PAD_CTRL(EPDC_PAD_CTRL));

560

MUX_PAD_CTRL(EPDC_PAD_CTRL));

551

/* Set as output */

561

/* Set as output */

552

gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0");

562

gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0");

553

gpio_direction_output(IMX_GPIO_NR(2, 20), 1);

563

gpio_direction_output(IMX_GPIO_NR(2, 20), 1);

554

}

564

}

555

565

556

static void epdc_enable_pins(void)

566

static void epdc_enable_pins(void)

557

{

567

{

558

/* epdc iomux settings */

568

/* epdc iomux settings */

559

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

569

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

560

ARRAY_SIZE(epdc_enable_pads));

570

ARRAY_SIZE(epdc_enable_pads));

561

}

571

}

562

572

563

static void epdc_disable_pins(void)

573

static void epdc_disable_pins(void)

564

{

574

{

565

/* Configure MUX settings for EPDC pins to GPIO */

575

/* Configure MUX settings for EPDC pins to GPIO */

566

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

576

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

567

ARRAY_SIZE(epdc_disable_pads));

577

ARRAY_SIZE(epdc_disable_pads));

568

}

578

}

569

579

570

static void setup_epdc(void)

580

static void setup_epdc(void)

571

{

581

{

572

unsigned int reg;

582

unsigned int reg;

573

struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

583

struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

574

584

575

/*** Set pixel clock rates for EPDC ***/

585

/*** Set pixel clock rates for EPDC ***/

576

586

577

/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */

587

/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */

578

reg = readl(&ccm_regs->cscdr3);

588

reg = readl(&ccm_regs->cscdr3);

579

reg &= ~0x7C000;

589

reg &= ~0x7C000;

580

reg |= (1 << 16) | (1 << 14);

590

reg |= (1 << 16) | (1 << 14);

581

writel(reg, &ccm_regs->cscdr3);

591

writel(reg, &ccm_regs->cscdr3);

582

592

583

/* EPDC AXI clk enable */

593

/* EPDC AXI clk enable */

584

reg = readl(&ccm_regs->CCGR3);

594

reg = readl(&ccm_regs->CCGR3);

585

reg |= 0x00C0;

595

reg |= 0x00C0;

586

writel(reg, &ccm_regs->CCGR3);

596

writel(reg, &ccm_regs->CCGR3);

587

597

588

/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */

598

/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */

589

reg = readl(&ccm_regs->cscdr2);

599

reg = readl(&ccm_regs->cscdr2);

590

reg &= ~0x3FE00;

600

reg &= ~0x3FE00;

591

reg |= (2 << 15) | (5 << 12);

601

reg |= (2 << 15) | (5 << 12);

592

writel(reg, &ccm_regs->cscdr2);

602

writel(reg, &ccm_regs->cscdr2);

593

603

594

/* PLL5 enable (defaults to 650) */

604

/* PLL5 enable (defaults to 650) */

595

reg = readl(&ccm_regs->analog_pll_video);

605

reg = readl(&ccm_regs->analog_pll_video);

596

reg &= ~((1 << 16) | (1 << 12));

606

reg &= ~((1 << 16) | (1 << 12));

597

reg |= (1 << 13);

607

reg |= (1 << 13);

598

writel(reg, &ccm_regs->analog_pll_video);

608

writel(reg, &ccm_regs->analog_pll_video);

599

609

600

/* EPDC PIX clk enable */

610

/* EPDC PIX clk enable */

601

reg = readl(&ccm_regs->CCGR3);

611

reg = readl(&ccm_regs->CCGR3);

602

reg |= 0x0C00;

612

reg |= 0x0C00;

603

writel(reg, &ccm_regs->CCGR3);

613

writel(reg, &ccm_regs->CCGR3);

604

614

605

panel_info.epdc_data.wv_modes.mode_init = 0;

615

panel_info.epdc_data.wv_modes.mode_init = 0;

606

panel_info.epdc_data.wv_modes.mode_du = 1;

616

panel_info.epdc_data.wv_modes.mode_du = 1;

607

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

617

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

608

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

618

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

609

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

619

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

610

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

620

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

611

621

612

panel_info.epdc_data.epdc_timings = panel_timings;

622

panel_info.epdc_data.epdc_timings = panel_timings;

613

623

614

setup_epdc_power();

624

setup_epdc_power();

615

}

625

}

616

626

617

void epdc_power_on(void)

627

void epdc_power_on(void)

618

{

628

{

619

unsigned int reg;

629

unsigned int reg;

620

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

630

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

621

631

622

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

632

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

623

gpio_set_value(IMX_GPIO_NR(2, 20), 1);

633

gpio_set_value(IMX_GPIO_NR(2, 20), 1);

624

udelay(1000);

634

udelay(1000);

625

635

626

/* Enable epdc signal pin */

636

/* Enable epdc signal pin */

627

epdc_enable_pins();

637

epdc_enable_pins();

628

638

629

/* Set PMIC Wakeup to high - enable Display power */

639

/* Set PMIC Wakeup to high - enable Display power */

630

gpio_set_value(IMX_GPIO_NR(3, 20), 1);

640

gpio_set_value(IMX_GPIO_NR(3, 20), 1);

631

641

632

/* Wait for PWRGOOD == 1 */

642

/* Wait for PWRGOOD == 1 */

633

while (1) {

643

while (1) {

634

reg = readl(&gpio_regs->gpio_psr);

644

reg = readl(&gpio_regs->gpio_psr);

635

if (!(reg & (1 << 21)))

645

if (!(reg & (1 << 21)))

636

break;

646

break;

637

647

638

udelay(100);

648

udelay(100);

639

}

649

}

640

650

641

/* Enable VCOM */

651

/* Enable VCOM */

642

gpio_set_value(IMX_GPIO_NR(3, 17), 1);

652

gpio_set_value(IMX_GPIO_NR(3, 17), 1);

643

653

644

udelay(500);

654

udelay(500);

645

}

655

}

646

656

647

void epdc_power_off(void)

657

void epdc_power_off(void)

648

{

658

{

649

/* Set PMIC Wakeup to low - disable Display power */

659

/* Set PMIC Wakeup to low - disable Display power */

650

gpio_set_value(IMX_GPIO_NR(3, 20), 0);

660

gpio_set_value(IMX_GPIO_NR(3, 20), 0);

651

661

652

/* Disable VCOM */

662

/* Disable VCOM */

653

gpio_set_value(IMX_GPIO_NR(3, 17), 0);

663

gpio_set_value(IMX_GPIO_NR(3, 17), 0);

654

664

655

epdc_disable_pins();

665

epdc_disable_pins();

656

666

657

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

667

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

658

gpio_set_value(IMX_GPIO_NR(2, 20), 0);

668

gpio_set_value(IMX_GPIO_NR(2, 20), 0);

659

}

669

}

660

#endif

670

#endif

661

671

662

#if defined(CONFIG_VIDEO_IPUV3)

672

#if defined(CONFIG_VIDEO_IPUV3)

663

static void disable_lvds(struct display_info_t const *dev)

673

static void disable_lvds(struct display_info_t const *dev)

664

{

674

{

665

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

675

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

666

676

667

int reg = readl(&iomux->gpr[2]);

677

int reg = readl(&iomux->gpr[2]);

668

678

669

reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |

679

reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |

670

IOMUXC_GPR2_LVDS_CH1_MODE_MASK);

680

IOMUXC_GPR2_LVDS_CH1_MODE_MASK);

671

681

672

writel(reg, &iomux->gpr[2]);

682

writel(reg, &iomux->gpr[2]);

673

}

683

}

674

684

675

static void do_enable_hdmi(struct display_info_t const *dev)

685

static void do_enable_hdmi(struct display_info_t const *dev)

676

{

686

{

677

disable_lvds(dev);

687

disable_lvds(dev);

678

imx_enable_hdmi_phy();

688

imx_enable_hdmi_phy();

679

}

689

}

680

690

681

struct display_info_t const displays[] = {{

691

struct display_info_t const displays[] = {{

682

.bus = -1,

692

.bus = -1,

683

.addr = 0,

693

.addr = 0,

684

.pixfmt = IPU_PIX_FMT_RGB666,

694

.pixfmt = IPU_PIX_FMT_RGB666,

685

.detect = NULL,

695

.detect = NULL,

686

.enable = enable_lvds,

696

.enable = enable_lvds,

687

.mode = {

697

.mode = {

688

.name = "Hannstar-XGA",

698

.name = "Hannstar-XGA",

689

.refresh = 60,

699

.refresh = 60,

690

.xres = 1024,

700

.xres = 1024,

691

.yres = 768,

701

.yres = 768,

692

.pixclock = 15384,

702

.pixclock = 15384,

693

.left_margin = 160,

703

.left_margin = 160,

694

.right_margin = 24,

704

.right_margin = 24,

695

.upper_margin = 29,

705

.upper_margin = 29,

696

.lower_margin = 3,

706

.lower_margin = 3,

697

.hsync_len = 136,

707

.hsync_len = 136,

698

.vsync_len = 6,

708

.vsync_len = 6,

699

.sync = FB_SYNC_EXT,

709

.sync = FB_SYNC_EXT,

700

.vmode = FB_VMODE_NONINTERLACED

710

.vmode = FB_VMODE_NONINTERLACED

701

} }, {

711

} }, {

702

.bus = -1,

712

.bus = -1,

703

.addr = 0,

713

.addr = 0,

704

.pixfmt = IPU_PIX_FMT_RGB24,

714

.pixfmt = IPU_PIX_FMT_RGB24,

705

.detect = NULL,

715

.detect = NULL,

706

.enable = do_enable_hdmi,

716

.enable = do_enable_hdmi,

707

.mode = {

717

.mode = {

708

.name = "HDMI",

718

.name = "HDMI",

709

.refresh = 60,

719

.refresh = 60,

710

.xres = 640,

720

.xres = 640,

711

.yres = 480,

721

.yres = 480,

712

.pixclock = 39721,

722

.pixclock = 39721,

713

.left_margin = 48,

723

.left_margin = 48,

714

.right_margin = 16,

724

.right_margin = 16,

715

.upper_margin = 33,

725

.upper_margin = 33,

716

.lower_margin = 10,

726

.lower_margin = 10,

717

.hsync_len = 96,

727

.hsync_len = 96,

718

.vsync_len = 2,

728

.vsync_len = 2,

719

.sync = 0,

729

.sync = 0,

720

.vmode = FB_VMODE_NONINTERLACED

730

.vmode = FB_VMODE_NONINTERLACED

721

} }, {

731

} }, {

722

.bus = 0,

732

.bus = 0,

723

.addr = 0,

733

.addr = 0,

724

.pixfmt = IPU_PIX_FMT_RGB24,

734

.pixfmt = IPU_PIX_FMT_RGB24,

725

.detect = NULL,

735

.detect = NULL,

726

.enable = enable_rgb,

736

.enable = enable_rgb,

727

.mode = {

737

.mode = {

728

.name = "SEIKO-WVGA",

738

.name = "SEIKO-WVGA",

729

.refresh = 60,

739

.refresh = 60,

730

.xres = 800,

740

.xres = 800,

731

.yres = 480,

741

.yres = 480,

732

.pixclock = 29850,

742

.pixclock = 29850,

733

.left_margin = 89,

743

.left_margin = 89,

734

.right_margin = 164,

744

.right_margin = 164,

735

.upper_margin = 23,

745

.upper_margin = 23,

736

.lower_margin = 10,

746

.lower_margin = 10,

737

.hsync_len = 10,

747

.hsync_len = 10,

738

.vsync_len = 10,

748

.vsync_len = 10,

739

.sync = 0,

749

.sync = 0,

740

.vmode = FB_VMODE_NONINTERLACED

750

.vmode = FB_VMODE_NONINTERLACED

741

} } };

751

} } };

742

size_t display_count = ARRAY_SIZE(displays);

752

size_t display_count = ARRAY_SIZE(displays);

743

753

744

static void setup_display(void)

754

static void setup_display(void)

745

{

755

{

746

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

756

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

747

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

757

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

748

int reg;

758

int reg;

749

759

750

/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */

760

/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */

751

imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));

761

imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));

752

762

753

enable_ipu_clock();

763

enable_ipu_clock();

754

imx_setup_hdmi();

764

imx_setup_hdmi();

755

765

756

/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */

766

/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */

757

reg = readl(&mxc_ccm->CCGR3);

767

reg = readl(&mxc_ccm->CCGR3);

758

reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;

768

reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;

759

writel(reg, &mxc_ccm->CCGR3);

769

writel(reg, &mxc_ccm->CCGR3);

760

770

761

/* set LDB0, LDB1 clk select to 011/011 */

771

/* set LDB0, LDB1 clk select to 011/011 */

762

reg = readl(&mxc_ccm->cs2cdr);

772

reg = readl(&mxc_ccm->cs2cdr);

763

reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK

773

reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK

764

| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);

774

| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);

765

reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)

775

reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)

766

| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);

776

| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);

767

writel(reg, &mxc_ccm->cs2cdr);

777

writel(reg, &mxc_ccm->cs2cdr);

768

778

769

reg = readl(&mxc_ccm->cscmr2);

779

reg = readl(&mxc_ccm->cscmr2);

770

reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;

780

reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;

771

writel(reg, &mxc_ccm->cscmr2);

781

writel(reg, &mxc_ccm->cscmr2);

772

782

773

reg = readl(&mxc_ccm->chsccdr);

783

reg = readl(&mxc_ccm->chsccdr);

774

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

784

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

775

<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

785

<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

776

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

786

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

777

<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);

787

<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);

778

writel(reg, &mxc_ccm->chsccdr);

788

writel(reg, &mxc_ccm->chsccdr);

779

789

780

reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

790

reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

781

| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW

791

| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW

782

| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW

792

| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW

783

| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG

793

| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG

784

| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT

794

| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT

785

| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG

795

| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG

786

| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT

796

| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT

787

| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED

797

| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED

788

| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;

798

| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;

789

writel(reg, &iomux->gpr[2]);

799

writel(reg, &iomux->gpr[2]);

790

800

791

reg = readl(&iomux->gpr[3]);

801

reg = readl(&iomux->gpr[3]);

792

reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK

802

reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK

793

| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))

803

| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))

794

| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0

804

| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0

795

<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);

805

<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);

796

writel(reg, &iomux->gpr[3]);

806

writel(reg, &iomux->gpr[3]);

797

}

807

}

798

#endif /* CONFIG_VIDEO_IPUV3 */

808

#endif /* CONFIG_VIDEO_IPUV3 */

799

809

800

/*

810

/*

801

* Do not overwrite the console

811

* Do not overwrite the console

802

* Use always serial for U-Boot console

812

* Use always serial for U-Boot console

803

*/

813

*/

804

int overwrite_console(void)

814

int overwrite_console(void)

805

{

815

{

806

return 1;

816

return 1;

807

}

817

}

808

818

809

static void setup_fec(void)

819

static void setup_fec(void)

810

{

820

{

811

if (is_mx6dqp()) {

821

if (is_mx6dqp()) {

812

int ret;

822

int ret;

813

823

814

/* select ENET MAC0 TX clock from PLL */

824

/* select ENET MAC0 TX clock from PLL */

815

imx_iomux_set_gpr_register(5, 9, 1, 1);

825

imx_iomux_set_gpr_register(5, 9, 1, 1);

816

ret = enable_fec_anatop_clock(0, ENET_125MHZ);

826

ret = enable_fec_anatop_clock(0, ENET_125MHZ);

817

if (ret)

827

if (ret)

818

printf("Error fec anatop clock settings!\n");

828

printf("Error fec anatop clock settings!\n");

819

}

829

}

830

831

fec_phy_reset();

820

}

832

}

821

833

822

int board_eth_init(bd_t *bis)

834

int board_eth_init(bd_t *bis)

823

{

835

{

824

setup_iomux_enet();

836

setup_iomux_enet();

825

837

826

return cpu_eth_init(bis);

838

return cpu_eth_init(bis);

827

}

839

}

828

840

829

#ifdef CONFIG_USB_EHCI_MX6

841

#ifdef CONFIG_USB_EHCI_MX6

830

#ifndef CONFIG_DM_USB

842

#ifndef CONFIG_DM_USB

831

843

832

#define USB_OTHERREGS_OFFSET 0x800

844

#define USB_OTHERREGS_OFFSET 0x800

833

#define UCTRL_PWR_POL (1 << 9)

845

#define UCTRL_PWR_POL (1 << 9)

834

846

835

static iomux_v3_cfg_t const usb_otg_pads[] = {

847

static iomux_v3_cfg_t const usb_otg_pads[] = {

836

MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

848

MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),

837

MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),

849

MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),

838

};

850

};

839

851

840

static iomux_v3_cfg_t const usb_hc1_pads[] = {

852

static iomux_v3_cfg_t const usb_hc1_pads[] = {

841

MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

853

MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

842

};

854

};

843

855

844

static void setup_usb(void)

856

static void setup_usb(void)

845

{

857

{

846

imx_iomux_v3_setup_multiple_pads(usb_otg_pads,

858

imx_iomux_v3_setup_multiple_pads(usb_otg_pads,

847

ARRAY_SIZE(usb_otg_pads));

859

ARRAY_SIZE(usb_otg_pads));

848

860

849

/*

861

/*

850

* set daisy chain for otg_pin_id on 6q.

862

* set daisy chain for otg_pin_id on 6q.

851

* for 6dl, this bit is reserved

863

* for 6dl, this bit is reserved

852

*/

864

*/

853

imx_iomux_set_gpr_register(1, 13, 1, 0);

865

imx_iomux_set_gpr_register(1, 13, 1, 0);

854

866

855

imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,

867

imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,

856

ARRAY_SIZE(usb_hc1_pads));

868

ARRAY_SIZE(usb_hc1_pads));

857

gpio_request(IMX_GPIO_NR(1, 29), "USB HC1 Power Enable");

869

gpio_request(IMX_GPIO_NR(1, 29), "USB HC1 Power Enable");

858

}

870

}

859

871

860

int board_ehci_hcd_init(int port)

872

int board_ehci_hcd_init(int port)

861

{

873

{

862

u32 *usbnc_usb_ctrl;

874

u32 *usbnc_usb_ctrl;

863

875

864

if (port > 1)

876

if (port > 1)

865

return -EINVAL;

877

return -EINVAL;

866

878

867

usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +

879

usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +

868

port * 4);

880

port * 4);

869

881

870

setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);

882

setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);

871

883

872

return 0;

884

return 0;

873

}

885

}

874

886

875

int board_ehci_power(int port, int on)

887

int board_ehci_power(int port, int on)

876

{

888

{

877

switch (port) {

889

switch (port) {

878

case 0:

890

case 0:

879

break;

891

break;

880

case 1:

892

case 1:

881

if (on)

893

if (on)

882

gpio_direction_output(IMX_GPIO_NR(1, 29), 1);

894

gpio_direction_output(IMX_GPIO_NR(1, 29), 1);

883

else

895

else

884

gpio_direction_output(IMX_GPIO_NR(1, 29), 0);

896

gpio_direction_output(IMX_GPIO_NR(1, 29), 0);

885

break;

897

break;

886

default:

898

default:

887

printf("MXC USB port %d not yet supported\n", port);

899

printf("MXC USB port %d not yet supported\n", port);

888

return -EINVAL;

900

return -EINVAL;

889

}

901

}

890

902

891

return 0;

903

return 0;

892

}

904

}

893

#endif

905

#endif

894

#endif

906

#endif

895

907

896

int board_early_init_f(void)

908

int board_early_init_f(void)

897

{

909

{

898

setup_iomux_uart();

910

setup_iomux_uart();

899

#if defined(CONFIG_VIDEO_IPUV3)

911

#if defined(CONFIG_VIDEO_IPUV3)

900

setup_display();

912

setup_display();

901

#endif

913

#endif

902

914

903

return 0;

915

return 0;

904

}

916

}

905

917

906

int board_init(void)

918

int board_init(void)

907

{

919

{

908

/* address of boot parameters */

920

/* address of boot parameters */

909

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

921

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

910

922

911

#ifdef CONFIG_MXC_SPI

923

#ifdef CONFIG_MXC_SPI

912

setup_spi();

924

setup_spi();

913

#endif

925

#endif

914

926

915

#ifdef CONFIG_SYS_I2C

927

#ifdef CONFIG_SYS_I2C

916

setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

928

setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

917

#endif

929

#endif

918

930

919

#ifdef CONFIG_USB_EHCI_MX6

931

#ifdef CONFIG_USB_EHCI_MX6

920

#ifndef CONFIG_DM_USB

932

#ifndef CONFIG_DM_USB

921

setup_usb();

933

setup_usb();

922

#else

934

#else

923

/*

935

/*

924

* set daisy chain for otg_pin_id on 6q.

936

* set daisy chain for otg_pin_id on 6q.

925

* for 6dl, this bit is reserved

937

* for 6dl, this bit is reserved

926

*/

938

*/

927

imx_iomux_set_gpr_register(1, 13, 1, 0);

939

imx_iomux_set_gpr_register(1, 13, 1, 0);

928

#endif

940

#endif

929

#endif

941

#endif

930

942

931

#ifdef CONFIG_PCIE_IMX

943

#ifdef CONFIG_PCIE_IMX

932

setup_pcie();

944

setup_pcie();

933

#endif

945

#endif

934

946

935

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

947

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

936

setup_epdc();

948

setup_epdc();

937

#endif

949

#endif

938

950

939

#ifdef CONFIG_CMD_SATA

951

#ifdef CONFIG_CMD_SATA

940

setup_sata();

952

setup_sata();

941

#endif

953

#endif

942

954

943

#ifdef CONFIG_FEC_MXC

955

#ifdef CONFIG_FEC_MXC

944

setup_fec();

956

setup_fec();

945

#endif

957

#endif

946

958

947

return 0;

959

return 0;

948

}

960

}

949

961

950

#ifdef CONFIG_POWER

962

#ifdef CONFIG_POWER

951

int power_init_board(void)

963

int power_init_board(void)

952

{

964

{

953

struct pmic *pfuze;

965

struct pmic *pfuze;

954

unsigned int reg;

966

unsigned int reg;

955

int ret;

967

int ret;

956

968

957

pfuze = pfuze_common_init(I2C_PMIC);

969

pfuze = pfuze_common_init(I2C_PMIC);

958

if (!pfuze)

970

if (!pfuze)

959

return -ENODEV;

971

return -ENODEV;

960

972

961

if (is_mx6dqp())

973

if (is_mx6dqp())

962

ret = pfuze_mode_init(pfuze, APS_APS);

974

ret = pfuze_mode_init(pfuze, APS_APS);

963

else

975

else

964

ret = pfuze_mode_init(pfuze, APS_PFM);

976

ret = pfuze_mode_init(pfuze, APS_PFM);

965

977

966

if (ret < 0)

978

if (ret < 0)

967

return ret;

979

return ret;

968

/* VGEN3 and VGEN5 corrected on i.mx6qp board */

980

/* VGEN3 and VGEN5 corrected on i.mx6qp board */

969

if (!is_mx6dqp()) {

981

if (!is_mx6dqp()) {

970

/* Increase VGEN3 from 2.5 to 2.8V */

982

/* Increase VGEN3 from 2.5 to 2.8V */

971

pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);

983

pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);

972

reg &= ~LDO_VOL_MASK;

984

reg &= ~LDO_VOL_MASK;

973

reg |= LDOB_2_80V;

985

reg |= LDOB_2_80V;

974

pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);

986

pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);

975

987

976

/* Increase VGEN5 from 2.8 to 3V */

988

/* Increase VGEN5 from 2.8 to 3V */

977

pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);

989

pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);

978

reg &= ~LDO_VOL_MASK;

990

reg &= ~LDO_VOL_MASK;

979

reg |= LDOB_3_00V;

991

reg |= LDOB_3_00V;

980

pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);

992

pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);

981

}

993

}

982

994

983

if (is_mx6dqp()) {

995

if (is_mx6dqp()) {

984

/* set SW1C staby volatage 1.075V*/

996

/* set SW1C staby volatage 1.075V*/

985

pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);

997

pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);

986

reg &= ~0x3f;

998

reg &= ~0x3f;

987

reg |= 0x1f;

999

reg |= 0x1f;

988

pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);

1000

pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);

989

1001

990

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1002

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

991

pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);

1003

pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);

992

reg &= ~0xc0;

1004

reg &= ~0xc0;

993

reg |= 0x40;

1005

reg |= 0x40;

994

pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);

1006

pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);

995

1007

996

/* set SW2/VDDARM staby volatage 0.975V*/

1008

/* set SW2/VDDARM staby volatage 0.975V*/

997

pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);

1009

pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);

998

reg &= ~0x3f;

1010

reg &= ~0x3f;

999

reg |= 0x17;

1011

reg |= 0x17;

1000

pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);

1012

pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);

1001

1013

1002

/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */

1014

/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */

1003

pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);

1015

pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);

1004

reg &= ~0xc0;

1016

reg &= ~0xc0;

1005

reg |= 0x40;

1017

reg |= 0x40;

1006

pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);

1018

pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);

1007

} else {

1019

} else {

1008

/* set SW1AB staby volatage 0.975V*/

1020

/* set SW1AB staby volatage 0.975V*/

1009

pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);

1021

pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);

1010

reg &= ~0x3f;

1022

reg &= ~0x3f;

1011

reg |= 0x1b;

1023

reg |= 0x1b;

1012

pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);

1024

pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);

1013

1025

1014

/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */

1026

/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */

1015

pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);

1027

pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);

1016

reg &= ~0xc0;

1028

reg &= ~0xc0;

1017

reg |= 0x40;

1029

reg |= 0x40;

1018

pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);

1030

pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);

1019

1031

1020

/* set SW1C staby volatage 0.975V*/

1032

/* set SW1C staby volatage 0.975V*/

1021

pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);

1033

pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);

1022

reg &= ~0x3f;

1034

reg &= ~0x3f;

1023

reg |= 0x1b;

1035

reg |= 0x1b;

1024

pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);

1036

pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);

1025

1037

1026

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1038

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1027

pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);

1039

pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);

1028

reg &= ~0xc0;

1040

reg &= ~0xc0;

1029

reg |= 0x40;

1041

reg |= 0x40;

1030

pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);

1042

pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);

1031

}

1043

}

1032

1044

1033

return 0;

1045

return 0;

1034

}

1046

}

1035

1047

1036

#elif defined(CONFIG_DM_PMIC_PFUZE100)

1048

#elif defined(CONFIG_DM_PMIC_PFUZE100)

1037

int power_init_board(void)

1049

int power_init_board(void)

1038

{

1050

{

1039

struct udevice *dev;

1051

struct udevice *dev;

1040

unsigned int reg;

1052

unsigned int reg;

1041

int ret;

1053

int ret;

1042

1054

1043

dev = pfuze_common_init();

1055

dev = pfuze_common_init();

1044

if (!dev)

1056

if (!dev)

1045

return -ENODEV;

1057

return -ENODEV;

1046

1058

1047

if (is_mx6dqp())

1059

if (is_mx6dqp())

1048

ret = pfuze_mode_init(dev, APS_APS);

1060

ret = pfuze_mode_init(dev, APS_APS);

1049

else

1061

else

1050

ret = pfuze_mode_init(dev, APS_PFM);

1062

ret = pfuze_mode_init(dev, APS_PFM);

1051

if (ret < 0)

1063

if (ret < 0)

1052

return ret;

1064

return ret;

1053

1065

1054

/* VGEN3 and VGEN5 corrected on i.mx6qp board */

1066

/* VGEN3 and VGEN5 corrected on i.mx6qp board */

1055

if (!is_mx6dqp()) {

1067

if (!is_mx6dqp()) {

1056

/* Increase VGEN3 from 2.5 to 2.8V */

1068

/* Increase VGEN3 from 2.5 to 2.8V */

1057

reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);

1069

reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);

1058

reg &= ~LDO_VOL_MASK;

1070

reg &= ~LDO_VOL_MASK;

1059

reg |= LDOB_2_80V;

1071

reg |= LDOB_2_80V;

1060

pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);

1072

pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);

1061

1073

1062

/* Increase VGEN5 from 2.8 to 3V */

1074

/* Increase VGEN5 from 2.8 to 3V */

1063

reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);

1075

reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);

1064

reg &= ~LDO_VOL_MASK;

1076

reg &= ~LDO_VOL_MASK;

1065

reg |= LDOB_3_00V;

1077

reg |= LDOB_3_00V;

1066

pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);

1078

pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);

1067

}

1079

}

1068

1080

1069

if (is_mx6dqp()) {

1081

if (is_mx6dqp()) {

1070

/* set SW1C staby volatage 1.075V*/

1082

/* set SW1C staby volatage 1.075V*/

1071

reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);

1083

reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);

1072

reg &= ~0x3f;

1084

reg &= ~0x3f;

1073

reg |= 0x1f;

1085

reg |= 0x1f;

1074

pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);

1086

pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);

1075

1087

1076

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1088

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1077

reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);

1089

reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);

1078

reg &= ~0xc0;

1090

reg &= ~0xc0;

1079

reg |= 0x40;

1091

reg |= 0x40;

1080

pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);

1092

pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);

1081

1093

1082

/* set SW2/VDDARM staby volatage 0.975V*/

1094

/* set SW2/VDDARM staby volatage 0.975V*/

1083

reg = pmic_reg_read(dev, PFUZE100_SW2STBY);

1095

reg = pmic_reg_read(dev, PFUZE100_SW2STBY);

1084

reg &= ~0x3f;

1096

reg &= ~0x3f;

1085

reg |= 0x17;

1097

reg |= 0x17;

1086

pmic_reg_write(dev, PFUZE100_SW2STBY, reg);

1098

pmic_reg_write(dev, PFUZE100_SW2STBY, reg);

1087

1099

1088

/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */

1100

/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */

1089

reg = pmic_reg_read(dev, PFUZE100_SW2CONF);

1101

reg = pmic_reg_read(dev, PFUZE100_SW2CONF);

1090

reg &= ~0xc0;

1102

reg &= ~0xc0;

1091

reg |= 0x40;

1103

reg |= 0x40;

1092

pmic_reg_write(dev, PFUZE100_SW2CONF, reg);

1104

pmic_reg_write(dev, PFUZE100_SW2CONF, reg);

1093

} else {

1105

} else {

1094

/* set SW1AB staby volatage 0.975V*/

1106

/* set SW1AB staby volatage 0.975V*/

1095

reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);

1107

reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);

1096

reg &= ~0x3f;

1108

reg &= ~0x3f;

1097

reg |= 0x1b;

1109

reg |= 0x1b;

1098

pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);

1110

pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);

1099

1111

1100

/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */

1112

/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */

1101

reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);

1113

reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);

1102

reg &= ~0xc0;

1114

reg &= ~0xc0;

1103

reg |= 0x40;

1115

reg |= 0x40;

1104

pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);

1116

pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);

1105

1117

1106

/* set SW1C staby volatage 0.975V*/

1118

/* set SW1C staby volatage 0.975V*/

1107

reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);

1119

reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);

1108

reg &= ~0x3f;

1120

reg &= ~0x3f;

1109

reg |= 0x1b;

1121

reg |= 0x1b;

1110

pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);

1122

pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);

1111

1123

1112

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1124

/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */

1113

reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);

1125

reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);

1114

reg &= ~0xc0;

1126

reg &= ~0xc0;

1115

reg |= 0x40;

1127

reg |= 0x40;

1116

pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);

1128

pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);

1117

}

1129

}

1118

1130

1119

return 0;

1131

return 0;

1120

}

1132

}

1121

#endif

1133

#endif

1122

1134

1123

#ifdef CONFIG_LDO_BYPASS_CHECK

1135

#ifdef CONFIG_LDO_BYPASS_CHECK

1124

#ifdef CONFIG_POWER

1136

#ifdef CONFIG_POWER

1125

void ldo_mode_set(int ldo_bypass)

1137

void ldo_mode_set(int ldo_bypass)

1126

{

1138

{

1127

unsigned int value;

1139

unsigned int value;

1128

int is_400M;

1140

int is_400M;

1129

unsigned char vddarm;

1141

unsigned char vddarm;

1130

struct pmic *p = pmic_get("PFUZE100");

1142

struct pmic *p = pmic_get("PFUZE100");

1131

1143

1132

if (!p) {

1144

if (!p) {

1133

printf("No PMIC found!\n");

1145

printf("No PMIC found!\n");

1134

return;

1146

return;

1135

}

1147

}

1136

1148

1137

/* increase VDDARM/VDDSOC to support 1.2G chip */

1149

/* increase VDDARM/VDDSOC to support 1.2G chip */

1138

if (check_1_2G()) {

1150

if (check_1_2G()) {

1139

ldo_bypass = 0; /* ldo_enable on 1.2G chip */

1151

ldo_bypass = 0; /* ldo_enable on 1.2G chip */

1140

printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");

1152

printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");

1141

if (is_mx6dqp()) {

1153

if (is_mx6dqp()) {

1142

/* increase VDDARM to 1.425V */

1154

/* increase VDDARM to 1.425V */

1143

pmic_reg_read(p, PFUZE100_SW2VOL, &value);

1155

pmic_reg_read(p, PFUZE100_SW2VOL, &value);

1144

value &= ~0x3f;

1156

value &= ~0x3f;

1145

value |= 0x29;

1157

value |= 0x29;

1146

pmic_reg_write(p, PFUZE100_SW2VOL, value);

1158

pmic_reg_write(p, PFUZE100_SW2VOL, value);

1147

} else {

1159

} else {

1148

/* increase VDDARM to 1.425V */

1160

/* increase VDDARM to 1.425V */

1149

pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);

1161

pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);

1150

value &= ~0x3f;

1162

value &= ~0x3f;

1151

value |= 0x2d;

1163

value |= 0x2d;

1152

pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

1164

pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

1153

}

1165

}

1154

/* increase VDDSOC to 1.425V */

1166

/* increase VDDSOC to 1.425V */

1155

pmic_reg_read(p, PFUZE100_SW1CVOL, &value);

1167

pmic_reg_read(p, PFUZE100_SW1CVOL, &value);

1156

value &= ~0x3f;

1168

value &= ~0x3f;

1157

value |= 0x2d;

1169

value |= 0x2d;

1158

pmic_reg_write(p, PFUZE100_SW1CVOL, value);

1170

pmic_reg_write(p, PFUZE100_SW1CVOL, value);

1159

}

1171

}

1160

/* switch to ldo_bypass mode , boot on 800Mhz */

1172

/* switch to ldo_bypass mode , boot on 800Mhz */

1161

if (ldo_bypass) {

1173

if (ldo_bypass) {

1162

prep_anatop_bypass();

1174

prep_anatop_bypass();

1163

if (is_mx6dqp()) {

1175

if (is_mx6dqp()) {

1164

/* decrease VDDARM for 400Mhz DQP:1.1V*/

1176

/* decrease VDDARM for 400Mhz DQP:1.1V*/

1165

pmic_reg_read(p, PFUZE100_SW2VOL, &value);

1177

pmic_reg_read(p, PFUZE100_SW2VOL, &value);

1166

value &= ~0x3f;

1178

value &= ~0x3f;

1167

value |= 0x1c;

1179

value |= 0x1c;

1168

pmic_reg_write(p, PFUZE100_SW2VOL, value);

1180

pmic_reg_write(p, PFUZE100_SW2VOL, value);

1169

} else {

1181

} else {

1170

/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */

1182

/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */

1171

pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);

1183

pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);

1172

value &= ~0x3f;

1184

value &= ~0x3f;

1173

if (is_mx6dl())

1185

if (is_mx6dl())

1174

value |= 0x27;

1186

value |= 0x27;

1175

else

1187

else

1176

value |= 0x20;

1188

value |= 0x20;

1177

1189

1178

pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

1190

pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

1179

}

1191

}

1180

/* increase VDDSOC to 1.3V */

1192

/* increase VDDSOC to 1.3V */

1181

pmic_reg_read(p, PFUZE100_SW1CVOL, &value);

1193

pmic_reg_read(p, PFUZE100_SW1CVOL, &value);

1182

value &= ~0x3f;

1194

value &= ~0x3f;

1183

value |= 0x28;

1195

value |= 0x28;

1184

pmic_reg_write(p, PFUZE100_SW1CVOL, value);

1196

pmic_reg_write(p, PFUZE100_SW1CVOL, value);

1185

1197

1186

/*

1198

/*

1187

* MX6Q/DQP:

1199

* MX6Q/DQP:

1188

* VDDARM:1.15V@800M; VDDSOC:1.175V@800M

1200

* VDDARM:1.15V@800M; VDDSOC:1.175V@800M

1189

* VDDARM:0.975V@400M; VDDSOC:1.175V@400M

1201

* VDDARM:0.975V@400M; VDDSOC:1.175V@400M

1190

* MX6DL:

1202

* MX6DL:

1191

* VDDARM:1.175V@800M; VDDSOC:1.175V@800M

1203

* VDDARM:1.175V@800M; VDDSOC:1.175V@800M

1192

* VDDARM:1.075V@400M; VDDSOC:1.175V@400M

1204

* VDDARM:1.075V@400M; VDDSOC:1.175V@400M

1193

*/

1205

*/

1194

is_400M = set_anatop_bypass(2);

1206

is_400M = set_anatop_bypass(2);

1195

if (is_mx6dqp()) {

1207

if (is_mx6dqp()) {

1196

pmic_reg_read(p, PFUZE100_SW2VOL, &value);

1208

pmic_reg_read(p, PFUZE100_SW2VOL, &value);

1197

value &= ~0x3f;

1209

value &= ~0x3f;

1198

if (is_400M)

1210

if (is_400M)

1199

value |= 0x17;

1211

value |= 0x17;

1200

else

1212

else

1201

value |= 0x1e;

1213

value |= 0x1e;

1202

pmic_reg_write(p, PFUZE100_SW2VOL, value);

1214

pmic_reg_write(p, PFUZE100_SW2VOL, value);

1203

}

1215

}

1204

1216

1205

if (is_400M) {

1217

if (is_400M) {

1206

if (is_mx6dl())

1218

if (is_mx6dl())

1207

vddarm = 0x1f;

1219

vddarm = 0x1f;

1208

else

1220

else

1209

vddarm = 0x1b;

1221

vddarm = 0x1b;

1210

} else {

1222

} else {

1211

if (is_mx6dl())

1223

if (is_mx6dl())

1212

vddarm = 0x23;

1224

vddarm = 0x23;

1213

else

1225

else

1214

vddarm = 0x22;

1226

vddarm = 0x22;

1215

}

1227

}

1216

pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);

1228

pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);

1217

value &= ~0x3f;

1229

value &= ~0x3f;

1218

value |= vddarm;

1230

value |= vddarm;

1219

pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

1231

pmic_reg_write(p, PFUZE100_SW1ABVOL, value);

1220

1232

1221

/* decrease VDDSOC to 1.175V */

1233

/* decrease VDDSOC to 1.175V */

1222

pmic_reg_read(p, PFUZE100_SW1CVOL, &value);

1234

pmic_reg_read(p, PFUZE100_SW1CVOL, &value);

1223

value &= ~0x3f;

1235

value &= ~0x3f;

1224

value |= 0x23;

1236

value |= 0x23;

1225

pmic_reg_write(p, PFUZE100_SW1CVOL, value);

1237

pmic_reg_write(p, PFUZE100_SW1CVOL, value);

1226

1238

1227

finish_anatop_bypass();

1239

finish_anatop_bypass();

1228

printf("switch to ldo_bypass mode!\n");

1240

printf("switch to ldo_bypass mode!\n");

1229

}

1241

}

1230

}

1242

}

1231

#elif defined(CONFIG_DM_PMIC_PFUZE100)

1243

#elif defined(CONFIG_DM_PMIC_PFUZE100)

1232

void ldo_mode_set(int ldo_bypass)

1244

void ldo_mode_set(int ldo_bypass)

1233

{

1245

{

1234

int is_400M;

1246

int is_400M;

1235

unsigned char vddarm;

1247

unsigned char vddarm;

1236

struct udevice *dev;

1248

struct udevice *dev;

1237

int ret;

1249

int ret;

1238

1250

1239

ret = pmic_get("pfuze100", &dev);

1251

ret = pmic_get("pfuze100", &dev);

1240

if (ret == -ENODEV) {

1252

if (ret == -ENODEV) {

1241

printf("No PMIC found!\n");

1253

printf("No PMIC found!\n");

1242

return;

1254

return;

1243

}

1255

}

1244

1256

1245

/* increase VDDARM/VDDSOC to support 1.2G chip */

1257

/* increase VDDARM/VDDSOC to support 1.2G chip */

1246

if (check_1_2G()) {

1258

if (check_1_2G()) {

1247

ldo_bypass = 0; /* ldo_enable on 1.2G chip */

1259

ldo_bypass = 0; /* ldo_enable on 1.2G chip */

1248

printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");

1260

printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");

1249

if (is_mx6dqp()) {

1261

if (is_mx6dqp()) {

1250

/* increase VDDARM to 1.425V */

1262

/* increase VDDARM to 1.425V */

1251

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);

1263

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);

1252

} else {

1264

} else {

1253

/* increase VDDARM to 1.425V */

1265

/* increase VDDARM to 1.425V */

1254

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);

1266

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);

1255

}

1267

}

1256

/* increase VDDSOC to 1.425V */

1268

/* increase VDDSOC to 1.425V */

1257

pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);

1269

pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);

1258

}

1270

}

1259

/* switch to ldo_bypass mode , boot on 800Mhz */

1271

/* switch to ldo_bypass mode , boot on 800Mhz */

1260

if (ldo_bypass) {

1272

if (ldo_bypass) {

1261

prep_anatop_bypass();

1273

prep_anatop_bypass();

1262

if (is_mx6dqp()) {

1274

if (is_mx6dqp()) {

1263

/* decrease VDDARM for 400Mhz DQP:1.1V*/

1275

/* decrease VDDARM for 400Mhz DQP:1.1V*/

1264

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c);

1276

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c);

1265

} else {

1277

} else {

1266

/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */

1278

/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */

1267

if (is_mx6dl())

1279

if (is_mx6dl())

1268

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27);

1280

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27);

1269

else

1281

else

1270

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);

1282

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);

1271

}

1283

}

1272

/* increase VDDSOC to 1.3V */

1284

/* increase VDDSOC to 1.3V */

1273

pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);

1285

pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);

1274

1286

1275

/*

1287

/*

1276

* MX6Q/DQP:

1288

* MX6Q/DQP:

1277

* VDDARM:1.15V@800M; VDDSOC:1.175V@800M

1289

* VDDARM:1.15V@800M; VDDSOC:1.175V@800M

1278

* VDDARM:0.975V@400M; VDDSOC:1.175V@400M

1290

* VDDARM:0.975V@400M; VDDSOC:1.175V@400M

1279

* MX6DL:

1291

* MX6DL:

1280

* VDDARM:1.175V@800M; VDDSOC:1.175V@800M

1292

* VDDARM:1.175V@800M; VDDSOC:1.175V@800M

1281

* VDDARM:1.075V@400M; VDDSOC:1.175V@400M

1293

* VDDARM:1.075V@400M; VDDSOC:1.175V@400M

1282

*/

1294

*/

1283

is_400M = set_anatop_bypass(2);

1295

is_400M = set_anatop_bypass(2);

1284

if (is_mx6dqp()) {

1296

if (is_mx6dqp()) {

1285

if (is_400M)

1297

if (is_400M)

1286

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17);

1298

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17);

1287

else

1299

else

1288

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e);

1300

pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e);

1289

}

1301

}

1290

1302

1291

if (is_400M) {

1303

if (is_400M) {

1292

if (is_mx6dl())

1304

if (is_mx6dl())

1293

vddarm = 0x1f;

1305

vddarm = 0x1f;

1294

else

1306

else

1295

vddarm = 0x1b;

1307

vddarm = 0x1b;

1296

} else {

1308

} else {

1297

if (is_mx6dl())

1309

if (is_mx6dl())

1298

vddarm = 0x23;

1310

vddarm = 0x23;

1299

else

1311

else

1300

vddarm = 0x22;

1312

vddarm = 0x22;

1301

}

1313

}

1302

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);

1314

pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);

1303

1315

1304

/* decrease VDDSOC to 1.175V */

1316

/* decrease VDDSOC to 1.175V */

1305

pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);

1317

pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);

1306

1318

1307

finish_anatop_bypass();

1319

finish_anatop_bypass();

1308

printf("switch to ldo_bypass mode!\n");

1320

printf("switch to ldo_bypass mode!\n");

1309

}

1321

}

1310

}

1322

}

1311

#endif

1323

#endif

1312

#endif

1324

#endif

1313

1325

1314

#ifdef CONFIG_CMD_BMODE

1326

#ifdef CONFIG_CMD_BMODE

1315

static const struct boot_mode board_boot_modes[] = {

1327

static const struct boot_mode board_boot_modes[] = {

1316

/* 4 bit bus width */

1328

/* 4 bit bus width */

1317

{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},

1329

{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},

1318

{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},

1330

{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},

1319

/* 8 bit bus width */

1331

/* 8 bit bus width */

1320

{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},

1332

{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},

1321

{NULL, 0},

1333

{NULL, 0},

1322

};

1334

};

1323

#endif

1335

#endif

1324

1336

1325

int board_late_init(void)

1337

int board_late_init(void)

1326

{

1338

{

1327

#ifdef CONFIG_CMD_BMODE

1339

#ifdef CONFIG_CMD_BMODE

1328

add_board_boot_modes(board_boot_modes);

1340

add_board_boot_modes(board_boot_modes);

1329

#endif

1341

#endif

1330

1342

1331

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

1343

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

1332

setenv("board_name", "SABRESD");

1344

setenv("board_name", "SABRESD");

1333

1345

1334

if (is_mx6dqp())

1346

if (is_mx6dqp())

1335

setenv("board_rev", "MX6QP");

1347

setenv("board_rev", "MX6QP");

1336

else if (is_mx6dq())

1348

else if (is_mx6dq())

1337

setenv("board_rev", "MX6Q");

1349

setenv("board_rev", "MX6Q");

1338

else if (is_mx6sdl())

1350

else if (is_mx6sdl())

1339

setenv("board_rev", "MX6DL");

1351

setenv("board_rev", "MX6DL");

1340

#endif

1352

#endif

1341

1353

1342

#ifdef CONFIG_ENV_IS_IN_MMC

1354

#ifdef CONFIG_ENV_IS_IN_MMC

1343

board_late_mmc_env_init();

1355

board_late_mmc_env_init();

1344

#endif

1356

#endif

1345

1357

1346

return 0;

1358

return 0;

1347

}

1359

}

1348

1360

1349

int checkboard(void)

1361

int checkboard(void)

1350

{

1362

{

1351

puts("Board: MX6-SabreSD\n");

1363

puts("Board: MX6-SabreSD\n");

1352

return 0;

1364

return 0;

1353

}

1365

}

1354

1366

1355

#ifdef CONFIG_FSL_FASTBOOT

1367

#ifdef CONFIG_FSL_FASTBOOT

1356

#ifdef CONFIG_ANDROID_RECOVERY

1368

#ifdef CONFIG_ANDROID_RECOVERY

1357

1369

1358

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)

1370

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)

1359

iomux_v3_cfg_t const recovery_key_pads[] = {

1371

iomux_v3_cfg_t const recovery_key_pads[] = {

1360

(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),

1372

(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),

1361

};

1373

};

1362

1374

1363

int is_recovery_key_pressing(void)

1375

int is_recovery_key_pressing(void)

1364

{

1376

{

1365

int button_pressed = 0;

1377

int button_pressed = 0;

1366

1378

1367

/* Check Recovery Combo Button press or not. */

1379

/* Check Recovery Combo Button press or not. */

1368

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1380

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1369

ARRAY_SIZE(recovery_key_pads));

1381

ARRAY_SIZE(recovery_key_pads));

1370

1382

1371

gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");

1383

gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");

1372

gpio_direction_input(GPIO_VOL_DN_KEY);

1384

gpio_direction_input(GPIO_VOL_DN_KEY);

1373

1385

1374

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1386

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1375

button_pressed = 1;

1387

button_pressed = 1;

1376

printf("Recovery key pressed\n");

1388

printf("Recovery key pressed\n");

1377

}

1389

}

1378

1390

1379

return button_pressed;

1391

return button_pressed;

1380

}

1392

}

1381

1393

1382

#endif /*CONFIG_ANDROID_RECOVERY*/

1394

#endif /*CONFIG_ANDROID_RECOVERY*/

1383

1395

1384

#endif /*CONFIG_FSL_FASTBOOT*/

1396

#endif /*CONFIG_FSL_FASTBOOT*/

1385

1397

1386

1398

1387

#ifdef CONFIG_SPL_BUILD

1399

#ifdef CONFIG_SPL_BUILD

1388

#include <spl.h>

1400

#include <spl.h>

1389

#include <libfdt.h>

1401

#include <libfdt.h>

1390

1402

1391

#ifdef CONFIG_SPL_OS_BOOT

1403

#ifdef CONFIG_SPL_OS_BOOT

1392

int spl_start_uboot(void)

1404

int spl_start_uboot(void)

1393

{

1405

{

1394

gpio_request(KEY_VOL_UP, "KEY Volume UP");

1406

gpio_request(KEY_VOL_UP, "KEY Volume UP");

1395

gpio_direction_input(KEY_VOL_UP);

1407

gpio_direction_input(KEY_VOL_UP);

1396

1408

1397

/* Only enter in Falcon mode if KEY_VOL_UP is pressed */

1409

/* Only enter in Falcon mode if KEY_VOL_UP is pressed */

1398

return gpio_get_value(KEY_VOL_UP);

1410

return gpio_get_value(KEY_VOL_UP);

1399

}

1411

}

1400

#endif

1412

#endif

1401

1413

1402

static void ccgr_init(void)

1414

static void ccgr_init(void)

1403

{

1415

{

1404

struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

1416

struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

1405

1417

1406

writel(0x00C03F3F, &ccm->CCGR0);

1418

writel(0x00C03F3F, &ccm->CCGR0);

1407

writel(0x0030FC03, &ccm->CCGR1);

1419

writel(0x0030FC03, &ccm->CCGR1);

1408

writel(0x0FFFC000, &ccm->CCGR2);

1420

writel(0x0FFFC000, &ccm->CCGR2);

1409

writel(0x3FF00000, &ccm->CCGR3);

1421

writel(0x3FF00000, &ccm->CCGR3);

1410

writel(0x00FFF300, &ccm->CCGR4);

1422

writel(0x00FFF300, &ccm->CCGR4);

1411

writel(0x0F0000C3, &ccm->CCGR5);

1423

writel(0x0F0000C3, &ccm->CCGR5);

1412

writel(0x000003FF, &ccm->CCGR6);

1424

writel(0x000003FF, &ccm->CCGR6);

1413

}

1425

}

1414

1426

1415

static void gpr_init(void)

1427

static void gpr_init(void)

1416

{

1428

{

1417

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

1429

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

1418

1430

1419

/* enable AXI cache for VDOA/VPU/IPU */

1431

/* enable AXI cache for VDOA/VPU/IPU */

1420

writel(0xF00000CF, &iomux->gpr[4]);

1432

writel(0xF00000CF, &iomux->gpr[4]);

1421

if (is_mx6dqp()) {

1433

if (is_mx6dqp()) {

1422

/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

1434

/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

1423

writel(0x007F007F, &iomux->gpr[6]);

1435

writel(0x007F007F, &iomux->gpr[6]);

1424

writel(0x007F007F, &iomux->gpr[7]);

1436

writel(0x007F007F, &iomux->gpr[7]);

1425

} else {

1437

} else {

1426

/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */

1438

/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */

1427

writel(0x007F007F, &iomux->gpr[6]);

1439

writel(0x007F007F, &iomux->gpr[6]);

1428

writel(0x007F007F, &iomux->gpr[7]);

1440

writel(0x007F007F, &iomux->gpr[7]);

1429

}

1441

}

1430

}

1442

}

1431

1443

1432

static int mx6q_dcd_table[] = {

1444

static int mx6q_dcd_table[] = {

1433

0x020e0798, 0x000C0000,

1445

0x020e0798, 0x000C0000,

1434

0x020e0758, 0x00000000,

1446

0x020e0758, 0x00000000,

1435

0x020e0588, 0x00000030,

1447

0x020e0588, 0x00000030,

1436

0x020e0594, 0x00000030,

1448

0x020e0594, 0x00000030,

1437

0x020e056c, 0x00000030,

1449

0x020e056c, 0x00000030,

1438

0x020e0578, 0x00000030,

1450

0x020e0578, 0x00000030,

1439

0x020e074c, 0x00000030,

1451

0x020e074c, 0x00000030,

1440

0x020e057c, 0x00000030,

1452

0x020e057c, 0x00000030,

1441

0x020e058c, 0x00000000,

1453

0x020e058c, 0x00000000,

1442

0x020e059c, 0x00000030,

1454

0x020e059c, 0x00000030,

1443

0x020e05a0, 0x00000030,

1455

0x020e05a0, 0x00000030,

1444

0x020e078c, 0x00000030,

1456

0x020e078c, 0x00000030,

1445

0x020e0750, 0x00020000,

1457

0x020e0750, 0x00020000,

1446

0x020e05a8, 0x00000030,

1458

0x020e05a8, 0x00000030,

1447

0x020e05b0, 0x00000030,

1459

0x020e05b0, 0x00000030,

1448

0x020e0524, 0x00000030,

1460

0x020e0524, 0x00000030,

1449

0x020e051c, 0x00000030,

1461

0x020e051c, 0x00000030,

1450

0x020e0518, 0x00000030,

1462

0x020e0518, 0x00000030,

1451

0x020e050c, 0x00000030,

1463

0x020e050c, 0x00000030,

1452

0x020e05b8, 0x00000030,

1464

0x020e05b8, 0x00000030,

1453

0x020e05c0, 0x00000030,

1465

0x020e05c0, 0x00000030,

1454

0x020e0774, 0x00020000,

1466

0x020e0774, 0x00020000,

1455

0x020e0784, 0x00000030,

1467

0x020e0784, 0x00000030,

1456

0x020e0788, 0x00000030,

1468

0x020e0788, 0x00000030,

1457

0x020e0794, 0x00000030,

1469

0x020e0794, 0x00000030,

1458

0x020e079c, 0x00000030,

1470

0x020e079c, 0x00000030,

1459

0x020e07a0, 0x00000030,

1471

0x020e07a0, 0x00000030,

1460

0x020e07a4, 0x00000030,

1472

0x020e07a4, 0x00000030,

1461

0x020e07a8, 0x00000030,

1473

0x020e07a8, 0x00000030,

1462

0x020e0748, 0x00000030,

1474

0x020e0748, 0x00000030,

1463

0x020e05ac, 0x00000030,

1475

0x020e05ac, 0x00000030,

1464

0x020e05b4, 0x00000030,

1476

0x020e05b4, 0x00000030,

1465

0x020e0528, 0x00000030,

1477

0x020e0528, 0x00000030,

1466

0x020e0520, 0x00000030,

1478

0x020e0520, 0x00000030,

1467

0x020e0514, 0x00000030,

1479

0x020e0514, 0x00000030,

1468

0x020e0510, 0x00000030,

1480

0x020e0510, 0x00000030,

1469

0x020e05bc, 0x00000030,

1481

0x020e05bc, 0x00000030,

1470

0x020e05c4, 0x00000030,

1482

0x020e05c4, 0x00000030,

1471

0x021b0800, 0xa1390003,

1483

0x021b0800, 0xa1390003,

1472

0x021b080c, 0x001F001F,

1484

0x021b080c, 0x001F001F,

1473

0x021b0810, 0x001F001F,

1485

0x021b0810, 0x001F001F,

1474

0x021b480c, 0x001F001F,

1486

0x021b480c, 0x001F001F,

1475

0x021b4810, 0x001F001F,

1487

0x021b4810, 0x001F001F,

1476

0x021b083c, 0x43270338,

1488

0x021b083c, 0x43270338,

1477

0x021b0840, 0x03200314,

1489

0x021b0840, 0x03200314,

1478

0x021b483c, 0x431A032F,

1490

0x021b483c, 0x431A032F,

1479

0x021b4840, 0x03200263,

1491

0x021b4840, 0x03200263,

1480

0x021b0848, 0x4B434748,

1492

0x021b0848, 0x4B434748,

1481

0x021b4848, 0x4445404C,

1493

0x021b4848, 0x4445404C,

1482

0x021b0850, 0x38444542,

1494

0x021b0850, 0x38444542,

1483

0x021b4850, 0x4935493A,

1495

0x021b4850, 0x4935493A,

1484

0x021b081c, 0x33333333,

1496

0x021b081c, 0x33333333,

1485

0x021b0820, 0x33333333,

1497

0x021b0820, 0x33333333,

1486

0x021b0824, 0x33333333,

1498

0x021b0824, 0x33333333,

1487

0x021b0828, 0x33333333,

1499

0x021b0828, 0x33333333,

1488

0x021b481c, 0x33333333,

1500

0x021b481c, 0x33333333,

1489

0x021b4820, 0x33333333,

1501

0x021b4820, 0x33333333,

1490

0x021b4824, 0x33333333,

1502

0x021b4824, 0x33333333,

1491

0x021b4828, 0x33333333,

1503

0x021b4828, 0x33333333,

1492

0x021b08b8, 0x00000800,

1504

0x021b08b8, 0x00000800,

1493

0x021b48b8, 0x00000800,

1505

0x021b48b8, 0x00000800,

1494

0x021b0004, 0x00020036,

1506

0x021b0004, 0x00020036,

1495

0x021b0008, 0x09444040,

1507

0x021b0008, 0x09444040,

1496

0x021b000c, 0x555A7975,

1508

0x021b000c, 0x555A7975,

1497

0x021b0010, 0xFF538F64,

1509

0x021b0010, 0xFF538F64,

1498

0x021b0014, 0x01FF00DB,

1510

0x021b0014, 0x01FF00DB,

1499

0x021b0018, 0x00001740,

1511

0x021b0018, 0x00001740,

1500

0x021b001c, 0x00008000,

1512

0x021b001c, 0x00008000,

1501

0x021b002c, 0x000026d2,

1513

0x021b002c, 0x000026d2,

1502

0x021b0030, 0x005A1023,

1514

0x021b0030, 0x005A1023,

1503

0x021b0040, 0x00000027,

1515

0x021b0040, 0x00000027,

1504

0x021b0000, 0x831A0000,

1516

0x021b0000, 0x831A0000,

1505

0x021b001c, 0x04088032,

1517

0x021b001c, 0x04088032,

1506

0x021b001c, 0x00008033,

1518

0x021b001c, 0x00008033,

1507

0x021b001c, 0x00048031,

1519

0x021b001c, 0x00048031,

1508

0x021b001c, 0x09408030,

1520

0x021b001c, 0x09408030,

1509

0x021b001c, 0x04008040,

1521

0x021b001c, 0x04008040,

1510

0x021b0020, 0x00005800,

1522

0x021b0020, 0x00005800,

1511

0x021b0818, 0x00011117,

1523

0x021b0818, 0x00011117,

1512

0x021b4818, 0x00011117,

1524

0x021b4818, 0x00011117,

1513

0x021b0004, 0x00025576,

1525

0x021b0004, 0x00025576,

1514

0x021b0404, 0x00011006,

1526

0x021b0404, 0x00011006,

1515

0x021b001c, 0x00000000,

1527

0x021b001c, 0x00000000,

1516

};

1528

};

1517

1529

1518

static int mx6qp_dcd_table[] = {

1530

static int mx6qp_dcd_table[] = {

1519

0x020e0798, 0x000c0000,

1531

0x020e0798, 0x000c0000,

1520

0x020e0758, 0x00000000,

1532

0x020e0758, 0x00000000,

1521

0x020e0588, 0x00000030,

1533

0x020e0588, 0x00000030,

1522

0x020e0594, 0x00000030,

1534

0x020e0594, 0x00000030,

1523

0x020e056c, 0x00000030,

1535

0x020e056c, 0x00000030,

1524

0x020e0578, 0x00000030,

1536

0x020e0578, 0x00000030,

1525

0x020e074c, 0x00000030,

1537

0x020e074c, 0x00000030,

1526

0x020e057c, 0x00000030,

1538

0x020e057c, 0x00000030,

1527

0x020e058c, 0x00000000,

1539

0x020e058c, 0x00000000,

1528

0x020e059c, 0x00000030,

1540

0x020e059c, 0x00000030,

1529

0x020e05a0, 0x00000030,

1541

0x020e05a0, 0x00000030,

1530

0x020e078c, 0x00000030,

1542

0x020e078c, 0x00000030,

1531

0x020e0750, 0x00020000,

1543

0x020e0750, 0x00020000,

1532

0x020e05a8, 0x00000030,

1544

0x020e05a8, 0x00000030,

1533

0x020e05b0, 0x00000030,

1545

0x020e05b0, 0x00000030,

1534

0x020e0524, 0x00000030,

1546

0x020e0524, 0x00000030,

1535

0x020e051c, 0x00000030,

1547

0x020e051c, 0x00000030,

1536

0x020e0518, 0x00000030,

1548

0x020e0518, 0x00000030,

1537

0x020e050c, 0x00000030,

1549

0x020e050c, 0x00000030,

1538

0x020e05b8, 0x00000030,

1550

0x020e05b8, 0x00000030,

1539

0x020e05c0, 0x00000030,

1551

0x020e05c0, 0x00000030,

1540

0x020e0774, 0x00020000,

1552

0x020e0774, 0x00020000,

1541

0x020e0784, 0x00000030,

1553

0x020e0784, 0x00000030,

1542

0x020e0788, 0x00000030,

1554

0x020e0788, 0x00000030,

1543

0x020e0794, 0x00000030,

1555

0x020e0794, 0x00000030,

1544

0x020e079c, 0x00000030,

1556

0x020e079c, 0x00000030,

1545

0x020e07a0, 0x00000030,

1557

0x020e07a0, 0x00000030,

1546

0x020e07a4, 0x00000030,

1558

0x020e07a4, 0x00000030,

1547

0x020e07a8, 0x00000030,

1559

0x020e07a8, 0x00000030,

1548

0x020e0748, 0x00000030,

1560

0x020e0748, 0x00000030,

1549

0x020e05ac, 0x00000030,

1561

0x020e05ac, 0x00000030,

1550

0x020e05b4, 0x00000030,

1562

0x020e05b4, 0x00000030,

1551

0x020e0528, 0x00000030,

1563

0x020e0528, 0x00000030,

1552

0x020e0520, 0x00000030,

1564

0x020e0520, 0x00000030,

1553

0x020e0514, 0x00000030,

1565

0x020e0514, 0x00000030,

1554

0x020e0510, 0x00000030,

1566

0x020e0510, 0x00000030,

1555

0x020e05bc, 0x00000030,

1567

0x020e05bc, 0x00000030,

1556

0x020e05c4, 0x00000030,

1568

0x020e05c4, 0x00000030,

1557

0x021b0800, 0xa1390003,

1569

0x021b0800, 0xa1390003,

1558

0x021b080c, 0x001b001e,

1570

0x021b080c, 0x001b001e,

1559

0x021b0810, 0x002e0029,

1571

0x021b0810, 0x002e0029,

1560

0x021b480c, 0x001b002a,

1572

0x021b480c, 0x001b002a,

1561

0x021b4810, 0x0019002c,

1573

0x021b4810, 0x0019002c,

1562

0x021b083c, 0x43240334,

1574

0x021b083c, 0x43240334,

1563

0x021b0840, 0x0324031a,

1575

0x021b0840, 0x0324031a,

1564

0x021b483c, 0x43340344,

1576

0x021b483c, 0x43340344,

1565

0x021b4840, 0x03280276,

1577

0x021b4840, 0x03280276,

1566

0x021b0848, 0x44383A3E,

1578

0x021b0848, 0x44383A3E,

1567

0x021b4848, 0x3C3C3846,

1579

0x021b4848, 0x3C3C3846,

1568

0x021b0850, 0x2e303230,

1580

0x021b0850, 0x2e303230,

1569

0x021b4850, 0x38283E34,

1581

0x021b4850, 0x38283E34,

1570

0x021b081c, 0x33333333,

1582

0x021b081c, 0x33333333,

1571

0x021b0820, 0x33333333,

1583

0x021b0820, 0x33333333,

1572

0x021b0824, 0x33333333,

1584

0x021b0824, 0x33333333,

1573

0x021b0828, 0x33333333,

1585

0x021b0828, 0x33333333,

1574

0x021b481c, 0x33333333,

1586

0x021b481c, 0x33333333,

1575

0x021b4820, 0x33333333,

1587

0x021b4820, 0x33333333,

1576

0x021b4824, 0x33333333,

1588

0x021b4824, 0x33333333,

1577

0x021b4828, 0x33333333,

1589

0x021b4828, 0x33333333,

1578

0x021b08c0, 0x24912249,

1590

0x021b08c0, 0x24912249,

1579

0x021b48c0, 0x24914289,

1591

0x021b48c0, 0x24914289,

1580

0x021b08b8, 0x00000800,

1592

0x021b08b8, 0x00000800,

1581

0x021b48b8, 0x00000800,

1593

0x021b48b8, 0x00000800,

1582

0x021b0004, 0x00020036,

1594

0x021b0004, 0x00020036,

1583

0x021b0008, 0x24444040,

1595

0x021b0008, 0x24444040,

1584

0x021b000c, 0x555A7955,

1596

0x021b000c, 0x555A7955,

1585

0x021b0010, 0xFF320F64,

1597

0x021b0010, 0xFF320F64,

1586

0x021b0014, 0x01ff00db,

1598

0x021b0014, 0x01ff00db,

1587

0x021b0018, 0x00001740,

1599

0x021b0018, 0x00001740,

1588

0x021b001c, 0x00008000,

1600

0x021b001c, 0x00008000,

1589

0x021b002c, 0x000026d2,

1601

0x021b002c, 0x000026d2,

1590

0x021b0030, 0x005A1023,

1602

0x021b0030, 0x005A1023,

1591

0x021b0040, 0x00000027,

1603

0x021b0040, 0x00000027,

1592

0x021b0400, 0x14420000,

1604

0x021b0400, 0x14420000,

1593

0x021b0000, 0x831A0000,

1605

0x021b0000, 0x831A0000,

1594

0x021b0890, 0x00400C58,

1606

0x021b0890, 0x00400C58,

1595

0x00bb0008, 0x00000000,

1607

0x00bb0008, 0x00000000,

1596

0x00bb000c, 0x2891E41A,

1608

0x00bb000c, 0x2891E41A,

1597

0x00bb0038, 0x00000564,

1609

0x00bb0038, 0x00000564,

1598

0x00bb0014, 0x00000040,

1610

0x00bb0014, 0x00000040,

1599

0x00bb0028, 0x00000020,

1611

0x00bb0028, 0x00000020,

1600

0x00bb002c, 0x00000020,

1612

0x00bb002c, 0x00000020,

1601

0x021b001c, 0x04088032,

1613

0x021b001c, 0x04088032,

1602

0x021b001c, 0x00008033,

1614

0x021b001c, 0x00008033,

1603

0x021b001c, 0x00048031,

1615

0x021b001c, 0x00048031,

1604

0x021b001c, 0x09408030,

1616

0x021b001c, 0x09408030,

1605

0x021b001c, 0x04008040,

1617

0x021b001c, 0x04008040,

1606

0x021b0020, 0x00005800,

1618

0x021b0020, 0x00005800,

1607

0x021b0818, 0x00011117,

1619

0x021b0818, 0x00011117,

1608

0x021b4818, 0x00011117,

1620

0x021b4818, 0x00011117,

1609

0x021b0004, 0x00025576,

1621

0x021b0004, 0x00025576,

1610

0x021b0404, 0x00011006,

1622

0x021b0404, 0x00011006,

1611

0x021b001c, 0x00000000,

1623

0x021b001c, 0x00000000,

1612

};

1624

};

1613

1625

1614

static void ddr_init(int *table, int size)

1626

static void ddr_init(int *table, int size)

1615

{

1627

{

1616

int i;

1628

int i;

1617

1629

1618

for (i = 0; i < size / 2 ; i++)

1630

for (i = 0; i < size / 2 ; i++)

1619

writel(table[2 * i + 1], table[2 * i]);

1631

writel(table[2 * i + 1], table[2 * i]);

1620

}

1632

}

1621

1633

1622

static void spl_dram_init(void)

1634

static void spl_dram_init(void)

1623

{

1635

{

1624

if (is_mx6dq())

1636

if (is_mx6dq())

1625

ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));

1637

ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));

1626

else if (is_mx6dqp())

1638

else if (is_mx6dqp())

1627

ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));

1639

ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));

1628

}

1640

}

1629

1641

1630

void board_init_f(ulong dummy)

1642

void board_init_f(ulong dummy)

1631

{

1643

{

1632

/* DDR initialization */

1644

/* DDR initialization */

1633

spl_dram_init();

1645

spl_dram_init();

1634

1646

1635

/* setup AIPS and disable watchdog */

1647

/* setup AIPS and disable watchdog */

1636

arch_cpu_init();

1648

arch_cpu_init();

1637

1649

1638

ccgr_init();

1650

ccgr_init();

1639

gpr_init();

1651

gpr_init();

1640

1652

1641

/* iomux and setup of i2c */

1653

/* iomux and setup of i2c */

1642

board_early_init_f();

1654

board_early_init_f();

1643

1655

1644

/* setup GP timer */

1656

/* setup GP timer */

1645

timer_init();

1657

timer_init();

1646

1658

1647

/* UART clocks enabled and gd valid - init serial console */

1659

/* UART clocks enabled and gd valid - init serial console */

1648

preloader_console_init();

1660

preloader_console_init();

1649

1661

1650

/* Clear the BSS. */

1662

/* Clear the BSS. */

1651

memset(__bss_start, 0, __bss_end - __bss_start);

1663

memset(__bss_start, 0, __bss_end - __bss_start);

1652

1664

1653

/* load/boot image from boot device */

1665

/* load/boot image from boot device */

1654

board_init_r(NULL, 0);

1666

board_init_r(NULL, 0);

1655

}

1667

}

GITLAB

MLK-15341 mx6qpsabresd: add PHY AR8031 hw reset

 /*
  * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 #include <asm/arch/mx6-ddr.h>
 #include <usb.h>
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 #include <lcd.h>
 #include <mxc_epdc_fb.h>
 #endif
 #ifdef CONFIG_CMD_SATA
 #include <asm/imx-common/sata.h>
 #endif
 #ifdef CONFIG_FSL_FASTBOOT
 #include <fsl_fastboot.h>
 #ifdef CONFIG_ANDROID_RECOVERY
 #include <recovery.h>
 #endif
 #endif /*CONFIG_FSL_FASTBOOT*/
 DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 #define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define I2C_PMIC	1
 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
 #define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
 #define KEY_VOL_UP	IMX_GPIO_NR(1, 4)
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
 	return 0;
 }
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 static iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	/* AR8031 PHY Reset */
 	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
 };
-static void setup_iomux_enet(void)
+static void fec_phy_reset(void)
 {
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 	/* Reset AR8031 PHY */
 	gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 	udelay(100);
 }
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+	fec_phy_reset();
+}
 static iomux_v3_cfg_t const usdhc2_pads[] = {
 	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 static iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 static iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 #ifdef CONFIG_MXC_SPI
 static iomux_v3_cfg_t const ecspi1_pads[] = {
 	MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static void setup_spi(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 	gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS");
 }
 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 {
 	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 }
 #endif
 static iomux_v3_cfg_t const rgb_pads[] = {
 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static iomux_v3_cfg_t const bl_pads[] = {
 	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static void enable_backlight(void)
 {
 	imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
 	gpio_request(DISP0_PWR_EN, "Display Power Enable");
 	gpio_direction_output(DISP0_PWR_EN, 1);
 }
 static void enable_rgb(struct display_info_t const *dev)
 {
 	imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
 	enable_backlight();
 }
 static void enable_lvds(struct display_info_t const *dev)
 {
 	enable_backlight();
 }
 #ifdef CONFIG_SYS_I2C
 static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
 #endif
 #ifdef CONFIG_PCIE_IMX
 iomux_v3_cfg_t const pcie_pads[] = {
 	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* POWER */
 	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* RESET */
 };
 static void setup_pcie(void)
 {
 	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 	gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");
 	gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");
 }
 #endif
 iomux_v3_cfg_t const di0_pads[] = {
 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	/* DISP0_CLK */
 	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,		/* DISP0_HSYNC */
 	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,		/* DISP0_VSYNC */
 };
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 static iomux_v3_cfg_t const epdc_enable_pads[] = {
 	MX6_PAD_EIM_A16__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA10__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA12__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA11__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_LBA__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_EB2__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_CS0__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_RW__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A21__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A22__EPDC_GDSP	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A23__EPDC_GDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A24__EPDC_GDRL	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_D31__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_D27__EPDC_SDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA1__EPDC_SDLE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_EB1__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA2__EPDC_BDR0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA4__EPDC_SDCE0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA5__EPDC_SDCE1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA6__EPDC_SDCE2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 };
 static iomux_v3_cfg_t const epdc_disable_pads[] = {
 	MX6_PAD_EIM_A16__GPIO2_IO22,
 	MX6_PAD_EIM_DA10__GPIO3_IO10,
 	MX6_PAD_EIM_DA12__GPIO3_IO12,
 	MX6_PAD_EIM_DA11__GPIO3_IO11,
 	MX6_PAD_EIM_LBA__GPIO2_IO27,
 	MX6_PAD_EIM_EB2__GPIO2_IO30,
 	MX6_PAD_EIM_CS0__GPIO2_IO23,
 	MX6_PAD_EIM_RW__GPIO2_IO26,
 	MX6_PAD_EIM_A21__GPIO2_IO17,
 	MX6_PAD_EIM_A22__GPIO2_IO16,
 	MX6_PAD_EIM_A23__GPIO6_IO06,
 	MX6_PAD_EIM_A24__GPIO5_IO04,
 	MX6_PAD_EIM_D31__GPIO3_IO31,
 	MX6_PAD_EIM_D27__GPIO3_IO27,
 	MX6_PAD_EIM_DA1__GPIO3_IO01,
 	MX6_PAD_EIM_EB1__GPIO2_IO29,
 	MX6_PAD_EIM_DA2__GPIO3_IO02,
 	MX6_PAD_EIM_DA4__GPIO3_IO04,
 	MX6_PAD_EIM_DA5__GPIO3_IO05,
 	MX6_PAD_EIM_DA6__GPIO3_IO06,
 };
 #endif
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
 };
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
 int board_mmc_get_env_dev(int devno)
 {
 	return devno - 1;
 }
 int mmc_map_to_kernel_blk(int devno)
 {
 	return devno + 1;
 }
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
 	switch (cfg->esdhc_base) {
 	case USDHC2_BASE_ADDR:
 		ret = !gpio_get_value(USDHC2_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
 		ret = !gpio_get_value(USDHC3_CD_GPIO);
 		break;
 	case USDHC4_BASE_ADDR:
 		ret = 1; /* eMMC/uSDHC4 is always present */
 		break;
 	}
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 #ifndef CONFIG_SPL_BUILD
 	int ret;
 	int i;
 	/*
 	 * According to the board_mmc_init() the following map is done:
 	 * (U-Boot device node)    (Physical Port)
 	 * mmc0                    SD2
 	 * mmc1                    SD3
 	 * mmc2                    eMMC
 	 */
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 			gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 			gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
 			gpio_direction_input(USDHC3_CD_GPIO);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		case 2:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 			       "(%d) then supported by the board (%d)\n",
 			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 			return -EINVAL;
 		}
 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 		if (ret)
 			return ret;
 	}
 	return 0;
 #else
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
 	unsigned reg = readl(&psrc->sbmr1) >> 11;
 	/*
 	 * Upon reading BOOT_CFG register the following map is done:
 	 * Bit 11 and 12 of BOOT_CFG register can determine the current
 	 * mmc port
 	 * 0x1                  SD1
 	 * 0x2                  SD2
 	 * 0x3                  SD4
 	 */
 	switch (reg & 0x3) {
 	case 0x1:
 		imx_iomux_v3_setup_multiple_pads(
 			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 		break;
 	case 0x2:
 		imx_iomux_v3_setup_multiple_pads(
 			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 		break;
 	case 0x3:
 		imx_iomux_v3_setup_multiple_pads(
 			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 		break;
 	}
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 #endif
 }
 #endif
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	if (!is_mx6dqp()) {
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
+		val &= 0xffe3;
-	val |= 0x18;
+		val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+	}
+	/* set the IO voltage to 1.8v */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 	/* introduce tx clock delay */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 	val |= 0x0100;
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 	return 0;
 }
 int board_phy_config(struct phy_device *phydev)
 {
 	ar8031_phy_fixup(phydev);
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
 	return 0;
 }
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 vidinfo_t panel_info = {
 	.vl_refresh = 85,
 	.vl_col = 800,
 	.vl_row = 600,
 	.vl_pixclock = 26666667,
 	.vl_left_margin = 8,
 	.vl_right_margin = 100,
 	.vl_upper_margin = 4,
 	.vl_lower_margin = 8,
 	.vl_hsync = 4,
 	.vl_vsync = 1,
 	.vl_sync = 0,
 	.vl_mode = 0,
 	.vl_flag = 0,
 	.vl_bpix = 3,
 	.cmap = 0,
 };
 struct epdc_timing_params panel_timings = {
 	.vscan_holdoff = 4,
 	.sdoed_width = 10,
 	.sdoed_delay = 20,
 	.sdoez_width = 10,
 	.sdoez_delay = 20,
 	.gdclk_hp_offs = 419,
 	.gdsp_offs = 20,
 	.gdoe_offs = 0,
 	.gdclk_offs = 5,
 	.num_ce = 1,
 };
 static void setup_epdc_power(void)
 {
 	/* Setup epdc voltage */
 	/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as input */
 	gpio_request(IMX_GPIO_NR(2, 21), "EPDC PWRSTAT");
 	gpio_direction_input(IMX_GPIO_NR(2, 21));
 	/* EIM_D17 - GPIO3[17] for VCOM control */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_request(IMX_GPIO_NR(3, 17), "EPDC VCOM0");
 	gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
 	/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_request(IMX_GPIO_NR(3, 20), "EPDC PWR WAKEUP");
 	gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
 	/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_request(IMX_GPIO_NR(2, 20), "EPDC PWR CTRL0");
 	gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
 }
 static void epdc_enable_pins(void)
 {
 	/* epdc iomux settings */
 	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
 				ARRAY_SIZE(epdc_enable_pads));
 }
 static void epdc_disable_pins(void)
 {
 	/* Configure MUX settings for EPDC pins to GPIO */
 	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
 				ARRAY_SIZE(epdc_disable_pads));
 }
 static void setup_epdc(void)
 {
 	unsigned int reg;
 	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	/*** Set pixel clock rates for EPDC ***/
 	/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
 	reg = readl(&ccm_regs->cscdr3);
 	reg &= ~0x7C000;
 	reg |= (1 << 16) | (1 << 14);
 	writel(reg, &ccm_regs->cscdr3);
 	/* EPDC AXI clk enable */
 	reg = readl(&ccm_regs->CCGR3);
 	reg |= 0x00C0;
 	writel(reg, &ccm_regs->CCGR3);
 	/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
 	reg = readl(&ccm_regs->cscdr2);
 	reg &= ~0x3FE00;
 	reg |= (2 << 15) | (5 << 12);
 	writel(reg, &ccm_regs->cscdr2);
 	/* PLL5 enable (defaults to 650) */
 	reg = readl(&ccm_regs->analog_pll_video);
 	reg &= ~((1 << 16) | (1 << 12));
 	reg |= (1 << 13);
 	writel(reg, &ccm_regs->analog_pll_video);
 	/* EPDC PIX clk enable */
 	reg = readl(&ccm_regs->CCGR3);
 	reg |= 0x0C00;
 	writel(reg, &ccm_regs->CCGR3);
 	panel_info.epdc_data.wv_modes.mode_init = 0;
 	panel_info.epdc_data.wv_modes.mode_du = 1;
 	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
 	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
 	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
 	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
 	panel_info.epdc_data.epdc_timings = panel_timings;
 	setup_epdc_power();
 }
 void epdc_power_on(void)
 {
 	unsigned int reg;
 	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
 	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
 	gpio_set_value(IMX_GPIO_NR(2, 20), 1);
 	udelay(1000);
 	/* Enable epdc signal pin */
 	epdc_enable_pins();
 	/* Set PMIC Wakeup to high - enable Display power */
 	gpio_set_value(IMX_GPIO_NR(3, 20), 1);
 	/* Wait for PWRGOOD == 1 */
 	while (1) {
 		reg = readl(&gpio_regs->gpio_psr);
 		if (!(reg & (1 << 21)))
 			break;
 		udelay(100);
 	}
 	/* Enable VCOM */
 	gpio_set_value(IMX_GPIO_NR(3, 17), 1);
 	udelay(500);
 }
 void epdc_power_off(void)
 {
 	/* Set PMIC Wakeup to low - disable Display power */
 	gpio_set_value(IMX_GPIO_NR(3, 20), 0);
 	/* Disable VCOM */
 	gpio_set_value(IMX_GPIO_NR(3, 17), 0);
 	epdc_disable_pins();
 	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
 	gpio_set_value(IMX_GPIO_NR(2, 20), 0);
 }
 #endif
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg = readl(&iomux->gpr[2]);
 	reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 		 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 	writel(reg, &iomux->gpr[2]);
 }
 static void do_enable_hdmi(struct display_info_t const *dev)
 {
 	disable_lvds(dev);
 	imx_enable_hdmi_phy();
 }
 struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB666,
 	.detect	= NULL,
 	.enable	= enable_lvds,
 	.mode	= {
 		.name           = "Hannstar-XGA",
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
 		.pixclock       = 15384,
 		.left_margin    = 160,
 		.right_margin   = 24,
 		.upper_margin   = 29,
 		.lower_margin   = 3,
 		.hsync_len      = 136,
 		.vsync_len      = 6,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
 	.detect	= NULL,
 	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
 		.refresh        = 60,
 		.xres           = 640,
 		.yres           = 480,
 		.pixclock       = 39721,
 		.left_margin    = 48,
 		.right_margin   = 16,
 		.upper_margin   = 33,
 		.lower_margin   = 10,
 		.hsync_len      = 96,
 		.vsync_len      = 2,
 		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
 	.bus	= 0,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
 	.detect	= NULL,
 	.enable	= enable_rgb,
 	.mode	= {
 		.name           = "SEIKO-WVGA",
 		.refresh        = 60,
 		.xres           = 800,
 		.yres           = 480,
 		.pixclock       = 29850,
 		.left_margin    = 89,
 		.right_margin   = 164,
 		.upper_margin   = 23,
 		.lower_margin   = 10,
 		.hsync_len      = 10,
 		.vsync_len      = 10,
 		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 static void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int reg;
 	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 	imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
 	enable_ipu_clock();
 	imx_setup_hdmi();
 	/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 	reg = readl(&mxc_ccm->CCGR3);
 	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 	/* set LDB0, LDB1 clk select to 011/011 */
 	reg = readl(&mxc_ccm->cs2cdr);
 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 	      | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->cs2cdr);
 	reg = readl(&mxc_ccm->cscmr2);
 	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 	writel(reg, &mxc_ccm->cscmr2);
 	reg = readl(&mxc_ccm->chsccdr);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
 	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 	     | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 	     | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 	     | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 	writel(reg, &iomux->gpr[2]);
 	reg = readl(&iomux->gpr[3]);
 	reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 			| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 	       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 	writel(reg, &iomux->gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 /*
  * Do not overwrite the console
  * Use always serial for U-Boot console
  */
 int overwrite_console(void)
 {
 	return 1;
 }
 static void setup_fec(void)
 {
 	if (is_mx6dqp()) {
 		int ret;
 		/* select ENET MAC0 TX clock from PLL */
 		imx_iomux_set_gpr_register(5, 9, 1, 1);
 		ret = enable_fec_anatop_clock(0, ENET_125MHZ);
 		if (ret)
 		    printf("Error fec anatop clock settings!\n");
 	}
+	fec_phy_reset();
 }
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
 	return cpu_eth_init(bis);
 }
 #ifdef CONFIG_USB_EHCI_MX6
 #ifndef CONFIG_DM_USB
 #define USB_OTHERREGS_OFFSET	0x800
 #define UCTRL_PWR_POL		(1 << 9)
 static iomux_v3_cfg_t const usb_otg_pads[] = {
 	MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 };
 static iomux_v3_cfg_t const usb_hc1_pads[] = {
 	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 static void setup_usb(void)
 {
 	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 					 ARRAY_SIZE(usb_otg_pads));
 	/*
 	 * set daisy chain for otg_pin_id on 6q.
 	 * for 6dl, this bit is reserved
 	 */
 	imx_iomux_set_gpr_register(1, 13, 1, 0);
 	imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
 					 ARRAY_SIZE(usb_hc1_pads));
 	gpio_request(IMX_GPIO_NR(1, 29), "USB HC1 Power Enable");
 }
 int board_ehci_hcd_init(int port)
 {
 	u32 *usbnc_usb_ctrl;
 	if (port > 1)
 		return -EINVAL;
 	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 				 port * 4);
 	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 	return 0;
 }
 int board_ehci_power(int port, int on)
 {
 	switch (port) {
 	case 0:
 		break;
 	case 1:
 		if (on)
 			gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
 		else
 			gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
 		break;
 	default:
 		printf("MXC USB port %d not yet supported\n", port);
 		return -EINVAL;
 	}
 	return 0;
 }
 #endif
 #endif
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
 	return 0;
 }
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
 #ifdef CONFIG_SYS_I2C
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif
 #ifdef CONFIG_USB_EHCI_MX6
 #ifndef CONFIG_DM_USB
 	setup_usb();
 #else
 	/*
 	 * set daisy chain for otg_pin_id on 6q.
 	 * for 6dl, this bit is reserved
 	 */
 	imx_iomux_set_gpr_register(1, 13, 1, 0);
 #endif
 #endif
 #ifdef CONFIG_PCIE_IMX
 	setup_pcie();
 #endif
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 	setup_epdc();
 #endif
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
 #ifdef CONFIG_FEC_MXC
 	setup_fec();
 #endif
 	return 0;
 }
 #ifdef CONFIG_POWER
 int power_init_board(void)
 {
 	struct pmic *pfuze;
 	unsigned int reg;
 	int ret;
 	pfuze = pfuze_common_init(I2C_PMIC);
 	if (!pfuze)
 		return -ENODEV;
 	if (is_mx6dqp())
 		ret = pfuze_mode_init(pfuze, APS_APS);
 	else
 		ret = pfuze_mode_init(pfuze, APS_PFM);
 	if (ret < 0)
 		return ret;
 	/* VGEN3 and VGEN5 corrected on i.mx6qp board */
 	if (!is_mx6dqp()) {
 		/* Increase VGEN3 from 2.5 to 2.8V */
 		pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);
 		reg &= ~LDO_VOL_MASK;
 		reg |= LDOB_2_80V;
 		pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
 		/* Increase VGEN5 from 2.8 to 3V */
 		pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
 		reg &= ~LDO_VOL_MASK;
 		reg |= LDOB_3_00V;
 		pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
 	}
 	if (is_mx6dqp()) {
 		/* set SW1C staby volatage 1.075V*/
 		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
 		reg &= ~0x3f;
 		reg |= 0x1f;
 		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
 		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
 		/* set SW2/VDDARM staby volatage 0.975V*/
 		pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);
 		reg &= ~0x3f;
 		reg |= 0x17;
 		pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);
 		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
 		pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);
 	} else {
 		/* set SW1AB staby volatage 0.975V*/
 		pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
 		reg &= ~0x3f;
 		reg |= 0x1b;
 		pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
 		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 		pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
 		/* set SW1C staby volatage 0.975V*/
 		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
 		reg &= ~0x3f;
 		reg |= 0x1b;
 		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
 		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
 	}
 	return 0;
 }
 #elif defined(CONFIG_DM_PMIC_PFUZE100)
 int power_init_board(void)
 {
 	struct udevice *dev;
 	unsigned int reg;
 	int ret;
 	dev = pfuze_common_init();
 	if (!dev)
 		return -ENODEV;
 	if (is_mx6dqp())
 		ret = pfuze_mode_init(dev, APS_APS);
 	else
 		ret = pfuze_mode_init(dev, APS_PFM);
 	if (ret < 0)
 		return ret;
 	/* VGEN3 and VGEN5 corrected on i.mx6qp board */
 	if (!is_mx6dqp()) {
 		/* Increase VGEN3 from 2.5 to 2.8V */
 		reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
 		reg &= ~LDO_VOL_MASK;
 		reg |= LDOB_2_80V;
 		pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
 		/* Increase VGEN5 from 2.8 to 3V */
 		reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
 		reg &= ~LDO_VOL_MASK;
 		reg |= LDOB_3_00V;
 		pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
 	}
 	if (is_mx6dqp()) {
 		/* set SW1C staby volatage 1.075V*/
 		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
 		reg &= ~0x3f;
 		reg |= 0x1f;
 		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
 		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
 		/* set SW2/VDDARM staby volatage 0.975V*/
 		reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
 		reg &= ~0x3f;
 		reg |= 0x17;
 		pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
 		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
 		reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
 	} else {
 		/* set SW1AB staby volatage 0.975V*/
 		reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
 		reg &= ~0x3f;
 		reg |= 0x1b;
 		pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
 		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 		reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
 		/* set SW1C staby volatage 0.975V*/
 		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
 		reg &= ~0x3f;
 		reg |= 0x1b;
 		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
 		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
 		reg &= ~0xc0;
 		reg |= 0x40;
 		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
 	}
 	return 0;
 }
 #endif
 #ifdef CONFIG_LDO_BYPASS_CHECK
 #ifdef CONFIG_POWER
 void ldo_mode_set(int ldo_bypass)
 {
 	unsigned int value;
 	int is_400M;
 	unsigned char vddarm;
 	struct pmic *p = pmic_get("PFUZE100");
 	if (!p) {
 		printf("No PMIC found!\n");
 		return;
 	}
 	/* increase VDDARM/VDDSOC to support 1.2G chip */
 	if (check_1_2G()) {
 		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
 		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
 		if (is_mx6dqp()) {
 			/* increase VDDARM to 1.425V */
 			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
 			value &= ~0x3f;
 			value |= 0x29;
 			pmic_reg_write(p, PFUZE100_SW2VOL, value);
 		} else {
 			/* increase VDDARM to 1.425V */
 			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
 			value &= ~0x3f;
 			value |= 0x2d;
 			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
 		}
 		/* increase VDDSOC to 1.425V */
 		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
 		value &= ~0x3f;
 		value |= 0x2d;
 		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
 	}
 	/* switch to ldo_bypass mode , boot on 800Mhz */
 	if (ldo_bypass) {
 		prep_anatop_bypass();
 		if (is_mx6dqp()) {
 			/* decrease VDDARM for 400Mhz DQP:1.1V*/
 			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
 			value &= ~0x3f;
 			value |= 0x1c;
 			pmic_reg_write(p, PFUZE100_SW2VOL, value);
 		} else {
 			/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
 			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
 			value &= ~0x3f;
 			if (is_mx6dl())
 				value |= 0x27;
 			else
 				value |= 0x20;
 			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
 		}
 		/* increase VDDSOC to 1.3V */
 		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
 		value &= ~0x3f;
 		value |= 0x28;
 		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
 		/*
 		 * MX6Q/DQP:
 		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
 		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
 		 * MX6DL:
 		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
 		 * VDDARM:1.075V@400M; VDDSOC:1.175V@400M
 		 */
 		is_400M = set_anatop_bypass(2);
 		if (is_mx6dqp()) {
 			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
 			value &= ~0x3f;
 			if (is_400M)
 				value |= 0x17;
 			else
 				value |= 0x1e;
 			pmic_reg_write(p, PFUZE100_SW2VOL, value);
 		}
 		if (is_400M) {
 			if (is_mx6dl())
 				vddarm = 0x1f;
 			else
 				vddarm = 0x1b;
 		} else {
 			if (is_mx6dl())
 				vddarm = 0x23;
 			else
 				vddarm = 0x22;
 		}
 		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
 		value &= ~0x3f;
 		value |= vddarm;
 		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
 		/* decrease VDDSOC to 1.175V */
 		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
 		value &= ~0x3f;
 		value |= 0x23;
 		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
 		finish_anatop_bypass();
 		printf("switch to ldo_bypass mode!\n");
 	}
 }
 #elif defined(CONFIG_DM_PMIC_PFUZE100)
 void ldo_mode_set(int ldo_bypass)
 {
 	int is_400M;
 	unsigned char vddarm;
 	struct udevice *dev;
 	int ret;
 	ret = pmic_get("pfuze100", &dev);
 	if (ret == -ENODEV) {
 		printf("No PMIC found!\n");
 		return;
 	}
 	/* increase VDDARM/VDDSOC to support 1.2G chip */
 	if (check_1_2G()) {
 		ldo_bypass = 0; /* ldo_enable on 1.2G chip */
 		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
 		if (is_mx6dqp()) {
 			/* increase VDDARM to 1.425V */
 			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
 		} else {
 			/* increase VDDARM to 1.425V */
 			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
 		}
 		/* increase VDDSOC to 1.425V */
 		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
 	}
 	/* switch to ldo_bypass mode , boot on 800Mhz */
 	if (ldo_bypass) {
 		prep_anatop_bypass();
 		if (is_mx6dqp()) {
 			/* decrease VDDARM for 400Mhz DQP:1.1V*/
 			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c);
 		} else {
 			/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
 			if (is_mx6dl())
 				pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27);
 			else
 				pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);
 		}
 		/* increase VDDSOC to 1.3V */
 		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);
 		/*
 		 * MX6Q/DQP:
 		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
 		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
 		 * MX6DL:
 		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
 		 * VDDARM:1.075V@400M; VDDSOC:1.175V@400M
 		 */
 		is_400M = set_anatop_bypass(2);
 		if (is_mx6dqp()) {
 			if (is_400M)
 				pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17);
 			else
 				pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e);
 		}
 		if (is_400M) {
 			if (is_mx6dl())
 				vddarm = 0x1f;
 			else
 				vddarm = 0x1b;
 		} else {
 			if (is_mx6dl())
 				vddarm = 0x23;
 			else
 				vddarm = 0x22;
 		}
 		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
 		/* decrease VDDSOC to 1.175V */
 		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);
 		finish_anatop_bypass();
 		printf("switch to ldo_bypass mode!\n");
 	}
 }
 #endif
 #endif
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
 	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 	/* 8 bit bus width */
 	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 	{NULL,	 0},
 };
 #endif
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	setenv("board_name", "SABRESD");
 	if (is_mx6dqp())
 		setenv("board_rev", "MX6QP");
 	else if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
 	else if (is_mx6sdl())
 		setenv("board_rev", "MX6DL");
 #endif
 #ifdef CONFIG_ENV_IS_IN_MMC
 	board_late_mmc_env_init();
 #endif
 	return 0;
 }
 int checkboard(void)
 {
 	puts("Board: MX6-SabreSD\n");
 	return 0;
 }
 #ifdef CONFIG_FSL_FASTBOOT
 #ifdef CONFIG_ANDROID_RECOVERY
 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
 iomux_v3_cfg_t const recovery_key_pads[] = {
 	(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 int is_recovery_key_pressing(void)
 {
 	int button_pressed = 0;
 	/* Check Recovery Combo Button press or not. */
 	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
 			ARRAY_SIZE(recovery_key_pads));
 	gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");
 	gpio_direction_input(GPIO_VOL_DN_KEY);
 	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
 		button_pressed = 1;
 		printf("Recovery key pressed\n");
 	}
 	return  button_pressed;
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FSL_FASTBOOT*/
 #ifdef CONFIG_SPL_BUILD
 #include <spl.h>
 #include <libfdt.h>
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
 	gpio_request(KEY_VOL_UP, "KEY Volume UP");
 	gpio_direction_input(KEY_VOL_UP);
 	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
 	return gpio_get_value(KEY_VOL_UP);
 }
 #endif
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	writel(0x00C03F3F, &ccm->CCGR0);
 	writel(0x0030FC03, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
 	writel(0x3FF00000, &ccm->CCGR3);
 	writel(0x00FFF300, &ccm->CCGR4);
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003FF, &ccm->CCGR6);
 }
 static void gpr_init(void)
 {
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	/* enable AXI cache for VDOA/VPU/IPU */
 	writel(0xF00000CF, &iomux->gpr[4]);
 	if (is_mx6dqp()) {
 		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
 		writel(0x007F007F, &iomux->gpr[6]);
 		writel(0x007F007F, &iomux->gpr[7]);
 	} else {
 		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 		writel(0x007F007F, &iomux->gpr[6]);
 		writel(0x007F007F, &iomux->gpr[7]);
 	}
 }
 static int mx6q_dcd_table[] = {
 	0x020e0798, 0x000C0000,
 	0x020e0758, 0x00000000,
 	0x020e0588, 0x00000030,
 	0x020e0594, 0x00000030,
 	0x020e056c, 0x00000030,
 	0x020e0578, 0x00000030,
 	0x020e074c, 0x00000030,
 	0x020e057c, 0x00000030,
 	0x020e058c, 0x00000000,
 	0x020e059c, 0x00000030,
 	0x020e05a0, 0x00000030,
 	0x020e078c, 0x00000030,
 	0x020e0750, 0x00020000,
 	0x020e05a8, 0x00000030,
 	0x020e05b0, 0x00000030,
 	0x020e0524, 0x00000030,
 	0x020e051c, 0x00000030,
 	0x020e0518, 0x00000030,
 	0x020e050c, 0x00000030,
 	0x020e05b8, 0x00000030,
 	0x020e05c0, 0x00000030,
 	0x020e0774, 0x00020000,
 	0x020e0784, 0x00000030,
 	0x020e0788, 0x00000030,
 	0x020e0794, 0x00000030,
 	0x020e079c, 0x00000030,
 	0x020e07a0, 0x00000030,
 	0x020e07a4, 0x00000030,
 	0x020e07a8, 0x00000030,
 	0x020e0748, 0x00000030,
 	0x020e05ac, 0x00000030,
 	0x020e05b4, 0x00000030,
 	0x020e0528, 0x00000030,
 	0x020e0520, 0x00000030,
 	0x020e0514, 0x00000030,
 	0x020e0510, 0x00000030,
 	0x020e05bc, 0x00000030,
 	0x020e05c4, 0x00000030,
 	0x021b0800, 0xa1390003,
 	0x021b080c, 0x001F001F,
 	0x021b0810, 0x001F001F,
 	0x021b480c, 0x001F001F,
 	0x021b4810, 0x001F001F,
 	0x021b083c, 0x43270338,
 	0x021b0840, 0x03200314,
 	0x021b483c, 0x431A032F,
 	0x021b4840, 0x03200263,
 	0x021b0848, 0x4B434748,
 	0x021b4848, 0x4445404C,
 	0x021b0850, 0x38444542,
 	0x021b4850, 0x4935493A,
 	0x021b081c, 0x33333333,
 	0x021b0820, 0x33333333,
 	0x021b0824, 0x33333333,
 	0x021b0828, 0x33333333,
 	0x021b481c, 0x33333333,
 	0x021b4820, 0x33333333,
 	0x021b4824, 0x33333333,
 	0x021b4828, 0x33333333,
 	0x021b08b8, 0x00000800,
 	0x021b48b8, 0x00000800,
 	0x021b0004, 0x00020036,
 	0x021b0008, 0x09444040,
 	0x021b000c, 0x555A7975,
 	0x021b0010, 0xFF538F64,
 	0x021b0014, 0x01FF00DB,
 	0x021b0018, 0x00001740,
 	0x021b001c, 0x00008000,
 	0x021b002c, 0x000026d2,
 	0x021b0030, 0x005A1023,
 	0x021b0040, 0x00000027,
 	0x021b0000, 0x831A0000,
 	0x021b001c, 0x04088032,
 	0x021b001c, 0x00008033,
 	0x021b001c, 0x00048031,
 	0x021b001c, 0x09408030,
 	0x021b001c, 0x04008040,
 	0x021b0020, 0x00005800,
 	0x021b0818, 0x00011117,
 	0x021b4818, 0x00011117,
 	0x021b0004, 0x00025576,
 	0x021b0404, 0x00011006,
 	0x021b001c, 0x00000000,
 };
 static int mx6qp_dcd_table[] = {
 	0x020e0798, 0x000c0000,
 	0x020e0758, 0x00000000,
 	0x020e0588, 0x00000030,
 	0x020e0594, 0x00000030,
 	0x020e056c, 0x00000030,
 	0x020e0578, 0x00000030,
 	0x020e074c, 0x00000030,
 	0x020e057c, 0x00000030,
 	0x020e058c, 0x00000000,
 	0x020e059c, 0x00000030,
 	0x020e05a0, 0x00000030,
 	0x020e078c, 0x00000030,
 	0x020e0750, 0x00020000,
 	0x020e05a8, 0x00000030,
 	0x020e05b0, 0x00000030,
 	0x020e0524, 0x00000030,
 	0x020e051c, 0x00000030,
 	0x020e0518, 0x00000030,
 	0x020e050c, 0x00000030,
 	0x020e05b8, 0x00000030,
 	0x020e05c0, 0x00000030,
 	0x020e0774, 0x00020000,
 	0x020e0784, 0x00000030,
 	0x020e0788, 0x00000030,
 	0x020e0794, 0x00000030,
 	0x020e079c, 0x00000030,
 	0x020e07a0, 0x00000030,
 	0x020e07a4, 0x00000030,
 	0x020e07a8, 0x00000030,
 	0x020e0748, 0x00000030,
 	0x020e05ac, 0x00000030,
 	0x020e05b4, 0x00000030,
 	0x020e0528, 0x00000030,
 	0x020e0520, 0x00000030,
 	0x020e0514, 0x00000030,
 	0x020e0510, 0x00000030,
 	0x020e05bc, 0x00000030,
 	0x020e05c4, 0x00000030,
 	0x021b0800, 0xa1390003,
 	0x021b080c, 0x001b001e,
 	0x021b0810, 0x002e0029,
 	0x021b480c, 0x001b002a,
 	0x021b4810, 0x0019002c,
 	0x021b083c, 0x43240334,
 	0x021b0840, 0x0324031a,
 	0x021b483c, 0x43340344,
 	0x021b4840, 0x03280276,
 	0x021b0848, 0x44383A3E,
 	0x021b4848, 0x3C3C3846,
 	0x021b0850, 0x2e303230,
 	0x021b4850, 0x38283E34,
 	0x021b081c, 0x33333333,
 	0x021b0820, 0x33333333,
 	0x021b0824, 0x33333333,
 	0x021b0828, 0x33333333,
 	0x021b481c, 0x33333333,
 	0x021b4820, 0x33333333,
 	0x021b4824, 0x33333333,
 	0x021b4828, 0x33333333,
 	0x021b08c0, 0x24912249,
 	0x021b48c0, 0x24914289,
 	0x021b08b8, 0x00000800,
 	0x021b48b8, 0x00000800,
 	0x021b0004, 0x00020036,
 	0x021b0008, 0x24444040,
 	0x021b000c, 0x555A7955,
 	0x021b0010, 0xFF320F64,
 	0x021b0014, 0x01ff00db,
 	0x021b0018, 0x00001740,
 	0x021b001c, 0x00008000,
 	0x021b002c, 0x000026d2,
 	0x021b0030, 0x005A1023,
 	0x021b0040, 0x00000027,
 	0x021b0400, 0x14420000,
 	0x021b0000, 0x831A0000,
 	0x021b0890, 0x00400C58,
 	0x00bb0008, 0x00000000,
 	0x00bb000c, 0x2891E41A,
 	0x00bb0038, 0x00000564,
 	0x00bb0014, 0x00000040,
 	0x00bb0028, 0x00000020,
 	0x00bb002c, 0x00000020,
 	0x021b001c, 0x04088032,
 	0x021b001c, 0x00008033,
 	0x021b001c, 0x00048031,
 	0x021b001c, 0x09408030,
 	0x021b001c, 0x04008040,
 	0x021b0020, 0x00005800,
 	0x021b0818, 0x00011117,
 	0x021b4818, 0x00011117,
 	0x021b0004, 0x00025576,
 	0x021b0404, 0x00011006,
 	0x021b001c, 0x00000000,
 };
 static void ddr_init(int *table, int size)
 {
 	int i;
 	for (i = 0; i < size / 2 ; i++)
 		writel(table[2 * i + 1], table[2 * i]);
 }
 static void spl_dram_init(void)
 {
 	if (is_mx6dq())
 		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
 	else if (is_mx6dqp())
 		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
 }
 void board_init_f(ulong dummy)
 {
 	/* DDR initialization */
 	spl_dram_init();
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 	ccgr_init();
 	gpr_init();
 	/* iomux and setup of i2c */
 	board_early_init_f();
 	/* setup GP timer */
 	timer_init();
 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }