Eric Lee / smarc-uboot

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Commit 721193c18f248faa1c892cc64fc656b21b7320b8

Authored by Fugang Duan
1 parent d7a3a0d519
Exists in smarc-n7.1.2_2.0.0-ga and in 2 other branches smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga

MLK-15341 mx6qpsabresd: add PHY AR8031 hw reset 

Currently mx6qpsabresd board file only add PHY AR8031 gpio reset
in non-DM driver, then net DM driver PHY cannot work after stress
reboot test. So also add gpio reset for DM driver.

RGMII and PHY work at VDDIO 1.8V has better timing and to align
the IO voltage with kernel, also set the IO voltage to 1.8V.

Since i.MX6QP tx_clk can loop from SOC internal, no need to set
PHY output 125Mhz clock that can save power.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

Showing 1 changed file with 22 additions and 10 deletions Side-by-side Diff

board/freescale/mx6sabresd/mx6sabresd.c
Diff comments   View file @ 721193c
... ... @@ -111,10 +111,8 @@
111 111 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
112 112 };
113 113  
114   -static void setup_iomux_enet(void)
  114 +static void fec_phy_reset(void)
115 115 {
116   - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
117   -
118 116 /* Reset AR8031 PHY */
119 117 gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset");
120 118 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
... ... @@ -123,6 +121,12 @@
123 121 udelay(100);
124 122 }
125 123  
  124 +static void setup_iomux_enet(void)
  125 +{
  126 + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  127 + fec_phy_reset();
  128 +}
  129 +
126 130 static iomux_v3_cfg_t const usdhc2_pads[] = {
127 131 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 132 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 133  
130 134  
... ... @@ -459,15 +463,21 @@
459 463 unsigned short val;
460 464  
461 465 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
462   - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
463   - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
464   - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  466 + if (!is_mx6dqp()) {
  467 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  468 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  469 + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
465 470  
466   - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
467   - val &= 0xffe3;
468   - val |= 0x18;
469   - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  471 + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  472 + val &= 0xffe3;
  473 + val |= 0x18;
  474 + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  475 + }
470 476  
  477 + /* set the IO voltage to 1.8v */
  478 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  479 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  480 +
471 481 /* introduce tx clock delay */
472 482 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
473 483 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
... ... @@ -817,6 +827,8 @@
817 827 if (ret)
818 828 printf("Error fec anatop clock settings!\n");
819 829 }
  830 +
  831 + fec_phy_reset();
820 832 }
821 833  
822 834 int board_eth_init(bd_t *bis)