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Commit 7211fbfa18f3061858696150ee6e9e093d9eceae

Authored by Haiying Wang
Committed by Kumar Gala
1 parent b3d7f20f43
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs 

Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 5 changed files with 52 additions and 12 deletions Side-by-side Diff

... ... @@ -258,9 +258,6 @@
258 258 return 0;
259 259 }
260 260  
261   -/* The maximum number of RISCs we support */
262   -#define MAX_QE_RISC 2
263   -
264 261 /* Firmware information stored here for qe_get_firmware_info() */
265 262 static struct qe_firmware_info qe_firmware_info;
266 263  
1 1 /*
2   - * Copyright (C) 2006 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3 3 *
4 4 * Dave Liu <daveliu@freescale.com>
5 5 * based on source code of Shlomi Gridish
... ... @@ -46,11 +46,16 @@
46 46  
47 47 /* QE RISC allocation
48 48 */
49   -typedef enum qe_risc_allocation {
50   - QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
51   - QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
52   - QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
53   -} qe_risc_allocation_e;
  49 +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
  50 +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
  51 +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
  52 +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
  53 +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
  54 + QE_RISC_ALLOCATION_RISC2)
  55 +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
  56 + QE_RISC_ALLOCATION_RISC2 | \
  57 + QE_RISC_ALLOCATION_RISC3 | \
  58 + QE_RISC_ALLOCATION_RISC4)
54 59  
55 60 /* QE CECR commands for UCC fast.
56 61 */
1 1 /*
2   - * Copyright (C) 2006 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3 3 *
4 4 * Dave Liu <daveliu@freescale.com>
5 5 *
6 6  
... ... @@ -46,8 +46,13 @@
46 46 .num_threads_tx = UEC_NUM_OF_THREADS_4,
47 47 .num_threads_rx = UEC_NUM_OF_THREADS_4,
48 48 #endif
  49 +#if (MAX_QE_RISC == 4)
  50 + .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
  51 + .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
  52 +#else
49 53 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
50 54 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  55 +#endif
51 56 .tx_bd_ring_len = 16,
52 57 .rx_bd_ring_len = 16,
53 58 .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
54 59  
... ... @@ -69,8 +74,13 @@
69 74 .num_threads_tx = UEC_NUM_OF_THREADS_4,
70 75 .num_threads_rx = UEC_NUM_OF_THREADS_4,
71 76 #endif
  77 +#if (MAX_QE_RISC == 4)
  78 + .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
  79 + .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
  80 +#else
72 81 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
73 82 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  83 +#endif
74 84 .tx_bd_ring_len = 16,
75 85 .rx_bd_ring_len = 16,
76 86 .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
77 87  
... ... @@ -92,8 +102,13 @@
92 102 .num_threads_tx = UEC_NUM_OF_THREADS_4,
93 103 .num_threads_rx = UEC_NUM_OF_THREADS_4,
94 104 #endif
  105 +#if (MAX_QE_RISC == 4)
  106 + .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
  107 + .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
  108 +#else
95 109 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
96 110 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  111 +#endif
97 112 .tx_bd_ring_len = 16,
98 113 .rx_bd_ring_len = 16,
99 114 .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
100 115  
... ... @@ -115,8 +130,13 @@
115 130 .num_threads_tx = UEC_NUM_OF_THREADS_4,
116 131 .num_threads_rx = UEC_NUM_OF_THREADS_4,
117 132 #endif
  133 +#if (MAX_QE_RISC == 4)
  134 + .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
  135 + .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
  136 +#else
118 137 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
119 138 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  139 +#endif
120 140 .tx_bd_ring_len = 16,
121 141 .rx_bd_ring_len = 16,
122 142 .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
123 143  
... ... @@ -138,8 +158,13 @@
138 158 .num_threads_tx = UEC_NUM_OF_THREADS_4,
139 159 .num_threads_rx = UEC_NUM_OF_THREADS_4,
140 160 #endif
  161 +#if (MAX_QE_RISC == 4)
  162 + .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
  163 + .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
  164 +#else
141 165 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
142 166 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  167 +#endif
143 168 .tx_bd_ring_len = 16,
144 169 .rx_bd_ring_len = 16,
145 170 .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
146 171  
... ... @@ -161,8 +186,13 @@
161 186 .num_threads_tx = UEC_NUM_OF_THREADS_4,
162 187 .num_threads_rx = UEC_NUM_OF_THREADS_4,
163 188 #endif
  189 +#if (MAX_QE_RISC == 4)
  190 + .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
  191 + .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
  192 +#else
164 193 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
165 194 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  195 +#endif
166 196 .tx_bd_ring_len = 16,
167 197 .rx_bd_ring_len = 16,
168 198 .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
... ... @@ -654,8 +654,8 @@
654 654 ucc_fast_info_t uf_info;
655 655 uec_num_of_threads_e num_threads_tx;
656 656 uec_num_of_threads_e num_threads_rx;
657   - qe_risc_allocation_e risc_tx;
658   - qe_risc_allocation_e risc_rx;
  657 + unsigned int risc_tx;
  658 + unsigned int risc_rx;
659 659 u16 rx_bd_ring_len;
660 660 u16 tx_bd_ring_len;
661 661 u8 phy_address;
include/asm-ppc/immap_qe.h
Diff comments   View file @ 7211fbf
... ... @@ -607,5 +607,13 @@
607 607 #define QE_MURAM_SIZE 0x4000UL
608 608 #endif
609 609  
  610 +#if defined(CONFIG_MPC8323)
  611 +#define MAX_QE_RISC 1
  612 +#elif defined(CONFIG_MPC8569)
  613 +#define MAX_QE_RISC 4
  614 +#else
  615 +#define MAX_QE_RISC 2
  616 +#endif
  617 +
610 618 #endif /* __IMMAP_QE_H__ */