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Commit 7237d22baac9ebeffc946dfd30b9f61aaf0bfdbc

Authored by Sergey Kostanbaev
Committed by Albert ARIBAUD
1 parent c0c374024d
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: ep9315: Return back Cirrus Logic EDB9315A board support 

This patch returns back support for old ep93xx processors family

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net

Showing 11 changed files with 1636 additions and 27 deletions Side-by-side Diff

arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
Diff comments   View file @ 7237d22
... ... @@ -2,49 +2,458 @@
2 2 * Low-level initialization for EP93xx
3 3 *
4 4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
  5 + * Copyright (C) 2013
  6 + * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
5 7 *
6 8 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
  9 + * Copyright (C) 2006 Cirrus Logic Inc.
7 10 *
  11 + * See file CREDITS for list of people who contributed to this
  12 + * project.
  13 + *
8 14 * SPDX-License-Identifier: GPL-2.0+
9 15 */
10 16  
11   -#include <version.h>
12   -#include <asm/arch/ep93xx.h>
  17 +#include <config.h>
  18 +#include <asm/arch-ep93xx/ep93xx.h>
13 19  
  20 +/*
  21 +/* Configure the SDRAM based on the supplied settings.
  22 + *
  23 + * Input: r0 - SDRAM DEVCFG register
  24 + * r2 - configuration for SDRAM chips
  25 + * Output: none
  26 + * Modifies: r3, r4
  27 + */
  28 +ep93xx_sdram_config:
  29 + /* Program the SDRAM device configuration register. */
  30 + ldr r3, =SDRAM_BASE
  31 +#ifdef CONFIG_EDB93XX_SDCS0
  32 + str r0, [r3, #SDRAM_OFF_DEVCFG0]
  33 +#endif
  34 +#ifdef CONFIG_EDB93XX_SDCS1
  35 + str r0, [r3, #SDRAM_OFF_DEVCFG1]
  36 +#endif
  37 +#ifdef CONFIG_EDB93XX_SDCS2
  38 + str r0, [r3, #SDRAM_OFF_DEVCFG2]
  39 +#endif
  40 +#ifdef CONFIG_EDB93XX_SDCS3
  41 + str r0, [r3, #SDRAM_OFF_DEVCFG3]
  42 +#endif
  43 +
  44 + /* Set the Initialize and MRS bits (issue continuous NOP commands
  45 + * (INIT & MRS set))
  46 + */
  47 + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
  48 + EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
  49 + EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
  50 + str r4, [r3, #SDRAM_OFF_GLCONFIG]
  51 +
  52 + /* Delay for 200us. */
  53 + mov r4, #0x3000
  54 +delay1:
  55 + subs r4, r4, #1
  56 + bne delay1
  57 +
  58 + /* Clear the MRS bit to issue a precharge all. */
  59 + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
  60 + EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
  61 + str r4, [r3, #SDRAM_OFF_GLCONFIG]
  62 +
  63 + /* Temporarily set the refresh timer to 0x10. Make it really low so
  64 + * that refresh cycles are generated.
  65 + */
  66 + ldr r4, =0x10
  67 + str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
  68 +
  69 + /* Delay for at least 80 SDRAM clock cycles. */
  70 + mov r4, #80
  71 +delay2:
  72 + subs r4, r4, #1
  73 + bne delay2
  74 +
  75 + /* Set the refresh timer to the fastest required for any device
  76 + * that might be used. Set 9.6 ms refresh time.
  77 + */
  78 + ldr r4, =0x01e0
  79 + str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
  80 +
  81 + /* Select mode register update mode. */
  82 + ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
  83 + EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
  84 + str r4, [r3, #SDRAM_OFF_GLCONFIG]
  85 +
  86 + /* Program the mode register on the SDRAM by performing fake read */
  87 + ldr r4, [r2]
  88 +
  89 + /* Select normal operating mode. */
  90 + ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
  91 + str r4, [r3, #SDRAM_OFF_GLCONFIG]
  92 +
  93 + /* Return to the caller. */
  94 + mov pc, lr
  95 +
  96 +/*
  97 + * Test to see if the SDRAM has been configured in a usable mode.
  98 + *
  99 + * Input: r0 - Test address of SDRAM
  100 + * Output: r0 - 0 -- Test OK, -1 -- Failed
  101 + * Modifies: r0-r5
  102 + */
  103 +ep93xx_sdram_test:
  104 + /* Load the test patterns to be written to SDRAM. */
  105 + ldr r1, =0xf00dface
  106 + ldr r2, =0xdeadbeef
  107 + ldr r3, =0x08675309
  108 + ldr r4, =0xdeafc0ed
  109 +
  110 + /* Store the test patterns to SDRAM. */
  111 + stmia r0, {r1-r4}
  112 +
  113 + /* Load the test patterns from SDRAM one at a time and compare them
  114 + * to the actual pattern.
  115 + */
  116 + ldr r5, [r0]
  117 + cmp r5, r1
  118 + ldreq r5, [r0, #0x0004]
  119 + cmpeq r5, r2
  120 + ldreq r5, [r0, #0x0008]
  121 + cmpeq r5, r3
  122 + ldreq r5, [r0, #0x000c]
  123 + cmpeq r5, r4
  124 +
  125 + /* Return -1 if a mismatch was encountered, 0 otherwise. */
  126 + mvnne r0, #0xffffffff
  127 + moveq r0, #0x00000000
  128 +
  129 + /* Return to the caller. */
  130 + mov pc, lr
  131 +
  132 +/*
  133 + * Determine the size of the SDRAM. Use data=address for the scan.
  134 + *
  135 + * Input: r0 - Start SDRAM address
  136 + * Return: r0 - Single block size
  137 + * r1 - Valid block mask
  138 + * r2 - Total block count
  139 + * Modifies: r0-r5
  140 + */
  141 +ep93xx_sdram_size:
  142 + /* Store zero at offset zero. */
  143 + str r0, [r0]
  144 +
  145 + /* Start checking for an alias at 1MB into SDRAM. */
  146 + ldr r1, =0x00100000
  147 +
  148 + /* Store the offset at the current offset. */
  149 +check_block_size:
  150 + str r1, [r0, r1]
  151 +
  152 + /* Read back from zero. */
  153 + ldr r2, [r0]
  154 +
  155 + /* Stop searching of an alias was found. */
  156 + cmp r1, r2
  157 + beq found_block_size
  158 +
  159 + /* Advance to the next power of two boundary. */
  160 + mov r1, r1, lsl #1
  161 +
  162 + /* Loop back if the size has not reached 256MB. */
  163 + cmp r1, #0x10000000
  164 + bne check_block_size
  165 +
  166 + /* A full 256MB of memory was found, so return it now. */
  167 + ldr r0, =0x10000000
  168 + ldr r1, =0x00000000
  169 + ldr r2, =0x00000001
  170 + mov pc, lr
  171 +
  172 + /* An alias was found. See if the first block is 128MB in size. */
  173 +found_block_size:
  174 + cmp r1, #0x08000000
  175 +
  176 + /* The first block is 128MB, so there is no further memory. Return it
  177 + * now.
  178 + */
  179 + ldreq r0, =0x08000000
  180 + ldreq r1, =0x00000000
  181 + ldreq r2, =0x00000001
  182 + moveq pc, lr
  183 +
  184 + /* Save the block size, set the block address bits to zero, and
  185 + * initialize the block count to one.
  186 + */
  187 + mov r3, r1
  188 + ldr r4, =0x00000000
  189 + ldr r5, =0x00000001
  190 +
  191 + /* Look for additional blocks of memory by searching for non-aliases. */
  192 +find_blocks:
  193 + /* Store zero back to address zero. It may be overwritten. */
  194 + str r0, [r0]
  195 +
  196 + /* Advance to the next power of two boundary. */
  197 + mov r1, r1, lsl #1
  198 +
  199 + /* Store the offset at the current offset. */
  200 + str r1, [r0, r1]
  201 +
  202 + /* Read back from zero. */
  203 + ldr r2, [r0]
  204 +
  205 + /* See if a non-alias was found. */
  206 + cmp r1, r2
  207 +
  208 + /* If a non-alias was found, then or in the block address bit and
  209 + * multiply the block count by two (since there are two unique
  210 + * blocks, one with this bit zero and one with it one).
  211 + */
  212 + orrne r4, r4, r1
  213 + movne r5, r5, lsl #1
  214 +
  215 + /* Continue searching if there are more address bits to check. */
  216 + cmp r1, #0x08000000
  217 + bne find_blocks
  218 +
  219 + /* Return the block size, address mask, and count. */
  220 + mov r0, r3
  221 + mov r1, r4
  222 + mov r2, r5
  223 +
  224 + /* Return to the caller. */
  225 + mov pc, lr
  226 +
  227 +
14 228 .globl lowlevel_init
15 229 lowlevel_init:
16   - /* backup return address */
17   - ldr r1, =SYSCON_SCRATCH0
18   - str lr, [r1]
19 230  
20   - /* Turn on both LEDs */
21   - bl red_led_on
22   - bl green_led_on
  231 + mov r6, lr
23 232  
24   - /* Configure flash wait states before we switch to the PLL */
25   - bl flash_cfg
  233 + /* Make sure caches are off and invalidated. */
  234 + ldr r0, =0x00000000
  235 + mcr p15, 0, r0, c1, c0, 0
  236 + nop
  237 + nop
  238 + nop
  239 + nop
  240 + nop
26 241  
27   - /* Set up PLL */
28   - bl pll_cfg
  242 + /* Turn off the green LED and turn on the red LED. If the red LED
  243 + * is left on for too long, the external reset circuit described
  244 + * by application note AN258 will cause the system to reset.
  245 + */
  246 + ldr r1, =EP93XX_LED_DATA
  247 + ldr r0, [r1]
  248 + bic r0, r0, #EP93XX_LED_GREEN_ON
  249 + orr r0, r0, #EP93XX_LED_RED_ON
  250 + str r0, [r1]
29 251  
30   - /* Turn off the Green LED and leave the Red LED on */
31   - bl green_led_off
  252 + /* Undo the silly static memory controller programming performed
  253 + * by the boot rom.
  254 + */
  255 + ldr r0, =SMC_BASE
32 256  
33   - /* Setup SDRAM */
34   - bl sdram_cfg
  257 + /* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
  258 + ldr r1, =0x0000fbe0
35 259  
36   - /* Turn on Green LED, Turn off the Red LED */
37   - bl green_led_on
38   - bl red_led_off
  260 + /* Reset EP93XX_OFF_SMCBCR0 */
  261 + ldr r2, [r0]
  262 + orr r2, r2, r1
  263 + str r2, [r0]
39 264  
40   - /* FIXME: we use async mode for now */
41   - mrc p15, 0, r0, c1, c0, 0
42   - orr r0, r0, #0xc0000000
43   - mcr p15, 0, r0, c1, c0, 0
  265 + ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
  266 + orr r2, r2, r1
  267 + str r2, [r0, #EP93XX_OFF_SMCBCR1]
44 268  
45   - /* restore return address */
46   - ldr r1, =SYSCON_SCRATCH0
47   - ldr lr, [r1]
  269 + ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
  270 + orr r2, r2, r1
  271 + str r2, [r0, #EP93XX_OFF_SMCBCR2]
48 272  
49   - mov pc, lr
  273 + ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
  274 + orr r2, r2, r1
  275 + str r2, [r0, #EP93XX_OFF_SMCBCR3]
  276 +
  277 + ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
  278 + orr r2, r2, r1
  279 + str r2, [r0, #EP93XX_OFF_SMCBCR6]
  280 +
  281 + ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
  282 + orr r2, r2, r1
  283 + str r2, [r0, #EP93XX_OFF_SMCBCR7]
  284 +
  285 + /* Set the PLL1 and processor clock. */
  286 + ldr r0, =SYSCON_BASE
  287 +#ifdef CONFIG_EDB9301
  288 + /* 332MHz, giving a 166MHz processor clock. */
  289 + ldr r1, = 0x02b49907
  290 +#else
  291 +
  292 +#ifdef CONFIG_EDB93XX_INDUSTRIAL
  293 + /* 384MHz, giving a 196MHz processor clock. */
  294 + ldr r1, =0x02a4bb38
  295 +#else
  296 + /* 400MHz, giving a 200MHz processor clock. */
  297 + ldr r1, =0x02a4e39e
  298 +#endif
  299 +#endif
  300 + str r1, [r0, #SYSCON_OFF_CLKSET1]
  301 +
  302 + nop
  303 + nop
  304 + nop
  305 + nop
  306 + nop
  307 +
  308 + /* Need to make sure that SDRAM is configured correctly before
  309 + * coping the code into it.
  310 + */
  311 +
  312 +#ifdef CONFIG_EDB93XX_SDCS0
  313 + mov r11, #SDRAM_DEVCFG0_BASE
  314 +#endif
  315 +#ifdef CONFIG_EDB93XX_SDCS1
  316 + mov r11, #SDRAM_DEVCFG1_BASE
  317 +#endif
  318 +#ifdef CONFIG_EDB93XX_SDCS2
  319 + mov r11, #SDRAM_DEVCFG2_BASE
  320 +#endif
  321 +#ifdef CONFIG_EDB93XX_SDCS3
  322 + ldr r0, =SYSCON_BASE
  323 + ldr r0, [r0, #SYSCON_OFF_SYSCFG]
  324 + ands r0, r0, #SYSCON_SYSCFG_LASDO
  325 + moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
  326 + movne r11, #SDRAM_DEVCFG3_ASD1_BASE
  327 +#endif
  328 + /* See Table 13-5 in EP93xx datasheet for more info about DRAM
  329 + * register mapping */
  330 +
  331 + /* Try a 32-bit wide configuration of SDRAM. */
  332 + ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
  333 + EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
  334 + EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
  335 + EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
  336 +
  337 + /* Set burst count: 4 and CAS: 2
  338 + * Burst mode [A11:A10]; CAS [A16:A14]
  339 + */
  340 + orr r2, r11, #0x00008800
  341 + bl ep93xx_sdram_config
  342 +
  343 + /* Test the SDRAM. */
  344 + mov r0, r11
  345 + bl ep93xx_sdram_test
  346 + cmp r0, #0x00000000
  347 + beq ep93xx_sdram_done
  348 +
  349 + /* Try a 16-bit wide configuration of SDRAM. */
  350 + ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
  351 + EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
  352 + EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
  353 + EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
  354 + EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
  355 +
  356 + /* Set burst count: 8, CAS: 2, sequential burst
  357 + * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
  358 + * Burst mode [A10:A9]; CAS [A15:A13]
  359 + */
  360 + orr r2, r11, #0x00004600
  361 + bl ep93xx_sdram_config
  362 +
  363 + /* Test the SDRAM. */
  364 + mov r0, r11
  365 + bl ep93xx_sdram_test
  366 + cmp r0, #0x00000000
  367 + beq ep93xx_sdram_done
  368 +
  369 + /* Turn off the red LED. */
  370 + ldr r0, =EP93XX_LED_DATA
  371 + ldr r1, [r0]
  372 + bic r1, r1, #EP93XX_LED_RED_ON
  373 + str r1, [r0]
  374 +
  375 + /* There is no SDRAM so flash the green LED. */
  376 +flash_green:
  377 + orr r1, r1, #EP93XX_LED_GREEN_ON
  378 + str r1, [r0]
  379 + ldr r2, =0x00010000
  380 +flash_green_delay_1:
  381 + subs r2, r2, #1
  382 + bne flash_green_delay_1
  383 + bic r1, r1, #EP93XX_LED_GREEN_ON
  384 + str r1, [r0]
  385 + ldr r2, =0x00010000
  386 +flash_green_delay_2:
  387 + subs r2, r2, #1
  388 + bne flash_green_delay_2
  389 + orr r1, r1, #EP93XX_LED_GREEN_ON
  390 + str r1, [r0]
  391 + ldr r2, =0x00010000
  392 +flash_green_delay_3:
  393 + subs r2, r2, #1
  394 + bne flash_green_delay_3
  395 + bic r1, r1, #EP93XX_LED_GREEN_ON
  396 + str r1, [r0]
  397 + ldr r2, =0x00050000
  398 +flash_green_delay_4:
  399 + subs r2, r2, #1
  400 + bne flash_green_delay_4
  401 + b flash_green
  402 +
  403 +
  404 +ep93xx_sdram_done:
  405 + ldr r1, =EP93XX_LED_DATA
  406 + ldr r0, [r1]
  407 + bic r0, r0, #EP93XX_LED_RED_ON
  408 + str r0, [r1]
  409 +
  410 + /* Determine the size of the SDRAM. */
  411 + mov r0, r11
  412 + bl ep93xx_sdram_size
  413 +
  414 + /* Save the SDRAM characteristics. */
  415 + mov r8, r0
  416 + mov r9, r1
  417 + mov r10, r2
  418 +
  419 + /* Compute total memory size into r1 */
  420 + mul r1, r8, r10
  421 +#ifdef CONFIG_EDB93XX_SDCS0
  422 + ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
  423 +#endif
  424 +#ifdef CONFIG_EDB93XX_SDCS1
  425 + ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
  426 +#endif
  427 +#ifdef CONFIG_EDB93XX_SDCS2
  428 + ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
  429 +#endif
  430 +#ifdef CONFIG_EDB93XX_SDCS3
  431 + ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
  432 +#endif
  433 +
  434 + /* Consider small DRAM size as:
  435 + * < 32Mb for 32bit bus
  436 + * < 64Mb for 16bit bus
  437 + */
  438 + tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
  439 + moveq r1, r1, lsr #1
  440 + cmp r1, #0x02000000
  441 +
  442 +#if defined(CONFIG_EDB9301)
  443 + /* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
  444 + movlt r1, #0x03f0
  445 + movge r1, #0x01e0
  446 +#else
  447 + /* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
  448 + movlt r1, #0x0600
  449 + movge r1, #0x2f0
  450 +#endif
  451 + str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
  452 +
  453 + /* Save the memory configuration information. */
  454 + orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
  455 + stmia r0, {r8-r11}
  456 +
  457 + mov lr, r6
  458 + mov pc, lr
arch/arm/include/asm/arch-ep93xx/ep93xx.h
Diff comments   View file @ 7237d22
1 1 /*
2 2 * Cirrus Logic EP93xx register definitions.
3 3 *
  4 + * Copyright (C) 2013
  5 + * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
  6 + *
4 7 * Copyright (C) 2009
5 8 * Matthias Kaehlcke <matthias@kaehlcke.net>
6 9 *
... ... @@ -287,6 +290,20 @@
287 290 #define SDRAM_DEVCFG_CASLAT_2 0x00010000
288 291 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
289 292  
  293 +#define SDRAM_OFF_GLCONFIG 0x0004
  294 +#define SDRAM_OFF_REFRSHTIMR 0x0008
  295 +
  296 +#define SDRAM_OFF_DEVCFG0 0x0010
  297 +#define SDRAM_OFF_DEVCFG1 0x0014
  298 +#define SDRAM_OFF_DEVCFG2 0x0018
  299 +#define SDRAM_OFF_DEVCFG3 0x001C
  300 +
  301 +#define SDRAM_DEVCFG0_BASE 0xC0000000
  302 +#define SDRAM_DEVCFG1_BASE 0xD0000000
  303 +#define SDRAM_DEVCFG2_BASE 0xE0000000
  304 +#define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
  305 +#define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
  306 +
290 307 #define GLCONFIG_INIT (1 << 0)
291 308 #define GLCONFIG_MRS (1 << 1)
292 309 #define GLCONFIG_SMEMBUSY (1 << 5)
... ... @@ -295,6 +312,43 @@
295 312 #define GLCONFIG_CLKSHUTDOWN (1 << 30)
296 313 #define GLCONFIG_CKE (1 << 31)
297 314  
  315 +#define EP93XX_SDRAMCTRL 0x80060000
  316 +#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
  317 +#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
  318 +#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
  319 +#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
  320 +#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
  321 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
  322 +#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
  323 +
  324 +#define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
  325 +
  326 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
  327 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
  328 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
  329 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
  330 +#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
  331 +
  332 +#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
  333 +#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
  334 +#define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
  335 +#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
  336 +#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
  337 +#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
  338 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
  339 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
  340 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
  341 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
  342 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
  343 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
  344 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
  345 +#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
  346 +#define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
  347 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
  348 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
  349 +#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
  350 +#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
  351 +
298 352 /*
299 353 * 0x80070000 - 0x8007FFFF: Reserved
300 354 */
... ... @@ -324,6 +378,13 @@
324 378 };
325 379 #endif
326 380  
  381 +#define EP93XX_OFF_SMCBCR0 0x00
  382 +#define EP93XX_OFF_SMCBCR1 0x04
  383 +#define EP93XX_OFF_SMCBCR2 0x08
  384 +#define EP93XX_OFF_SMCBCR3 0x0C
  385 +#define EP93XX_OFF_SMCBCR6 0x18
  386 +#define EP93XX_OFF_SMCBCR7 0x1C
  387 +
327 388 #define SMC_BCR_IDCY_SHIFT 0
328 389 #define SMC_BCR_WST1_SHIFT 5
329 390 #define SMC_BCR_BLE (1 << 10)
... ... @@ -445,6 +506,14 @@
445 506 };
446 507 #endif
447 508  
  509 +#define EP93XX_LED_DATA 0x80840020
  510 +#define EP93XX_LED_GREEN_ON 0x0001
  511 +#define EP93XX_LED_RED_ON 0x0002
  512 +
  513 +#define EP93XX_LED_DDR 0x80840024
  514 +#define EP93XX_LED_GREEN_ENABLE 0x0001
  515 +#define EP93XX_LED_RED_ENABLE 0x00020000
  516 +
448 517 /*
449 518 * 0x80850000 - 0x8087FFFF: Reserved
450 519 */
... ... @@ -519,6 +588,9 @@
519 588 #define SYSCON_OFFSET 0x930000
520 589 #define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
521 590  
  591 +/* Security */
  592 +#define SECURITY_EXTENSIONID 0x80832714
  593 +
522 594 #ifndef __ASSEMBLY__
523 595 struct syscon_regs {
524 596 uint32_t pwrsts;
525 597  
... ... @@ -553,7 +625,11 @@
553 625 #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
554 626 #endif
555 627  
  628 +#define SYSCON_OFF_CLKSET1 0x0020
  629 +#define SYSCON_OFF_SYSCFG 0x009c
  630 +
556 631 #define SYSCON_PWRCNT_UART_BAUD (1 << 29)
  632 +#define SYSCON_PWRCNT_USH_EN (1 << 28)
557 633  
558 634 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
559 635 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
... ... @@ -571,6 +647,8 @@
571 647 #define SYSCON_CHIPID_REV_MASK 0xF0000000
572 648 #define SYSCON_DEVICECFG_SWRST (1 << 31)
573 649  
  650 +#define SYSCON_SYSCFG_LASDO 0x00000020
  651 +
574 652 /*
575 653 * 0x80930000 - 0x8093FFFF: Watchdog Timer
576 654 */
... ... @@ -580,4 +658,11 @@
580 658 /*
581 659 * 0x80950000 - 0x9000FFFF: Reserved
582 660 */
  661 +
  662 +/*
  663 + * During low_level init we store memory layout in memory at specific location
  664 + */
  665 +#define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
  666 +#define UBOOT_MEMORYCNF_BANK_MASK 0x2004
  667 +#define UBOOT_MEMORYCNF_BANK_COUNT 0x2008
board/cirrus/edb93xx/Makefile
Diff comments   View file @ 7237d22
  1 +#
  2 +# (C) Copyright 2013
  3 +# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
  4 +#
  5 +# (C) Copyright 2003-2006
  6 +# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
  7 +#
  8 +# * SPDX-License-Identifier: GPL-2.0+
  9 +#
  10 +
  11 +obj-y := edb93xx.o
board/cirrus/edb93xx/edb93xx.c
Diff comments   View file @ 7237d22
  1 +/*
  2 + * Board initialization for EP93xx
  3 + *
  4 + * Copyright (C) 2013
  5 + * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
  6 + *
  7 + * Copyright (C) 2009
  8 + * Matthias Kaehlcke <matthias <at> kaehlcke.net>
  9 + *
  10 + * (C) Copyright 2002 2003
  11 + * Network Audio Technologies, Inc. <www.netaudiotech.com>
  12 + * Adam Bezanson <bezanson <at> netaudiotech.com>
  13 + *
  14 + * SPDX-License-Identifier: GPL-2.0+
  15 + */
  16 +
  17 +#include <config.h>
  18 +#include <common.h>
  19 +#include <netdev.h>
  20 +#include <asm/io.h>
  21 +#include <asm/arch/ep93xx.h>
  22 +
  23 +DECLARE_GLOBAL_DATA_PTR;
  24 +
  25 +/*
  26 + * usb_div: 4, nbyp2: 1, pll2_en: 1
  27 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
  28 + * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
  29 + */
  30 +#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
  31 + 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
  32 + 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
  33 + 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
  34 + SYSCON_CLKSET2_PLL2_EN | \
  35 + SYSCON_CLKSET2_NBYP2 | \
  36 + 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
  37 +
  38 +#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
  39 + SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
  40 + 1 << SMC_BCR_MW_SHIFT)
  41 +
  42 +/* delay execution before timers are initialized */
  43 +static inline void early_udelay(uint32_t usecs)
  44 +{
  45 + /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
  46 + register uint32_t loops = (usecs * 1000) / 20;
  47 +
  48 + __asm__ volatile ("1:\n"
  49 + "subs %0, %1, #1\n"
  50 + "bne 1b" : "=r" (loops) : "0" (loops));
  51 +}
  52 +
  53 +#ifndef CONFIG_EP93XX_NO_FLASH_CFG
  54 +static void flash_cfg(void)
  55 +{
  56 + struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
  57 +
  58 + writel(SMC_BCR6_VALUE, &smc->bcr6);
  59 +}
  60 +#else
  61 +#define flash_cfg()
  62 +#endif
  63 +
  64 +int board_init(void)
  65 +{
  66 + /*
  67 + * Setup PLL2, PPL1 has been set during lowlevel init
  68 + */
  69 + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  70 + writel(CLKSET2_VAL, &syscon->clkset2);
  71 +
  72 + /*
  73 + * the user's guide recommends to wait at least 1 ms for PLL2 to
  74 + * stabilize
  75 + */
  76 + early_udelay(1000);
  77 +
  78 + /* Go to Async mode */
  79 + __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
  80 + __asm__ volatile ("orr r0, r0, #0xc0000000");
  81 + __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
  82 +
  83 + icache_enable();
  84 +
  85 +#ifdef USE_920T_MMU
  86 + dcache_enable();
  87 +#endif
  88 +
  89 + /* Machine number, as defined in linux/arch/arm/tools/mach-types */
  90 + gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  91 +
  92 + /* adress of boot parameters */
  93 + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  94 +
  95 + /* We have a console */
  96 + gd->have_console = 1;
  97 +
  98 + enable_interrupts();
  99 +
  100 + flash_cfg();
  101 +
  102 + green_led_on();
  103 + red_led_off();
  104 +
  105 + return 0;
  106 +}
  107 +
  108 +int board_early_init_f(void)
  109 +{
  110 + /*
  111 + * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
  112 + * 14.7456/2 MHz
  113 + */
  114 + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  115 + writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
  116 + return 0;
  117 +}
  118 +
  119 +int board_eth_init(bd_t *bd)
  120 +{
  121 + return ep93xx_eth_initialize(0, MAC_BASE);
  122 +}
  123 +
  124 +static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
  125 + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
  126 +{
  127 + if (dram_bank_cnt == 1) {
  128 + dram_bank_base[0] = PHYS_SDRAM_1;
  129 + } else {
  130 + /* Table lookup for holes in address space. Maximum memory
  131 + * for the single SDCS may be up to 256Mb. We start scanning
  132 + * banks from 1Mb, so it could be up to 128 banks theoretically.
  133 + * We need at maximum 7 bits for the loockup, 8 slots is
  134 + * enough for the worst case.
  135 + */
  136 + unsigned tbl[8];
  137 + unsigned i = dram_bank_cnt / 2;
  138 + unsigned j = 0x00100000; /* 1 Mb */
  139 + unsigned *ptbl = tbl;
  140 + do {
  141 + while (!(dram_addr_mask & j)) {
  142 + j <<= 1;
  143 + }
  144 + *ptbl++ = j;
  145 + j <<= 1;
  146 + i >>= 1;
  147 + } while (i != 0);
  148 +
  149 + for (i = dram_bank_cnt, j = 0;
  150 + (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
  151 + unsigned addr = PHYS_SDRAM_1;
  152 + unsigned k;
  153 + unsigned bit;
  154 +
  155 + for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
  156 + if (bit & j)
  157 + addr |= tbl[k];
  158 + }
  159 +
  160 + dram_bank_base[j] = addr;
  161 + }
  162 + }
  163 +}
  164 +
  165 +/* called in board_init_f (before relocation) */
  166 +static unsigned dram_init_banksize_int(int print)
  167 +{
  168 + /*
  169 + * Collect information of banks that has been filled during lowlevel
  170 + * initialization
  171 + */
  172 + unsigned i;
  173 + unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
  174 + unsigned dram_total = 0;
  175 + unsigned dram_bank_size = *(unsigned *)
  176 + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
  177 + unsigned dram_addr_mask = *(unsigned *)
  178 + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
  179 + unsigned dram_bank_cnt = *(unsigned *)
  180 + (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
  181 +
  182 + dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
  183 +
  184 + for (i = 0; i < dram_bank_cnt; i++) {
  185 + gd->bd->bi_dram[i].start = dram_bank_base[i];
  186 + gd->bd->bi_dram[i].size = dram_bank_size;
  187 + dram_total += dram_bank_size;
  188 + }
  189 + for (; i < CONFIG_NR_DRAM_BANKS; i++) {
  190 + gd->bd->bi_dram[i].start = 0;
  191 + gd->bd->bi_dram[i].size = 0;
  192 + }
  193 +
  194 + if (print) {
  195 + printf("DRAM mask: %08x\n", dram_addr_mask);
  196 + printf("DRAM total %u banks:\n", dram_bank_cnt);
  197 + printf("bank base-address size\n");
  198 +
  199 + if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
  200 + printf("WARNING! UBoot was configured for %u banks,\n"
  201 + "but %u has been found. "
  202 + "Supressing extra memory banks\n",
  203 + CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
  204 + dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
  205 + }
  206 +
  207 + for (i = 0; i < dram_bank_cnt; i++) {
  208 + printf(" %u %08x %08x\n",
  209 + i, dram_bank_base[i], dram_bank_size);
  210 + }
  211 + printf(" ------------------------------------------\n"
  212 + "Total %9d\n\n",
  213 + dram_total);
  214 + }
  215 +
  216 + return dram_total;
  217 +}
  218 +
  219 +void dram_init_banksize(void)
  220 +{
  221 + dram_init_banksize_int(0);
  222 +}
  223 +
  224 +/* called in board_init_f (before relocation) */
  225 +int dram_init(void)
  226 +{
  227 + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  228 + unsigned sec_id = readl(SECURITY_EXTENSIONID);
  229 + unsigned chip_id = readl(&syscon->chipid);
  230 +
  231 + printf("CPU: Cirrus Logic ");
  232 + switch (sec_id & 0x000001FE) {
  233 + case 0x00000008:
  234 + printf("EP9301");
  235 + break;
  236 + case 0x00000004:
  237 + printf("EP9307");
  238 + break;
  239 + case 0x00000002:
  240 + printf("EP931x");
  241 + break;
  242 + case 0x00000000:
  243 + printf("EP9315");
  244 + break;
  245 + default:
  246 + printf("<unknown>");
  247 + break;
  248 + }
  249 +
  250 + printf(" - Rev. ");
  251 + switch (chip_id & 0xF0000000) {
  252 + case 0x00000000:
  253 + printf("A");
  254 + break;
  255 + case 0x10000000:
  256 + printf("B");
  257 + break;
  258 + case 0x20000000:
  259 + printf("C");
  260 + break;
  261 + case 0x30000000:
  262 + printf("D0");
  263 + break;
  264 + case 0x40000000:
  265 + printf("D1");
  266 + break;
  267 + case 0x50000000:
  268 + printf("E0");
  269 + break;
  270 + case 0x60000000:
  271 + printf("E1");
  272 + break;
  273 + case 0x70000000:
  274 + printf("E2");
  275 + break;
  276 + default:
  277 + printf("?");
  278 + break;
  279 + }
  280 + printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
  281 +
  282 + gd->ram_size = dram_init_banksize_int(1);
  283 + return 0;
  284 +}
  285 +
  286 +
  287 +#ifdef CONFIG_EP93XX_SPI
  288 +#include <spi.h>
  289 +
  290 +/*
  291 + * EGIO0-EGIPO7 -> port A
  292 + * EGIO8-EGIP15 -> port B
  293 + */
  294 +
  295 +static void ep93xx_set_epgio(unsigned num)
  296 +{
  297 + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
  298 + if (num < 8)
  299 + writel(readl(&regs->padr) | (1<<num), &regs->padr);
  300 + else
  301 + writel(readl(&regs->pbdr) | (1<<(num-8)), &regs->pbdr);
  302 +}
  303 +
  304 +static void ep93xx_clear_epgio(unsigned num)
  305 +{
  306 + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
  307 + if (num < 8)
  308 + writel(readl(&regs->padr) & (~(1<<num)), &regs->padr);
  309 + else
  310 + writel(readl(&regs->pbdr) & (~(1<<(num-8))), &regs->pbdr);
  311 +}
  312 +
  313 +static void ep93xx_dir_epgio_out(unsigned num)
  314 +{
  315 + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
  316 + if (num < 8)
  317 + writel(readl(&regs->paddr) | (1<<num), &regs->paddr);
  318 + else
  319 + writel(readl(&regs->pbddr) | (1<<(num-8)), &regs->pbddr);
  320 +}
  321 +
  322 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  323 +{
  324 + if (bus == 0 && cs < 16)
  325 + return 1;
  326 +
  327 + return 0;
  328 +}
  329 +
  330 +void spi_cs_activate(struct spi_slave *slave)
  331 +{
  332 + ep93xx_clear_epgio(slave->cs);
  333 +}
  334 +
  335 +void spi_cs_deactivate(struct spi_slave *slave)
  336 +{
  337 + ep93xx_set_epgio(slave->cs);
  338 +}
  339 +
  340 +#ifdef CONFIG_MMC_SPI
  341 +#include <mmc.h>
  342 +
  343 +#ifndef CONFIG_MMC_SPI_CS_EPGIO
  344 +# define CONFIG_MMC_SPI_CS_EPGIO 4
  345 +#endif
  346 +
  347 +#ifndef CONFIG_MMC_SPI_SPEED
  348 +# define CONFIG_MMC_SPI_SPEED 25000000
  349 +#endif
  350 +
  351 +#ifndef CONFIG_MMC_SPI_MODE
  352 +# define CONFIG_MMC_SPI_MODE SPI_MODE_0
  353 +#endif
  354 +
  355 +int board_mmc_init(bd_t *bis)
  356 +{
  357 + struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
  358 +
  359 + ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
  360 + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
  361 +
  362 +#ifdef CONFIG_MMC_SPI_POWER_EGPIO
  363 + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
  364 + ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
  365 +#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
  366 + ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
  367 + ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
  368 +#endif
  369 + struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
  370 + CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
  371 +
  372 + if (!mmc) {
  373 + printf("Failed to create MMC Device\n");
  374 + return 1;
  375 + }
  376 + mmc_init(mmc);
  377 + return 0;
  378 +}
  379 +
  380 +
  381 +#endif /* CONFIG_MMC_SPI */
  382 +#endif /* CONFIG_EP93XX_SPI */
board/cirrus/edb93xx/u-boot.lds
Diff comments   View file @ 7237d22
  1 +/*
  2 + *
  3 + * Copyright (C) 2013
  4 + * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
  5 + *
  6 + * Copyright (c) 2004-2008 Texas Instruments
  7 + *
  8 + * (C) Copyright 2002
  9 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  10 + *
  11 + * SPDX-License-Identifier: GPL-2.0+
  12 + */
  13 +
  14 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  15 +OUTPUT_ARCH(arm)
  16 +ENTRY(_start)
  17 +SECTIONS
  18 +{
  19 + . = 0x00000000;
  20 +
  21 + . = ALIGN(4);
  22 + .text : {
  23 + *(.__image_copy_start)
  24 + arch/arm/cpu/arm920t/start.o (.text*)
  25 + . = 0x1000;
  26 +
  27 + LONG(0x53555243)
  28 + *(.text*)
  29 + }
  30 +
  31 + . = ALIGN(4);
  32 + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  33 +
  34 + . = ALIGN(4);
  35 + .data : {
  36 + *(.data*)
  37 + }
  38 +
  39 + . = ALIGN(4);
  40 +
  41 + . = .;
  42 +
  43 + . = ALIGN(4);
  44 + .u_boot_list : {
  45 + KEEP(*(SORT(.u_boot_list*)));
  46 + }
  47 +
  48 + . = ALIGN(4);
  49 +
  50 + .image_copy_end :
  51 + {
  52 + *(.__image_copy_end)
  53 + }
  54 +
  55 + .rel_dyn_start :
  56 + {
  57 + *(.__rel_dyn_start)
  58 + }
  59 +
  60 + .rel.dyn : {
  61 + *(.rel*)
  62 + }
  63 +
  64 + .rel_dyn_end :
  65 + {
  66 + *(.__rel_dyn_end)
  67 + }
  68 +
  69 + .end :
  70 + {
  71 + *(.__end)
  72 + }
  73 +
  74 + _image_binary_end = .;
  75 +
  76 + /*
  77 + * Deprecated: this MMU section is used by pxa at present but
  78 + * should not be used by new boards/CPUs.
  79 + */
  80 + . = ALIGN(4096);
  81 + .mmutable : {
  82 + *(.mmutable)
  83 + }
  84 +
  85 +/*
  86 + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
  87 + * __bss_base and __bss_limit are for linker only (overlay ordering)
  88 + */
  89 +
  90 + .bss_start __rel_dyn_start (OVERLAY) : {
  91 + KEEP(*(.__bss_start));
  92 + __bss_base = .;
  93 + }
  94 +
  95 + .bss __bss_base (OVERLAY) : {
  96 + *(.bss*)
  97 + . = ALIGN(4);
  98 + __bss_limit = .;
  99 + }
  100 +
  101 + .bss_end __bss_limit (OVERLAY) : {
  102 + KEEP(*(.__bss_end));
  103 + }
  104 +
  105 + .dynsym _image_binary_end : { *(.dynsym) }
  106 + .dynbss : { *(.dynbss) }
  107 + .dynstr : { *(.dynstr*) }
  108 + .dynamic : { *(.dynamic*) }
  109 + .plt : { *(.plt*) }
  110 + .interp : { *(.interp*) }
  111 + .gnu.hash : { *(.gnu.hash) }
  112 + .gnu : { *(.gnu*) }
  113 + .ARM.exidx : { *(.ARM.exidx*) }
  114 + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
  115 +}
... ... @@ -78,6 +78,7 @@
78 78 Active arm arm920t ks8695 - - cm41xx - -
79 79 Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Mรผller <d.mueller@elsoft.ch>
80 80 Active arm arm920t s3c24x0 samsung - smdk2410 - David Mรผller <d.mueller@elsoft.ch>
  81 +Active arm arm920t ep93xx cirrus edb93xx edb9315a edb93xx:MK_edb9315a Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
81 82 Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
82 83 Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
83 84 Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com>
drivers/spi/Makefile
Diff comments   View file @ 7237d22
... ... @@ -8,6 +8,7 @@
8 8 # There are many options which enable SPI, so make this library available
9 9 obj-y += spi.o
10 10  
  11 +obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
11 12 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
12 13 obj-$(CONFIG_ANDES_SPI) += andes_spi.o
13 14 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
drivers/spi/ep93xx_spi.c
Diff comments   View file @ 7237d22
  1 +/*
  2 + * SPI Driver for EP93xx
  3 + *
  4 + * Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
  5 + *
  6 + * Inspired form linux kernel driver and atmel uboot driver
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <spi.h>
  13 +#include <malloc.h>
  14 +
  15 +#include <asm/io.h>
  16 +
  17 +#include <asm/arch/ep93xx.h>
  18 +
  19 +
  20 +#define BIT(x) (1<<(x))
  21 +#define SSPBASE SPI_BASE
  22 +
  23 +#define SSPCR0 0x0000
  24 +#define SSPCR0_MODE_SHIFT 6
  25 +#define SSPCR0_SCR_SHIFT 8
  26 +#define SSPCR0_SPH BIT(7)
  27 +#define SSPCR0_SPO BIT(6)
  28 +#define SSPCR0_FRF_SPI 0
  29 +#define SSPCR0_DSS_8BIT 7
  30 +
  31 +#define SSPCR1 0x0004
  32 +#define SSPCR1_RIE BIT(0)
  33 +#define SSPCR1_TIE BIT(1)
  34 +#define SSPCR1_RORIE BIT(2)
  35 +#define SSPCR1_LBM BIT(3)
  36 +#define SSPCR1_SSE BIT(4)
  37 +#define SSPCR1_MS BIT(5)
  38 +#define SSPCR1_SOD BIT(6)
  39 +
  40 +#define SSPDR 0x0008
  41 +
  42 +#define SSPSR 0x000c
  43 +#define SSPSR_TFE BIT(0)
  44 +#define SSPSR_TNF BIT(1)
  45 +#define SSPSR_RNE BIT(2)
  46 +#define SSPSR_RFF BIT(3)
  47 +#define SSPSR_BSY BIT(4)
  48 +#define SSPCPSR 0x0010
  49 +
  50 +#define SSPIIR 0x0014
  51 +#define SSPIIR_RIS BIT(0)
  52 +#define SSPIIR_TIS BIT(1)
  53 +#define SSPIIR_RORIS BIT(2)
  54 +#define SSPICR SSPIIR
  55 +
  56 +#define SSPCLOCK 14745600
  57 +#define SSP_MAX_RATE (SSPCLOCK / 2)
  58 +#define SSP_MIN_RATE (SSPCLOCK / (254 * 256))
  59 +
  60 +/* timeout in milliseconds */
  61 +#define SPI_TIMEOUT 5
  62 +/* maximum depth of RX/TX FIFO */
  63 +#define SPI_FIFO_SIZE 8
  64 +
  65 +struct ep93xx_spi_slave {
  66 + struct spi_slave slave;
  67 +
  68 + unsigned sspcr0;
  69 + unsigned sspcpsr;
  70 +};
  71 +
  72 +static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave)
  73 +{
  74 + return container_of(slave, struct ep93xx_spi_slave, slave);
  75 +}
  76 +
  77 +void spi_init()
  78 +{
  79 +}
  80 +
  81 +static inline void ep93xx_spi_write_u8(u16 reg, u8 value)
  82 +{
  83 + writel(value, (unsigned int *)(SSPBASE + reg));
  84 +}
  85 +
  86 +static inline u8 ep93xx_spi_read_u8(u16 reg)
  87 +{
  88 + return readl((unsigned int *)(SSPBASE + reg));
  89 +}
  90 +
  91 +static inline void ep93xx_spi_write_u16(u16 reg, u16 value)
  92 +{
  93 + writel(value, (unsigned int *)(SSPBASE + reg));
  94 +}
  95 +
  96 +static inline u16 ep93xx_spi_read_u16(u16 reg)
  97 +{
  98 + return (u16)readl((unsigned int *)(SSPBASE + reg));
  99 +}
  100 +
  101 +static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode,
  102 + struct ep93xx_spi_slave *slave)
  103 +{
  104 + unsigned cpsr, scr;
  105 +
  106 + if (rate > SSP_MAX_RATE)
  107 + rate = SSP_MAX_RATE;
  108 +
  109 + if (rate < SSP_MIN_RATE)
  110 + return -1;
  111 +
  112 + /* Calculate divisors so that we can get speed according the
  113 + * following formula:
  114 + * rate = spi_clock_rate / (cpsr * (1 + scr))
  115 + *
  116 + * cpsr must be even number and starts from 2, scr can be any number
  117 + * between 0 and 255.
  118 + */
  119 + for (cpsr = 2; cpsr <= 254; cpsr += 2) {
  120 + for (scr = 0; scr <= 255; scr++) {
  121 + if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) {
  122 + /* Set CHPA and CPOL, SPI format and 8bit */
  123 + unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) |
  124 + SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT;
  125 + if (mode & SPI_CPHA)
  126 + sspcr0 |= SSPCR0_SPH;
  127 + if (mode & SPI_CPOL)
  128 + sspcr0 |= SSPCR0_SPO;
  129 +
  130 + slave->sspcr0 = sspcr0;
  131 + slave->sspcpsr = cpsr;
  132 + return 0;
  133 + }
  134 + }
  135 + }
  136 +
  137 + return -1;
  138 +}
  139 +
  140 +void spi_set_speed(struct spi_slave *slave, unsigned int hz)
  141 +{
  142 + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
  143 +
  144 + unsigned int mode = 0;
  145 + if (as->sspcr0 & SSPCR0_SPH)
  146 + mode |= SPI_CPHA;
  147 + if (as->sspcr0 & SSPCR0_SPO)
  148 + mode |= SPI_CPOL;
  149 +
  150 + ep93xx_spi_init_hw(hz, mode, as);
  151 +}
  152 +
  153 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  154 + unsigned int max_hz, unsigned int mode)
  155 +{
  156 + struct ep93xx_spi_slave *as;
  157 +
  158 + if (!spi_cs_is_valid(bus, cs))
  159 + return NULL;
  160 +
  161 + as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs);
  162 + if (!as)
  163 + return NULL;
  164 +
  165 + if (ep93xx_spi_init_hw(max_hz, mode, as)) {
  166 + free(as);
  167 + return NULL;
  168 + }
  169 +
  170 + return &as->slave;
  171 +}
  172 +
  173 +void spi_free_slave(struct spi_slave *slave)
  174 +{
  175 + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
  176 +
  177 + free(as);
  178 +}
  179 +
  180 +int spi_claim_bus(struct spi_slave *slave)
  181 +{
  182 + struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
  183 +
  184 + /* Enable the SPI hardware */
  185 + ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE);
  186 +
  187 +
  188 + ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr);
  189 + ep93xx_spi_write_u16(SSPCR0, as->sspcr0);
  190 +
  191 + debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n",
  192 + slave->cs, as->sspcpsr, as->sspcr0);
  193 + return 0;
  194 +}
  195 +
  196 +void spi_release_bus(struct spi_slave *slave)
  197 +{
  198 + /* Disable the SPI hardware */
  199 + ep93xx_spi_write_u8(SSPCR1, 0);
  200 +}
  201 +
  202 +int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  203 + const void *dout, void *din, unsigned long flags)
  204 +{
  205 + unsigned int len_tx;
  206 + unsigned int len_rx;
  207 + unsigned int len;
  208 + u32 status;
  209 + const u8 *txp = dout;
  210 + u8 *rxp = din;
  211 + u8 value;
  212 +
  213 + debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
  214 + slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen);
  215 +
  216 +
  217 + if (bitlen == 0)
  218 + /* Finish any previously submitted transfers */
  219 + goto out;
  220 +
  221 + if (bitlen % 8) {
  222 + /* Errors always terminate an ongoing transfer */
  223 + flags |= SPI_XFER_END;
  224 + goto out;
  225 + }
  226 +
  227 + len = bitlen / 8;
  228 +
  229 +
  230 + if (flags & SPI_XFER_BEGIN) {
  231 + /* Empty RX FIFO */
  232 + while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE))
  233 + ep93xx_spi_read_u8(SSPDR);
  234 +
  235 + spi_cs_activate(slave);
  236 + }
  237 +
  238 + for (len_tx = 0, len_rx = 0; len_rx < len; ) {
  239 + status = ep93xx_spi_read_u8(SSPSR);
  240 +
  241 + if ((len_tx < len) && (status & SSPSR_TNF)) {
  242 + if (txp)
  243 + value = *txp++;
  244 + else
  245 + value = 0xff;
  246 +
  247 + ep93xx_spi_write_u8(SSPDR, value);
  248 + len_tx++;
  249 + }
  250 +
  251 + if (status & SSPSR_RNE) {
  252 + value = ep93xx_spi_read_u8(SSPDR);
  253 +
  254 + if (rxp)
  255 + *rxp++ = value;
  256 + len_rx++;
  257 + }
  258 + }
  259 +
  260 +out:
  261 + if (flags & SPI_XFER_END) {
  262 + /*
  263 + * Wait until the transfer is completely done before
  264 + * we deactivate CS.
  265 + */
  266 + do {
  267 + status = ep93xx_spi_read_u8(SSPSR);
  268 + } while (status & SSPSR_BSY);
  269 +
  270 + spi_cs_deactivate(slave);
  271 + }
  272 +
  273 + return 0;
  274 +}
drivers/usb/host/Makefile
Diff comments   View file @ 7237d22
... ... @@ -13,6 +13,7 @@
13 13 obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
14 14 obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
15 15 obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
  16 +obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
16 17  
17 18 # echi
18 19 obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
drivers/usb/host/ohci-ep93xx.c
Diff comments   View file @ 7237d22
  1 +/*
  2 + * (C) Copyright 2013
  3 + * Sergey Kostanbaev < sergey.kostanbaev <at> fairwaves.ru >
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <config.h>
  9 +#include <common.h>
  10 +
  11 +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
  12 +#include <asm/io.h>
  13 +#include <asm/arch/ep93xx.h>
  14 +
  15 +int usb_cpu_init(void)
  16 +{
  17 + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  18 + unsigned long pwr = readl(&syscon->pwrcnt);
  19 + writel(pwr | SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
  20 +
  21 + return 0;
  22 +}
  23 +
  24 +int usb_cpu_stop(void)
  25 +{
  26 + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  27 + unsigned long pwr = readl(&syscon->pwrcnt);
  28 + writel(pwr & ~SYSCON_PWRCNT_USH_EN, &syscon->pwrcnt);
  29 +
  30 + return 0;
  31 +}
  32 +
  33 +int usb_cpu_init_fail(void)
  34 +{
  35 + return usb_cpu_stop();
  36 +}
  37 +
  38 +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
include/configs/edb93xx.h
Diff comments   View file @ 7237d22
  1 +/*
  2 + * U-boot - Configuration file for Cirrus Logic EDB93xx boards
  3 + */
  4 +
  5 +#ifndef __CONFIG_H
  6 +#define __CONFIG_H
  7 +
  8 +#ifdef CONFIG_MK_edb9301
  9 +#define CONFIG_EDB9301
  10 +#elif defined(CONFIG_MK_edb9302)
  11 +#define CONFIG_EDB9302
  12 +#elif defined(CONFIG_MK_edb9302a)
  13 +#define CONFIG_EDB9302A
  14 +#elif defined(CONFIG_MK_edb9307)
  15 +#define CONFIG_EDB9307
  16 +#elif defined(CONFIG_MK_edb9307a)
  17 +#define CONFIG_EDB9307A
  18 +#elif defined(CONFIG_MK_edb9312)
  19 +#define CONFIG_EDB9312
  20 +#elif defined(CONFIG_MK_edb9315)
  21 +#define CONFIG_EDB9315
  22 +#elif defined(CONFIG_MK_edb9315a)
  23 +#define CONFIG_EDB9315A
  24 +#else
  25 +#error "no board defined"
  26 +#endif
  27 +
  28 +/* Initial environment and monitor configuration options. */
  29 +#define CONFIG_BOOTDELAY 2
  30 +#define CONFIG_CMDLINE_TAG 1
  31 +#define CONFIG_INITRD_TAG 1
  32 +#define CONFIG_SETUP_MEMORY_TAGS 1
  33 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
  34 +#define CONFIG_BOOTFILE "edb93xx.img"
  35 +
  36 +#define CONFIG_SYS_HUSH_PARSER 1
  37 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  38 +
  39 +
  40 +#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
  41 +
  42 +
  43 +#ifdef CONFIG_EDB9301
  44 +#define CONFIG_EP9301
  45 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301
  46 +#define CONFIG_SYS_PROMPT "EDB9301> "
  47 +#define CONFIG_ENV_SECT_SIZE 0x00020000
  48 +#elif defined(CONFIG_EDB9302)
  49 +#define CONFIG_EP9302
  50 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302
  51 +#define CONFIG_SYS_PROMPT "EDB9302> "
  52 +#define CONFIG_ENV_SECT_SIZE 0x00020000
  53 +#elif defined(CONFIG_EDB9302A)
  54 +#define CONFIG_EP9302
  55 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A
  56 +#define CONFIG_SYS_PROMPT "EDB9302A> "
  57 +#define CONFIG_ENV_SECT_SIZE 0x00020000
  58 +#elif defined(CONFIG_EDB9307)
  59 +#define CONFIG_EP9307
  60 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307
  61 +#define CONFIG_SYS_PROMPT "EDB9307> "
  62 +#define CONFIG_ENV_SECT_SIZE 0x00040000
  63 +#elif defined(CONFIG_EDB9307A)
  64 +#define CONFIG_EP9307
  65 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A
  66 +#define CONFIG_SYS_PROMPT "EDB9307A> "
  67 +#define CONFIG_ENV_SECT_SIZE 0x00020000
  68 +#elif defined(CONFIG_EDB9312)
  69 +#define CONFIG_EP9312
  70 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312
  71 +#define CONFIG_SYS_PROMPT "EDB9312> "
  72 +#define CONFIG_ENV_SECT_SIZE 0x00040000
  73 +#elif defined(CONFIG_EDB9315)
  74 +#define CONFIG_EP9315
  75 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315
  76 +#define CONFIG_SYS_PROMPT "EDB9315> "
  77 +#define CONFIG_ENV_SECT_SIZE 0x00040000
  78 +#elif defined(CONFIG_EDB9315A)
  79 +#define CONFIG_EP9315
  80 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A
  81 +#define CONFIG_SYS_PROMPT "EDB9315A> "
  82 +#define CONFIG_ENV_SECT_SIZE 0x00020000
  83 +#else
  84 +#error "no board defined"
  85 +#endif
  86 +
  87 +/* High-level configuration options */
  88 +#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
  89 +#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
  90 +
  91 +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
  92 +#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */
  93 +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
  94 +
  95 +/* Monitor configuration */
  96 +#include <config_cmd_default.h>
  97 +#undef CONFIG_CMD_FPGA
  98 +#undef CONFIG_CMD_SETGETDCR
  99 +#undef CONFIG_CMD_XIMG
  100 +
  101 +#undef CONFIG_CMD_DATE
  102 +#define CONFIG_CMD_DHCP
  103 +#define CONFIG_CMD_JFFS2
  104 +
  105 +#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
  106 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  107 +/* Print buffer size */
  108 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  109 +/* Boot argument buffer size */
  110 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  111 +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
  112 +
  113 +/* Serial port hardware configuration */
  114 +#define CONFIG_PL010_SERIAL
  115 +#define CONFIG_CONS_INDEX 0
  116 +#define CONFIG_BAUDRATE 115200
  117 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \
  118 + 115200, 230400}
  119 +#define CONFIG_SYS_SERIAL0 0x808C0000
  120 +#define CONFIG_SYS_SERIAL1 0x808D0000
  121 +/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
  122 + (void *)CONFIG_SYS_SERIAL1} */
  123 +
  124 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
  125 +
  126 +/* Status LED */
  127 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  128 +#define CONFIG_BOARD_SPECIFIC_LED 1
  129 +#define STATUS_LED_GREEN 0
  130 +#define STATUS_LED_RED 1
  131 +/* Green */
  132 +#define STATUS_LED_BIT STATUS_LED_GREEN
  133 +#define STATUS_LED_STATE STATUS_LED_ON
  134 +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
  135 +/* Red */
  136 +#define STATUS_LED_BIT1 STATUS_LED_RED
  137 +#define STATUS_LED_STATE1 STATUS_LED_OFF
  138 +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
  139 +/* Optional value */
  140 +#define STATUS_LED_BOOT STATUS_LED_BIT
  141 +
  142 +/* Network hardware configuration */
  143 +#define CONFIG_DRIVER_EP93XX_MAC
  144 +#define CONFIG_MII_SUPPRESS_PREAMBLE
  145 +#define CONFIG_MII
  146 +#define CONFIG_PHY_ADDR 1
  147 +#define CONFIG_NET_MULTI
  148 +#undef CONFIG_NETCONSOLE
  149 +
  150 +/* SDRAM configuration */
  151 +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
  152 + defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
  153 + defined(CONFIG_EDB9315)
  154 +/*
  155 + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
  156 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
  157 + * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
  158 + *
  159 + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
  160 + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
  161 + * 64 MB of SDRAM.
  162 + */
  163 +
  164 +#define CONFIG_EDB93XX_SDCS3
  165 +
  166 +#elif defined(CONFIG_EDB9302A) || \
  167 + defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
  168 +/*
  169 + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
  170 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
  171 + * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
  172 + *
  173 + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
  174 + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
  175 + */
  176 +#define CONFIG_EDB93XX_SDCS0
  177 +
  178 +#else
  179 +#error "no SDCS configuration for this board"
  180 +#endif
  181 +
  182 +
  183 +#if defined(CONFIG_EDB93XX_SDCS3)
  184 +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */
  185 +#define PHYS_SDRAM_1 0x00000000
  186 +#elif defined(CONFIG_EDB93XX_SDCS0)
  187 +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */
  188 +#define PHYS_SDRAM_1 0xc0000000
  189 +#endif
  190 +
  191 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  192 +#define CONFIG_NR_DRAM_BANKS 8
  193 +
  194 +#define CONFIG_SYS_INIT_SP_ADDR \
  195 + (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
  196 +
  197 +
  198 +/* Must match kernel config */
  199 +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
  200 +
  201 +/* Run-time memory allocatons */
  202 +#define CONFIG_SYS_GBL_DATA_SIZE 128
  203 +#define CONFIG_STACKSIZE (128 * 1024)
  204 +
  205 +#if defined(CONFIG_USE_IRQ)
  206 +#define CONFIG_STACKSIZE_IRQ (4 * 1024)
  207 +#define CONFIG_STACKSIZE_FIQ (4 * 1024)
  208 +#endif
  209 +
  210 +#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  211 +
  212 +/* -----------------------------------------------------------------------------
  213 + * FLASH and environment organization
  214 + *
  215 + * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at
  216 + * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit
  217 + * data bus, for a total of 16 MB of CFI-compatible flash.
  218 + *
  219 + * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
  220 + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
  221 + * data bus, for a total of 32 MB of CFI-compatible flash.
  222 + *
  223 + *
  224 + * EDB9301/02(a)7a/15a EDB9307/12/15
  225 + * 0x60000000 - 0x0003FFFF u-boot u-boot
  226 + * 0x60040000 - 0x0005FFFF environment #1 environment #1
  227 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued)
  228 + * 0x60080000 - 0x0009FFFF unused environment #2
  229 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued)
  230 + * 0x600C0000 - 0x00FFFFFF unused unused
  231 + * 0x61000000 - 0x01FFFFFF not present unused
  232 + */
  233 +#define CONFIG_SYS_FLASH_CFI
  234 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  235 +
  236 +
  237 +#define CONFIG_SYS_FLASH_PROTECTION
  238 +#define CONFIG_FLASH_CFI_DRIVER
  239 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
  240 +#define CONFIG_SYS_MAX_FLASH_SECT (256+8)
  241 +
  242 +#define CONFIG_SYS_TEXT_BASE 0x60000000
  243 +#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE
  244 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
  245 +
  246 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  247 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  248 +
  249 +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */
  250 +#define CONFIG_ENV_IS_IN_FLASH
  251 +
  252 +#define CONFIG_ENV_ADDR 0x60040000
  253 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  254 +
  255 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  256 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  257 +
  258 +/* Define to enable MMC on SPI support */
  259 +/* #define CONFIG_EP93XX_SPI_MMC */
  260 +
  261 +#ifdef CONFIG_EP93XX_SPI_MMC
  262 +#define CONFIG_EP93XX_SPI
  263 +#define CONFIG_MMC
  264 +#define CONFIG_GENERIC_MMC
  265 +#define CONFIG_MMC_SPI
  266 +#define CONFIG_CMD_MMC
  267 +#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
  268 +#endif
  269 +
  270 +#define CONFIG_USB_STORAGE
  271 +#define CONFIG_USB_OHCI_NEW
  272 +#define CONFIG_USB_OHCI_EP93XX
  273 +#define CONFIG_SYS_USB_OHCI_CPU_INIT
  274 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
  275 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci"
  276 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000
  277 +
  278 +#define CONFIG_CMD_EXT2
  279 +#define CONFIG_CMD_EXT4
  280 +#define CONFIG_CMD_FAT
  281 +#define CONFIG_CMD_USB
  282 +
  283 +#define CONFIG_BOARD_EARLY_INIT_F
  284 +#define CONFIG_CMD_BOOTZ
  285 +
  286 +/* Define to disable flash configuration*/
  287 +/* #define CONFIG_EP93XX_NO_FLASH_CFG */
  288 +
  289 +/* Define this for indusrial rated chips */
  290 +/* #define CONFIG_EDB93XX_INDUSTRIAL */
  291 +
  292 +#endif /* !defined (__CONFIG_H) */