Eric Lee / smarc-uboot

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Commit 7282672d298905088fb3c7c0a049d7d7d31cb8b4

Authored by Simon Glass
Committed by Bin Meng
1 parent ac94b7bcbe
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

dm: pci: Convert bios_emu to use the driver model PCI API 

At present this BIOS emulator uses a bus/device/function number. Change
it to use a device if CONFIG_DM_PCI is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 4 changed files with 165 additions and 8 deletions Side-by-side Diff

drivers/bios_emulator/atibios.c
Diff comments   View file @ 7282672
... ... @@ -226,11 +226,19 @@
226 226 at this stage the controller has its I/O and memory space enabled and
227 227 that all other controllers are in a disabled state.
228 228 ****************************************************************************/
  229 +#ifdef CONFIG_DM_PCI
  230 +static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info,
  231 + int vesa_mode, struct vbe_mode_info *mode_info)
  232 +#else
229 233 static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
230 234 int vesa_mode, struct vbe_mode_info *mode_info)
  235 +#endif
231 236 {
232 237 RMREGS regs;
233 238 RMSREGS sregs;
  239 +#ifdef CONFIG_DM_PCI
  240 + pci_dev_t bdf;
  241 +#endif
234 242  
235 243 /* Determine the value to store in AX for BIOS POST. Per the PCI specs,
236 244 AH must contain the bus and AL must contain the devfn, encoded as
237 245  
... ... @@ -238,9 +246,14 @@
238 246 */
239 247 memset(&regs, 0, sizeof(regs));
240 248 memset(&sregs, 0, sizeof(sregs));
  249 +#ifdef CONFIG_DM_PCI
  250 + bdf = dm_pci_get_bdf(pcidev);
  251 + regs.x.ax = (int)PCI_BUS(bdf) << 8 |
  252 + (int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf);
  253 +#else
241 254 regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
242 255 ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
243   -
  256 +#endif
244 257 /*Setup the X86 emulator for the VGA BIOS*/
245 258 BE_setVGA(vga_info);
246 259  
247 260  
248 261  
249 262  
250 263  
251 264  
... ... @@ -281,15 +294,28 @@
281 294 it programmed to all 1's. It must be restored to the correct value
282 295 later.
283 296 ****************************************************************************/
  297 +#ifdef CONFIG_DM_PCI
  298 +static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar)
  299 +#else
284 300 static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
  301 +#endif
285 302 {
286 303 u32 base, size;
287 304  
288 305 for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
  306 +#ifdef CONFIG_DM_PCI
  307 + dm_pci_read_config32(pcidev, *bar, &base);
  308 +#else
289 309 pci_read_config_dword(pcidev, *bar, &base);
  310 +#endif
290 311 if (!(base & 0x1)) {
  312 +#ifdef CONFIG_DM_PCI
  313 + dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF);
  314 + dm_pci_read_config32(pcidev, *bar, &size);
  315 +#else
291 316 pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
292 317 pci_read_config_dword(pcidev, *bar, &size);
  318 +#endif
293 319 size = ~(size & ~0xFF) + 1;
294 320 if (size >= MAX_BIOSLEN)
295 321 return base & ~0xFF;
296 322  
297 323  
298 324  
... ... @@ -312,11 +338,19 @@
312 338 Anyway to fix this we change all I/O mapped base registers and
313 339 chop off the top bits.
314 340 ****************************************************************************/
  341 +#ifdef CONFIG_DM_PCI
  342 +static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base)
  343 +#else
315 344 static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
  345 +#endif
316 346 {
317 347 if ((*base & 0x1) && (*base > 0xFFFE)) {
318 348 *base &= 0xFFFF;
  349 +#ifdef CONFIG_DM_PCI
  350 + dm_pci_write_config32(pcidev, reg, *base);
  351 +#else
319 352 pci_write_config_dword(pcidev, reg, *base);
  353 +#endif
320 354  
321 355 }
322 356 }
323 357  
324 358  
325 359  
... ... @@ -331,18 +365,30 @@
331 365 REMARKS:
332 366 Maps a pointer to the BIOS image on the graphics card on the PCI bus.
333 367 ****************************************************************************/
  368 +#ifdef CONFIG_DM_PCI
  369 +void *PCI_mapBIOSImage(struct udevice *pcidev)
  370 +#else
334 371 void *PCI_mapBIOSImage(pci_dev_t pcidev)
  372 +#endif
335 373 {
336 374 u32 BIOSImageBus;
337 375 int BIOSImageBAR;
338 376 u8 *BIOSImage;
339 377  
340 378 /*Save PCI BAR registers that might get changed*/
  379 +#ifdef CONFIG_DM_PCI
  380 + dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
  381 + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
  382 + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
  383 + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
  384 + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
  385 +#else
341 386 pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
342 387 pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
343 388 pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
344 389 pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
345 390 pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
  391 +#endif
346 392  
347 393 /*Fix up I/O base registers to less than 64K */
348 394 if(saveBaseAddress14 != 0)
349 395  
... ... @@ -361,13 +407,21 @@
361 407 return NULL;
362 408 }
363 409  
  410 +#ifdef CONFIG_DM_PCI
  411 + BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus,
  412 + PCI_REGION_MEM, 0, MAP_NOCACHE);
  413 +
  414 + /*Change the PCI BAR registers to map it onto the bus.*/
  415 + dm_pci_write_config32(pcidev, BIOSImageBAR, 0);
  416 + dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
  417 +#else
364 418 BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
365 419 PCI_REGION_MEM, 0, MAP_NOCACHE);
366 420  
367 421 /*Change the PCI BAR registers to map it onto the bus.*/
368 422 pci_write_config_dword(pcidev, BIOSImageBAR, 0);
369 423 pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
370   -
  424 +#endif
371 425 udelay(1);
372 426  
373 427 /*Check that the BIOS image is valid. If not fail, or return the
... ... @@ -387,6 +441,16 @@
387 441 REMARKS:
388 442 Unmaps the BIOS image for the device and restores framebuffer mappings
389 443 ****************************************************************************/
  444 +#ifdef CONFIG_DM_PCI
  445 +void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
  446 +{
  447 + dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
  448 + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
  449 + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
  450 + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
  451 + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
  452 +}
  453 +#else
390 454 void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
391 455 {
392 456 pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
... ... @@ -395,6 +459,7 @@
395 459 pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
396 460 pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
397 461 }
  462 +#endif
398 463  
399 464 /****************************************************************************
400 465 PARAMETERS:
401 466  
402 467  
... ... @@ -408,13 +473,22 @@
408 473 Loads and POST's the display controllers BIOS, directly from the BIOS
409 474 image we can extract over the PCI bus.
410 475 ****************************************************************************/
  476 +#ifdef CONFIG_DM_PCI
  477 +static int PCI_postController(struct udevice *pcidev, uchar *bios_rom,
  478 + int bios_len, BE_VGAInfo *vga_info,
  479 + int vesa_mode, struct vbe_mode_info *mode_info)
  480 +#else
411 481 static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
412 482 BE_VGAInfo *vga_info, int vesa_mode,
413 483 struct vbe_mode_info *mode_info)
  484 +#endif
414 485 {
415 486 u32 bios_image_len;
416 487 uchar *mapped_bios;
417 488 uchar *copy_of_bios;
  489 +#ifdef CONFIG_DM_PCI
  490 + pci_dev_t bdf;
  491 +#endif
418 492  
419 493 if (bios_rom) {
420 494 copy_of_bios = bios_rom;
421 495  
... ... @@ -442,9 +516,16 @@
442 516 }
443 517  
444 518 /*Save information in vga_info structure*/
  519 +#ifdef CONFIG_DM_PCI
  520 + bdf = dm_pci_get_bdf(pcidev);
  521 + vga_info->function = PCI_FUNC(bdf);
  522 + vga_info->device = PCI_DEV(bdf);
  523 + vga_info->bus = PCI_BUS(bdf);
  524 +#else
445 525 vga_info->function = PCI_FUNC(pcidev);
446 526 vga_info->device = PCI_DEV(pcidev);
447 527 vga_info->bus = PCI_BUS(pcidev);
  528 +#endif
448 529 vga_info->pcidev = pcidev;
449 530 vga_info->BIOSImage = copy_of_bios;
450 531 vga_info->BIOSImageLen = bios_image_len;
451 532  
452 533  
453 534  
... ... @@ -462,13 +543,22 @@
462 543 return true;
463 544 }
464 545  
  546 +#ifdef CONFIG_DM_PCI
  547 +int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop)
  548 +#else
465 549 int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
  550 +#endif
466 551 {
467 552 BE_VGAInfo *VGAInfo;
  553 +#ifdef CONFIG_DM_PCI
  554 + pci_dev_t bdf = dm_pci_get_bdf(pcidev);
468 555  
469 556 printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
470   - PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
471   -
  557 + PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf));
  558 +#else
  559 + printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
  560 + PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
  561 +#endif
472 562 /*Initialise the x86 BIOS emulator*/
473 563 if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
474 564 printf("videoboot: Out of memory!\n");
475 565  
... ... @@ -486,9 +576,15 @@
486 576 X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
487 577 }
488 578  
  579 +#ifdef CONFIG_DM_PCI
  580 +int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len,
  581 + BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
  582 + struct vbe_mode_info *mode_info)
  583 +#else
489 584 int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
490 585 BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
491 586 struct vbe_mode_info *mode_info)
  587 +#endif
492 588 {
493 589 /*Post all the display controller BIOS'es*/
494 590 if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
495 591  
... ... @@ -522,7 +618,12 @@
522 618 Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
523 619 and the X86 BIOS emulator module.
524 620 ****************************************************************************/
  621 +#ifdef CONFIG_DM_PCI
  622 +int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
  623 + int clean_up)
  624 +#else
525 625 int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
  626 +#endif
526 627 {
527 628 BE_VGAInfo *VGAInfo;
528 629 int ret;
drivers/bios_emulator/bios.c
Diff comments   View file @ 7282672
... ... @@ -185,12 +185,21 @@
185 185 case 0xB103: /* Find PCI class code */
186 186 M.x86.R_AH = DEVICE_NOT_FOUND;
187 187 #ifdef __KERNEL__
  188 +#ifdef CONFIG_DM_PCI
  189 + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
  190 + &interface);
  191 + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
  192 + &subclass);
  193 + dm_pci_read_config8(_BE_env.vgaInfo.pcidev,
  194 + PCI_CLASS_DEVICE + 1, &baseclass);
  195 +#else
188 196 pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
189 197 &interface);
190 198 pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
191 199 &subclass);
192 200 pci_read_config_byte(_BE_env.vgaInfo.pcidev,
193 201 PCI_CLASS_DEVICE + 1, &baseclass);
  202 +#endif
194 203 if (M.x86.R_CL == interface && M.x86.R_CH == subclass
195 204 && (u8) (M.x86.R_ECX >> 16) == baseclass) {
196 205 #else
197 206  
... ... @@ -209,8 +218,13 @@
209 218 if (M.x86.R_BX == pciSlot) {
210 219 M.x86.R_AH = SUCCESSFUL;
211 220 #ifdef __KERNEL__
  221 +# ifdef CONFIG_DM_PCI
  222 + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
  223 + &M.x86.R_CL);
  224 +# else
212 225 pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
213 226 &M.x86.R_CL);
  227 +# endif
214 228 #else
215 229 M.x86.R_CL =
216 230 (u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE,
217 231  
... ... @@ -224,8 +238,13 @@
224 238 if (M.x86.R_BX == pciSlot) {
225 239 M.x86.R_AH = SUCCESSFUL;
226 240 #ifdef __KERNEL__
  241 +# ifdef CONFIG_DM_PCI
  242 + dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
  243 + &M.x86.R_CX);
  244 +# else
227 245 pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
228 246 &M.x86.R_CX);
  247 +# endif
229 248 #else
230 249 M.x86.R_CX =
231 250 (u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD,
232 251  
... ... @@ -239,8 +258,13 @@
239 258 if (M.x86.R_BX == pciSlot) {
240 259 M.x86.R_AH = SUCCESSFUL;
241 260 #ifdef __KERNEL__
  261 +# ifdef CONFIG_DM_PCI
  262 + dm_pci_read_config32(_BE_env.vgaInfo.pcidev,
  263 + M.x86.R_DI, &M.x86.R_ECX);
  264 +# else
242 265 pci_read_config_dword(_BE_env.vgaInfo.pcidev,
243 266 M.x86.R_DI, &M.x86.R_ECX);
  267 +# endif
244 268 #else
245 269 M.x86.R_ECX =
246 270 (u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD,
247 271  
... ... @@ -254,8 +278,13 @@
254 278 if (M.x86.R_BX == pciSlot) {
255 279 M.x86.R_AH = SUCCESSFUL;
256 280 #ifdef __KERNEL__
  281 +# ifdef CONFIG_DM_PCI
  282 + dm_pci_write_config8(_BE_env.vgaInfo.pcidev,
  283 + M.x86.R_DI, M.x86.R_CL);
  284 +# else
257 285 pci_write_config_byte(_BE_env.vgaInfo.pcidev,
258 286 M.x86.R_DI, M.x86.R_CL);
  287 +# endif
259 288 #else
260 289 PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE,
261 290 _BE_env.vgaInfo.pciInfo);
262 291  
... ... @@ -268,8 +297,13 @@
268 297 if (M.x86.R_BX == pciSlot) {
269 298 M.x86.R_AH = SUCCESSFUL;
270 299 #ifdef __KERNEL__
  300 +# ifdef CONFIG_DM_PCI
  301 + dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
  302 + M.x86.R_DI, M.x86.R_CX);
  303 +# else
271 304 pci_write_config_word(_BE_env.vgaInfo.pcidev,
272 305 M.x86.R_DI, M.x86.R_CX);
  306 +# endif
273 307 #else
274 308 PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD,
275 309 _BE_env.vgaInfo.pciInfo);
276 310  
... ... @@ -282,8 +316,13 @@
282 316 if (M.x86.R_BX == pciSlot) {
283 317 M.x86.R_AH = SUCCESSFUL;
284 318 #ifdef __KERNEL__
  319 +# ifdef CONFIG_DM_PCI
  320 + dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
  321 + M.x86.R_DI, M.x86.R_ECX);
  322 +# else
285 323 pci_write_config_dword(_BE_env.vgaInfo.pcidev,
286 324 M.x86.R_DI, M.x86.R_ECX);
  325 +# endif
287 326 #else
288 327 PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD,
289 328 _BE_env.vgaInfo.pciInfo);
drivers/pci/pci_rom.c
Diff comments   View file @ 7282672
... ... @@ -328,12 +328,12 @@
328 328 #ifdef CONFIG_BIOSEMU
329 329 BE_VGAInfo *info;
330 330  
331   - ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
  331 + ret = biosemu_setup(dev, &info);
332 332 if (ret)
333 333 goto err;
334 334 biosemu_set_interrupt_handler(0x15, int15_handler);
335   - ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
336   - info, true, vesa_mode, &mode_info);
  335 + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
  336 + true, vesa_mode, &mode_info);
337 337 if (ret)
338 338 goto err;
339 339 #endif
... ... @@ -31,7 +31,11 @@
31 31 int bus;
32 32 u32 VendorID;
33 33 u32 DeviceID;
  34 +#ifdef CONFIG_DM_PCI
  35 + struct udevice *pcidev;
  36 +#else
34 37 pci_dev_t pcidev;
  38 +#endif
35 39 void *BIOSImage;
36 40 u32 BIOSImageLen;
37 41 u8 LowMem[1536];
... ... @@ -39,7 +43,12 @@
39 43  
40 44 struct vbe_mode_info;
41 45  
42   -int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
  46 +#ifdef CONFIG_DM_PCI
  47 +int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
  48 + int clean_up);
  49 +#else
  50 +int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
  51 +#endif
43 52  
44 53 /* Run a BIOS ROM natively (only supported on x86 machines) */
45 54 void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
46 55  
... ... @@ -57,11 +66,19 @@
57 66  
58 67 void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
59 68  
  69 +#ifdef CONFIG_DM_PCI
  70 +int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
  71 +
  72 +int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
  73 + BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
  74 + struct vbe_mode_info *mode_info);
  75 +#else
60 76 int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
61 77  
62 78 int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
63 79 BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
64 80 struct vbe_mode_info *mode_info);
  81 +#endif
65 82  
66 83 #endif