Commit 738815c0cc44aa329097f868dc1efc49ede9c5ba
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87c1833a39
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ppc4xx: Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Showing 3 changed files with 13 additions and 13 deletions Side-by-side Diff
board/amcc/luan/luan.c
cpu/ppc4xx/440spe_pcie.c
| ... | ... | @@ -104,7 +104,7 @@ |
| 104 | 104 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && |
| 105 | 105 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) |
| 106 | 106 | return 0; |
| 107 | - | |
| 107 | + | |
| 108 | 108 | address = pcie_get_base(hose, devfn); |
| 109 | 109 | offset += devfn << 4; |
| 110 | 110 | |
| 111 | 111 | |
| ... | ... | @@ -136,12 +136,12 @@ |
| 136 | 136 | int offset, int len, u32 val) { |
| 137 | 137 | |
| 138 | 138 | u8 *address; |
| 139 | - | |
| 139 | + | |
| 140 | 140 | /* |
| 141 | 141 | * Bus numbers are relative to hose->first_busno |
| 142 | 142 | */ |
| 143 | 143 | devfn -= PCI_BDF(hose->first_busno, 0, 0); |
| 144 | - | |
| 144 | + | |
| 145 | 145 | /* |
| 146 | 146 | * Same constraints as in pcie_read_config(). |
| 147 | 147 | */ |
| ... | ... | @@ -151,7 +151,7 @@ |
| 151 | 151 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && |
| 152 | 152 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) |
| 153 | 153 | return 0; |
| 154 | - | |
| 154 | + | |
| 155 | 155 | address = pcie_get_base(hose, devfn); |
| 156 | 156 | offset += devfn << 4; |
| 157 | 157 | |
| ... | ... | @@ -926,7 +926,7 @@ |
| 926 | 926 | in_le16((u16 *)(mbase + PCI_COMMAND)) | |
| 927 | 927 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 928 | 928 | printf("PCIE:%d successfully set as rootpoint\n",port); |
| 929 | - | |
| 929 | + | |
| 930 | 930 | /* Set Device and Vendor Id */ |
| 931 | 931 | switch (port) { |
| 932 | 932 | case 0: |
cpu/ppc4xx/4xx_enet.c
| ... | ... | @@ -410,7 +410,7 @@ |
| 410 | 410 | #endif |
| 411 | 411 | #endif |
| 412 | 412 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| 413 | - defined(CONFIG_440SPE) || defined(CONFIG_440SP) | |
| 413 | + defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
| 414 | 414 | unsigned long mfr; |
| 415 | 415 | #endif |
| 416 | 416 | |
| ... | ... | @@ -502,8 +502,8 @@ |
| 502 | 502 | __asm__ volatile ("eieio"); |
| 503 | 503 | |
| 504 | 504 | /* reset emac so we have access to the phy */ |
| 505 | -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 506 | - defined(CONFIG_440SP) | |
| 505 | +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 506 | + defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
| 507 | 507 | /* provide clocks for EMAC internal loopback */ |
| 508 | 508 | mfsdr (sdr_mfr, mfr); |
| 509 | 509 | mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); |
| ... | ... | @@ -521,8 +521,8 @@ |
| 521 | 521 | if (failsafe <= 0) |
| 522 | 522 | printf("\nProblem resetting EMAC!\n"); |
| 523 | 523 | |
| 524 | -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 525 | - defined(CONFIG_440SP) | |
| 524 | +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 525 | + defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
| 526 | 526 | /* remove clocks for EMAC internal loopback */ |
| 527 | 527 | mfsdr (sdr_mfr, mfr); |
| 528 | 528 | mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); |
| ... | ... | @@ -924,8 +924,8 @@ |
| 924 | 924 | |
| 925 | 925 | /* set speed */ |
| 926 | 926 | if (speed == _1000BASET) { |
| 927 | -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
| 928 | - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| 927 | +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
| 928 | + defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
| 929 | 929 | unsigned long pfc1; |
| 930 | 930 | |
| 931 | 931 | mfsdr (sdr_pfc1, pfc1); |