OneNAND Initial Program Loader (IPL) support

This patch enables the OneNAND boot within U-Boot. Before this work, we used another OneNAND IPL called X-Loader based on open source. With this work, we can build the oneboot.bin image without other program. The build sequence is simple. First, it compiles the u-boot.bin Second, it compiles OneNAND IPL Finally, it becomes the oneboot.bin from OneNAND IPL and u-boot.bin The mechanism is similar with NAND boot except it boots from itself. Another thing is that you can only use the OneNAND IPL only to work other bootloader such as RedBoot and so on. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

OneNAND Initial Program Loader (IPL) support
This patch enables the OneNAND boot within U-Boot. Before this work, we used another OneNAND IPL called X-Loader based on open source. With this work, we can build the oneboot.bin image without other program. The build sequence is simple. First, it compiles the u-boot.bin Second, it compiles OneNAND IPL Finally, it becomes the oneboot.bin from OneNAND IPL and u-boot.bin The mechanism is similar with NAND boot except it boots from itself. Another thing is that you can only use the OneNAND IPL only to work other bootloader such as RedBoot and so on. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park · Wolfgang Denk
1 parent 21f6f9636f
Showing 11 changed files with 698 additions and 2 deletions Side-by-side Diff
Makefile
board/apollon/apollon.c
cpu/arm1136/start.S
onenand_ipl/board/apollon/Makefile
onenand_ipl/board/apollon/apollon.c
onenand_ipl/board/apollon/config.mk
onenand_ipl/board/apollon/low_levelinit.S
onenand_ipl/board/apollon/u-boot.onenand.lds
onenand_ipl/onenand_boot.c
onenand_ipl/onenand_ipl.h
onenand_ipl/onenand_read.c
@@ -274,13 +274,18 @@
 U_BOOT_NAND = $(obj)u-boot-nand.bin
 endif
  
+ifeq ($(CONFIG_ONENAND_U_BOOT),y)
+ONENAND_IPL = onenand_ipl
+U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS))
  
 #########################################################################
 #########################################################################
  
-ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
+ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
  
 all:		$(ALL)
  
@@ -327,6 +332,12 @@
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
  
+$(ONENAND_IPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
+
+$(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
+		cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
+
 $(VERSION_FILE):
 		@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
 		echo -n "$(U_BOOT_VERSION)" ; \
  
@@ -2597,7 +2608,9 @@
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
  
 apollon_config		: unconfig
+	@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
 	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
+	@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
  
 #========================================================================
 # i386
@@ -2898,6 +2911,8 @@
 	@rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
+	@rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
+		$(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
 	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
  
 clobber:	clean
@@ -2912,6 +2927,7 @@
 	@rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
+	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f
 	@[ ! -d $(obj)api_examples ] || find $(obj)api_examples -lname "*" -print | xargs rm -f
  
 ifeq ($(OBJTREE),$(SRCTREE))
@@ -440,7 +440,8 @@
 void muxSetupGPMC(void)
 {
 	/* gpmc_io_dir, MCR */
-	writel(0x4800008C, 0x19000000);
+	volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
+	*MCR = 0x19000000;
  
 	/* NOR FLASH CS0 */
 	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
@@ -35,6 +35,25 @@
 #endif
 .globl _start
 _start: b	reset
+#ifdef CONFIG_ONENAND_IPL
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -51,6 +70,7 @@
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_ONENAND_IPL */
 .global _end_vect
 _end_vect:
  
  
@@ -139,7 +159,9 @@
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
 	cmp	r0, r1			/* don't reloc during debug	    */
+#ifndef CONFIG_ONENAND_IPL
 	beq	stack_setup
+#endif	/* CONFIG_ONENAND_IPL */
  
 	ldr	r2, _armboot_start
 	ldr	r3, _bss_start
  
  
  
  
  
@@ -156,26 +178,36 @@
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+#ifdef CONFIG_ONENAND_IPL
+	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
+#else
 	sub	r0, r0, #CFG_MALLOC_LEN /* malloc area			    */
 	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo			    */
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+#endif	/* CONFIG_ONENAND_IPL */
  
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment	    */
 	ldr	r1, _bss_end		/* stop here			    */
 	mov	r2, #0x00000000		/* clear			    */
  
+#ifndef CONFIG_ONENAND_IPL
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
+#endif
  
 	ldr	pc, _start_armboot
  
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
 _start_armboot: .word start_armboot
+#endif
  
  
 /*
@@ -214,6 +246,8 @@
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
+
+#ifndef CONFIG_ONENAND_IPL
 /*
  *************************************************************************
  *
  
  
@@ -326,11 +360,18 @@
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
+#endif	/* CONFIG_ONENAND_IPL */
  
 /*
  * exception handlers
  */
+#ifdef CONFIG_ONENAND_IPL
 	.align	5
+do_hang:
+	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_ONENAND IPL */
+	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
@@ -415,4 +456,5 @@
 	.word	PM_RSTCTRL_WKUP
  
 #endif
+#endif	/* CONFIG_ONENAND_IPL */
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/include/config.mk
+include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_ONENAND_IPL
+CFLAGS	+= -DCONFIG_ONENAND_IPL
+OBJCLFAGS += --gap-fill=0x00
+
+SOBJS	= start.o low_levelinit.o # _memcpy32.o
+COBJS	= apollon.o onenand_read.o onenand_boot.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
+
+onenandobj	:= $(OBJTREE)/onenand_ipl/
+
+ALL	= $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(onenandobj)onenand-ipl-2k.bin:	$(onenandobj)onenand-ipl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
+
+$(onenandobj)onenand-ipl.bin:	$(onenandobj)onenand-ipl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(onenandobj)onenand-ipl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+		-Map $(onenandobj)onenand-ipl.map \
+		-o $(onenandobj)onenand-ipl
+
+# create symbolic links from common files
+
+# from cpu directory
+$(obj)start.S:
+	rm -f $(obj)start.S
+	ln -s $(SRCTREE)/cpu/$(CPU)/start.S $(obj)start.S
+
+# from onenand_ipl directory
+$(obj)onenand_ipl.h:
+	rm -f $(obj)onenand_ipl.h
+	ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $(obj)onenand_ipl.h
+
+$(obj)onenand_boot.c:	$(obj)onenand_ipl.h
+	rm -f $(obj)onenand_boot.c
+	ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $(obj)onenand_boot.c
+
+$(obj)onenand_read.c:	$(obj)onenand_ipl.h
+	rm -f $(obj)onenand_read.c
+	ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $(obj)onenand_read.c
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)$.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mux.h>
+
+#define write_config_reg(reg, value)                                    \
+do {                                                                    \
+	writeb(value, reg);                                             \
+} while (0)
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+	return 0;
+}
+
+#ifdef CFG_PRINTF
+/* Pin Muxing registers used for UART1 */
+/****************************************
+ * Routine: muxSetupUART1  (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+static void muxSetupUART1(void)
+{
+	/* UART1_CTS pin configuration, PIN = D21 */
+	write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
+	/* UART1_RTS pin configuration, PIN = H21 */
+	write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
+	/* UART1_TX pin configuration, PIN = L20 */
+	write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
+	/* UART1_RX pin configuration, PIN = T21 */
+	write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
+}
+#endif
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+int s_init(int skip)
+{
+#ifdef CFG_PRINTF
+	muxSetupUART1();
+#endif
+	return 0;
+}
+#
+# (C) Copyright 2005-2008 Samsung Electronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# Samsung Apollon board with OMAP2420 (ARM1136) cpu
+#
+# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+# 8800'0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+TEXT_BASE = 0x00000000
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from board/omap2420h4/platform.S
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+#define APOLLON_CS0_BASE	0x00000000
+
+#ifdef PRCM_CONFIG_I
+#define SDRC_ACTIM_CTRLA_0_VAL	0x7BA35907
+#define SDRC_ACTIM_CTRLB_0_VAL	0x00000013
+#define SDRC_RFR_CTRL_0_VAL	0x00044C01
+
+/* GPMC */
+#define APOLLON_GPMC_CONFIG1_0	0xe30d1201
+#define APOLLON_GPMC_CONFIG2_0	0x000c1000
+#define APOLLON_GPMC_CONFIG3_0	0x00030400
+#define APOLLON_GPMC_CONFIG4_0	0x0B841006
+#define APOLLON_GPMC_CONFIG5_0	0x020F0C11
+#define APOLLON_GPMC_CONFIG6_0	0x00000000
+#define APOLLON_GPMC_CONFIG7_0	(0x00000e40 | (APOLLON_CS0_BASE >> 24))
+
+#elif defined(PRCM_CONFIG_II)
+#define SDRC_ACTIM_CTRLA_0_VAL	0x4A59B485
+#define SDRC_ACTIM_CTRLB_0_VAL	0x0000000C
+#define SDRC_RFR_CTRL_0_VAL	0x00030001
+
+/* GPMC */
+#define APOLLON_GPMC_CONFIG1_0	0xe30d1201
+#define APOLLON_GPMC_CONFIG2_0	0x00080E81
+#define APOLLON_GPMC_CONFIG3_0	0x00030400
+#define APOLLON_GPMC_CONFIG4_0	0x08041586
+#define APOLLON_GPMC_CONFIG5_0	0x020C090E
+#define APOLLON_GPMC_CONFIG6_0	0x00000000
+#define APOLLON_GPMC_CONFIG7_0	(0x00000e40 | (APOLLON_CS0_BASE >> 24))
+
+#else
+#error "Please configure PRCM schecm"
+#endif
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+	mov r3, r0     /* save skip information */
+
+	/* Disable watchdog */
+	ldr	r0, =WD2_BASE
+	ldr	r1, =WD_UNLOCK1
+	str	r1, [r0, #WSPR]
+
+	ldr	r1, =WD_UNLOCK2
+	str	r1, [r0, #WSPR]
+
+#ifdef DEBUG_LED
+	/* LED0 OFF */
+	ldr	r0, =0x480000E5		/* ball AA10, mode 3 */
+	mov	r1, #0x0b
+	strb	r1, [r0]
+#endif
+
+	/* Pin muxing for SDRC */
+	mov	r1, #0x00
+	ldr	r0, =0x480000A1		/* ball C12, mode 0 */
+	strb	r1, [r0]
+
+	ldr	r0, =0x48000032		/* ball D11, mode 0 */
+	strb	r1, [r0]
+
+	ldr	r0, =0x480000A3		/* ball B13, mode 0 */
+	strb	r1, [r0]
+
+	/* SDRC setting */
+	ldr	r0, =OMAP2420_SDRC_BASE
+	ldr	r1, =0x00000010
+	str	r1, [r0, #0x10]
+
+	ldr	r1, =0x00000100
+	str	r1, [r0, #0x44]
+
+	/* SDRC CS0 configuration */
+#ifdef CONFIG_APOLLON_PLUS
+	ldr	r1, =0x01702011
+#else
+	ldr	r1, =0x00d04011
+#endif
+	str	r1, [r0, #0x80]
+
+	ldr	r1, =SDRC_ACTIM_CTRLA_0_VAL
+	str	r1, [r0, #0x9C]
+
+	ldr	r1, =SDRC_ACTIM_CTRLB_0_VAL
+	str	r1, [r0, #0xA0]
+
+	ldr	r1, =SDRC_RFR_CTRL_0_VAL
+	str	r1, [r0, #0xA4]
+
+	ldr	r1, =0x00000041
+	str	r1, [r0, #0x70]
+
+	/* Manual command sequence */
+	ldr	r1, =0x00000007
+	str	r1, [r0, #0xA8]
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0xA8]
+
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xA8]
+
+	ldr	r1, =0x00000002
+	str	r1, [r0, #0xA8]
+	str	r1, [r0, #0xA8]
+
+	/*
+	 * CS0 SDRC Mode register
+	 *   Burst length = 4 - DDR memory
+	 *   Serial mode
+	 *   CAS latency = 3
+	 */
+	ldr	r1, =0x00000032
+	str	r1, [r0, #0x84]
+
+	/* Note: You MUST set EMR values */
+	/* EMR1 & EMR2 */
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x88]
+	str	r1, [r0, #0x8C]
+
+#ifdef OLD_SDRC_DLLA_CTRL
+	/* SDRC_DLLA_CTRL */
+	ldr	r1, =0x00007306
+	str	r1, [r0, #0x60]
+
+	ldr	r1, =0x00007303
+	str	r1, [r0, #0x60]
+#else
+	/* SDRC_DLLA_CTRL */
+	ldr	r1, =0x00000506
+	str	r1, [r0, #0x60]
+
+	ldr	r1, =0x00000503
+	str	r1, [r0, #0x60]
+#endif
+
+#ifdef __BROKEN_FEATURE__
+	/* SDRC_DLLB_CTRL */
+	ldr	r1, =0x00000506
+	str	r1, [r0, #0x68]
+
+	ldr	r1, =0x00000503
+	str	r1, [r0, #0x68]
+#endif
+
+	/* little delay after init */
+	mov	r2, #0x1800
+1:
+	subs	r2, r2, #0x1
+        bne	1b
+
+	ldr	sp, SRAM_STACK
+        str     ip, [sp]	/* stash old link register */
+	mov	ip, lr		/* save link reg across call */
+        mov     r0, r3		/* pass skip info to s_init */
+
+        bl      s_init		/* go setup pll,mux,memory */
+
+        ldr     ip, [sp]	/* restore save ip */
+	mov	lr, ip		/* restore link reg */
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from X-loader
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Derived from x-loader
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <version.h>
+
+#include "onenand_ipl.h"
+
+#ifdef CFG_PRINTF
+int print_info(void)
+{
+	printf(XLOADER_VERSION);
+
+	return 0;
+}
+#endif
+
+typedef int (init_fnc_t)(void);
+
+init_fnc_t *init_sequence[] = {
+	board_init,		/* basic board dependent setup */
+#ifdef CFG_PRINTF
+	serial_init,		/* serial communications setup */
+	print_info,
+#endif
+	NULL,
+};
+
+void start_oneboot(void)
+{
+	init_fnc_t **init_fnc_ptr;
+	uchar *buf;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	buf = (uchar *) CFG_LOAD_ADDR;
+
+	if (!onenand_read_block(buf, ONENAND_START_BLOCK))
+		buf += ONENAND_BLOCK_SIZE;
+
+	if (buf == (uchar *)CFG_LOAD_ADDR)
+		hang();
+
+	/* go run U-Boot and never return */
+	printf("Starting OS Bootloader...\n");
+	((init_fnc_t *)CFG_LOAD_ADDR)();
+
+	/* should never come here */
+}
+
+void hang(void)
+{
+	/* if board_hang() returns, hange here */
+	printf("X-Loader hangs\n");
+	for (;;);
+}
+/*
+ * (C) Copyright 2005-2008 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ONENAND_IPL_H
+#define _ONENAND_IPL_H
+
+#include <linux/mtd/onenand_regs.h>
+
+#define ONENAND_START_BLOCK             0
+#define ONENAND_BLOCK_SIZE              2048
+
+#ifndef CFG_PRINTF
+#define printf(format, args...)
+#endif
+
+#define onenand_readw(a)        readw(a)
+#define onenand_writew(v, a)    writew(v, a)
+
+#define THIS_ONENAND(a)         (CFG_ONENAND_BASE + (a))
+
+#define READ_INTERRUPT()                                                \
+	onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT))
+
+#define ONENAND_PAGE_SIZE                       2048
+
+extern int onenand_read_block(unsigned char *buf, ulong block);
+#endif
+/*
+ * (C) Copyright 2005-2008 Samsung Electronis
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/string.h>
+
+#include "onenand_ipl.h"
+
+#define onenand_block_address(block)		(block)
+#define onenand_sector_address(page)		(page << 2)
+#define onenand_buffer_address()		((1 << 3) << 8)
+#define onenand_bufferram_address(block)	(0)
+
+/* read a page with ECC */
+static inline int onenand_read_page(ulong block, ulong page, u_char *buf)
+{
+	unsigned long *base;
+
+#ifndef __HAVE_ARCH_MEMCPY32
+	unsigned int offset, value;
+	unsigned long *p;
+#endif
+
+	onenand_writew(onenand_block_address(block),
+		THIS_ONENAND(ONENAND_REG_START_ADDRESS1));
+
+	onenand_writew(onenand_sector_address(page),
+		THIS_ONENAND(ONENAND_REG_START_ADDRESS8));
+
+	onenand_writew(onenand_buffer_address(),
+		THIS_ONENAND(ONENAND_REG_START_BUFFER));
+
+	onenand_writew(onenand_bufferram_address(block),
+		THIS_ONENAND(ONENAND_REG_START_ADDRESS2));
+
+	onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT));
+
+	onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND));
+
+#ifndef __HAVE_ARCH_MEMCPY32
+	p = (unsigned long *) buf;
+#endif
+	base = (unsigned long *) (CFG_ONENAND_BASE + ONENAND_DATARAM);
+
+	while (!(READ_INTERRUPT() & ONENAND_INT_READ))
+		continue;
+
+#ifdef __HAVE_ARCH_MEMCPY32
+	/* 32 bytes boundary memory copy */
+	memcpy32(buf, base, ONENAND_PAGE_SIZE);
+#else
+	for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) {
+		value = *(base + offset);
+		*p++ = value;
+	}
+#endif
+
+	return 0;
+}
+
+#define ONENAND_START_PAGE		1
+#define ONENAND_PAGES_PER_BLOCK		64
+
+/**
+ * onenand_read_block - Read a block data to buf
+ * @return 0 on success
+ */
+int onenand_read_block(unsigned char *buf, ulong block)
+{
+	int page, offset = 0;
+
+	/* NOTE: you must read page from page 1 of block 0 */
+	/* read the block page by page*/
+	for (page = ONENAND_START_PAGE;
+	    page < ONENAND_PAGES_PER_BLOCK; page++) {
+
+		onenand_read_page(block, page, buf + offset);
+
+		offset += ONENAND_PAGE_SIZE;
+	}
+
+	return 0;
+}
...	...	@@ -274,13 +274,18 @@
274	274	U_BOOT_NAND = $(obj)u-boot-nand.bin
275	275	endif
276	276
	277	+ifeq ($(CONFIG_ONENAND_U_BOOT),y)
	278	+ONENAND_IPL = onenand_ipl
	279	+U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
	280	+endif
	281	+
277	282	__OBJS := $(subst $(obj),,$(OBJS))
278	283	__LIBS := $(subst $(obj),,$(LIBS))
279	284
280	285	#########################################################################
281	286	#########################################################################
282	287
283		-ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
	288	+ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
284	289
285	290	all: $(ALL)
286	291
...	...	@@ -327,6 +332,12 @@
327	332	$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
328	333	cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
329	334
	335	+$(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk
	336	+ $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
	337	+
	338	+$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
	339	+ cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
	340	+
330	341	$(VERSION_FILE):
331	342	@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
332	343	echo -n "$(U_BOOT_VERSION)" ; \
333	344
...	...	@@ -2597,7 +2608,9 @@
2597	2608	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
2598	2609
2599	2610	apollon_config : unconfig
	2611	+ @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
2600	2612	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon
	2613	+ @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
2601	2614
2602	2615	#========================================================================
2603	2616	# i386
...	...	@@ -2898,6 +2911,8 @@
2898	2911	@rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
2899	2912	@rm -f $(obj)include/bmp_logo.h
2900	2913	@rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
	2914	+ @rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
	2915	+ $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
2901	2916	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
2902	2917
2903	2918	clobber: clean
...	...	@@ -2912,6 +2927,7 @@
2912	2927	@rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
2913	2928	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
2914	2929	@[ ! -d $(obj)nand_spl ] \|\| find $(obj)nand_spl -lname "*" -print \| xargs rm -f
	2930	+ @[ ! -d $(obj)onenand_ipl ] \|\| find $(obj)onenand_ipl -lname "*" -print \| xargs rm -f
2915	2931	@[ ! -d $(obj)api_examples ] \|\| find $(obj)api_examples -lname "*" -print \| xargs rm -f
2916	2932
2917	2933	ifeq ($(OBJTREE),$(SRCTREE))
...	...	@@ -440,7 +440,8 @@
440	440	void muxSetupGPMC(void)
441	441	{
442	442	/* gpmc_io_dir, MCR */
443		- writel(0x4800008C, 0x19000000);
	443	+ volatile unsigned int MCR = (unsigned int ) 0x4800008C;
	444	+ *MCR = 0x19000000;
444	445
445	446	/* NOR FLASH CS0 */
446	447	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
...	...	@@ -35,6 +35,25 @@
35	35	#endif
36	36	.globl _start
37	37	_start: b reset
	38	+#ifdef CONFIG_ONENAND_IPL
	39	+ ldr pc, _hang
	40	+ ldr pc, _hang
	41	+ ldr pc, _hang
	42	+ ldr pc, _hang
	43	+ ldr pc, _hang
	44	+ ldr pc, _hang
	45	+ ldr pc, _hang
	46	+
	47	+_hang:
	48	+ .word do_hang
	49	+ .word 0x12345678
	50	+ .word 0x12345678
	51	+ .word 0x12345678
	52	+ .word 0x12345678
	53	+ .word 0x12345678
	54	+ .word 0x12345678
	55	+ .word 0x12345678 /* now 164=64 /
	56	+#else
38	57	ldr pc, _undefined_instruction
39	58	ldr pc, _software_interrupt
40	59	ldr pc, _prefetch_abort
...	...	@@ -51,6 +70,7 @@
51	70	_irq: .word irq
52	71	_fiq: .word fiq
53	72	_pad: .word 0x12345678 /* now 164=64 /
	73	+#endif /* CONFIG_ONENAND_IPL */
54	74	.global _end_vect
55	75	_end_vect:
56	76
57	77
...	...	@@ -139,7 +159,9 @@
139	159	adr r0, _start /* r0 <- current position of code */
140	160	ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
141	161	cmp r0, r1 /* don't reloc during debug */
	162	+#ifndef CONFIG_ONENAND_IPL
142	163	beq stack_setup
	164	+#endif /* CONFIG_ONENAND_IPL */
143	165
144	166	ldr r2, _armboot_start
145	167	ldr r3, _bss_start
146	168
147	169
148	170
149	171
150	172
...	...	@@ -156,26 +178,36 @@
156	178	/* Set up the stack */
157	179	stack_setup:
158	180	ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
	181	+#ifdef CONFIG_ONENAND_IPL
	182	+ sub sp, r0, #128 /* leave 32 words for abort-stack */
	183	+#else
159	184	sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
160	185	sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
161	186	#ifdef CONFIG_USE_IRQ
162	187	sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
163	188	#endif
164	189	sub sp, r0, #12 /* leave 3 words for abort-stack */
	190	+#endif /* CONFIG_ONENAND_IPL */
165	191
166	192	clear_bss:
167	193	ldr r0, _bss_start /* find start of bss segment */
168	194	ldr r1, _bss_end /* stop here */
169	195	mov r2, #0x00000000 /* clear */
170	196
	197	+#ifndef CONFIG_ONENAND_IPL
171	198	clbss_l:str r2, [r0] /* clear loop... */
172	199	add r0, r0, #4
173	200	cmp r0, r1
174	201	bne clbss_l
	202	+#endif
175	203
176	204	ldr pc, _start_armboot
177	205
	206	+#ifdef CONFIG_ONENAND_IPL
	207	+_start_armboot: .word start_oneboot
	208	+#else
178	209	_start_armboot: .word start_armboot
	210	+#endif
179	211
180	212
181	213	/*
...	...	@@ -214,6 +246,8 @@
214	246	bl lowlevel_init /* go setup pll,mux,memory */
215	247	mov lr, ip /* restore link */
216	248	mov pc, lr /* back to my caller */
	249	+
	250	+#ifndef CONFIG_ONENAND_IPL
217	251	/*
218	252	*************************************************************************
219	253	*
220	254
221	255
...	...	@@ -326,11 +360,18 @@
326	360	.macro get_fiq_stack @ setup FIQ stack
327	361	ldr sp, FIQ_STACK_START
328	362	.endm
	363	+#endif /* CONFIG_ONENAND_IPL */
329	364
330	365	/*
331	366	* exception handlers
332	367	*/
	368	+#ifdef CONFIG_ONENAND_IPL
333	369	.align 5
	370	+do_hang:
	371	+ ldr sp, _TEXT_BASE /* use 32 words about stack */
	372	+ bl hang /* hang and never return */
	373	+#else /* !CONFIG_ONENAND IPL */
	374	+ .align 5
334	375	undefined_instruction:
335	376	get_bad_stack
336	377	bad_save_user_regs
...	...	@@ -415,4 +456,5 @@
415	456	.word PM_RSTCTRL_WKUP
416	457
417	458	#endif
	459	+#endif /* CONFIG_ONENAND_IPL */
	1	+
	2	+include $(TOPDIR)/config.mk
	3	+include $(TOPDIR)/include/config.mk
	4	+include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
	5	+
	6	+LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
	7	+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
	8	+AFLAGS += -DCONFIG_ONENAND_IPL
	9	+CFLAGS += -DCONFIG_ONENAND_IPL
	10	+OBJCLFAGS += --gap-fill=0x00
	11	+
	12	+SOBJS = start.o low_levelinit.o # _memcpy32.o
	13	+COBJS = apollon.o onenand_read.o onenand_boot.o
	14	+
	15	+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
	16	+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
	17	+__OBJS := $(SOBJS) $(COBJS)
	18	+LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
	19	+
	20	+onenandobj := $(OBJTREE)/onenand_ipl/
	21	+
	22	+ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
	23	+
	24	+all: $(obj).depend $(ALL)
	25	+
	26	+$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
	27	+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
	28	+
	29	+$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
	30	+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
	31	+
	32	+$(onenandobj)onenand-ipl: $(OBJS)
	33	+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
	34	+ -Map $(onenandobj)onenand-ipl.map \
	35	+ -o $(onenandobj)onenand-ipl
	36	+
	37	+# create symbolic links from common files
	38	+
	39	+# from cpu directory
	40	+$(obj)start.S:
	41	+ rm -f $(obj)start.S
	42	+ ln -s $(SRCTREE)/cpu/$(CPU)/start.S $(obj)start.S
	43	+
	44	+# from onenand_ipl directory
	45	+$(obj)onenand_ipl.h:
	46	+ rm -f $(obj)onenand_ipl.h
	47	+ ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $(obj)onenand_ipl.h
	48	+
	49	+$(obj)onenand_boot.c: $(obj)onenand_ipl.h
	50	+ rm -f $(obj)onenand_boot.c
	51	+ ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $(obj)onenand_boot.c
	52	+
	53	+$(obj)onenand_read.c: $(obj)onenand_ipl.h
	54	+ rm -f $(obj)onenand_read.c
	55	+ ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $(obj)onenand_read.c
	56	+
	57	+$(obj)%.o: $(obj)%.S
	58	+ $(CC) $(AFLAGS) -c -o $@ $<
	59	+
	60	+$(obj)%.o: $(obj)$.c
	61	+ $(CC) $(CFLAGS) -c -o $@ $<
	62	+
	63	+include $(SRCTREE)/rules.mk
	64	+
	65	+sinclude $(obj).depend
	1	+/*
	2	+ * (C) Copyright 2005-2008 Samsung Electronics
	3	+ * Kyungmin Park <kyungmin.park@samsung.com>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+#include <common.h>
	24	+#include <asm/arch/mux.h>
	25	+
	26	+#define write_config_reg(reg, value) \
	27	+do { \
	28	+ writeb(value, reg); \
	29	+} while (0)
	30	+
	31	+/*****************************************
	32	+ * Routine: board_init
	33	+ * Description: Early hardware init.
	34	+ *****************************************/
	35	+int board_init(void)
	36	+{
	37	+ return 0;
	38	+}
	39	+
	40	+#ifdef CFG_PRINTF
	41	+/* Pin Muxing registers used for UART1 */
	42	+/****************************************
	43	+ * Routine: muxSetupUART1 (ostboot)
	44	+ * Description: Set up uart1 muxing
	45	+ *****************************************/
	46	+static void muxSetupUART1(void)
	47	+{
	48	+ /* UART1_CTS pin configuration, PIN = D21 */
	49	+ write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
	50	+ /* UART1_RTS pin configuration, PIN = H21 */
	51	+ write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
	52	+ /* UART1_TX pin configuration, PIN = L20 */
	53	+ write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
	54	+ /* UART1_RX pin configuration, PIN = T21 */
	55	+ write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
	56	+}
	57	+#endif
	58	+
	59	+/**********************************************************
	60	+ * Routine: s_init
	61	+ * Description: Does early system init of muxing and clocks.
	62	+ * - Called at time when only stack is available.
	63	+ **********************************************************/
	64	+int s_init(int skip)
	65	+{
	66	+#ifdef CFG_PRINTF
	67	+ muxSetupUART1();
	68	+#endif
	69	+ return 0;
	70	+}
	1	+#
	2	+# (C) Copyright 2005-2008 Samsung Electronics
	3	+# Kyungmin Park <kyungmin.park@samsung.com>
	4	+#
	5	+# Samsung Apollon board with OMAP2420 (ARM1136) cpu
	6	+#
	7	+# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0
	8	+# Physical Address:
	9	+# 8000'0000 (bank0)
	10	+# 8800'0000 (bank1)
	11	+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
	12	+# (mem base + reserved)
	13	+
	14	+TEXT_BASE = 0x00000000
	1	+/*
	2	+ * Board specific setup info
	3	+ *
	4	+ * (C) Copyright 2005-2008 Samsung Electronics
	5	+ * Kyungmin Park <kyungmin.park@samsung.com>
	6	+ *
	7	+ * Derived from board/omap2420h4/platform.S
	8	+ *
	9	+ * See file CREDITS for list of people who contributed to this
	10	+ * project.
	11	+ *
	12	+ * This program is free software; you can redistribute it and/or
	13	+ * modify it under the terms of the GNU General Public License as
	14	+ * published by the Free Software Foundation; either version 2 of
	15	+ * the License, or (at your option) any later version.
	16	+ *
	17	+ * This program is distributed in the hope that it will be useful,
	18	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+ * GNU General Public License for more details.
	21	+ *
	22	+ * You should have received a copy of the GNU General Public License
	23	+ * along with this program; if not, write to the Free Software
	24	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+ * MA 02111-1307 USA
	26	+ */
	27	+
	28	+#include <config.h>
	29	+#include <asm/arch/omap2420.h>
	30	+#include <asm/arch/mem.h>
	31	+#include <asm/arch/clocks.h>
	32	+
	33	+#define APOLLON_CS0_BASE 0x00000000
	34	+
	35	+#ifdef PRCM_CONFIG_I
	36	+#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
	37	+#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
	38	+#define SDRC_RFR_CTRL_0_VAL 0x00044C01
	39	+
	40	+/* GPMC */
	41	+#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
	42	+#define APOLLON_GPMC_CONFIG2_0 0x000c1000
	43	+#define APOLLON_GPMC_CONFIG3_0 0x00030400
	44	+#define APOLLON_GPMC_CONFIG4_0 0x0B841006
	45	+#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
	46	+#define APOLLON_GPMC_CONFIG6_0 0x00000000
	47	+#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 \| (APOLLON_CS0_BASE >> 24))
	48	+
	49	+#elif defined(PRCM_CONFIG_II)
	50	+#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
	51	+#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
	52	+#define SDRC_RFR_CTRL_0_VAL 0x00030001
	53	+
	54	+/* GPMC */
	55	+#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
	56	+#define APOLLON_GPMC_CONFIG2_0 0x00080E81
	57	+#define APOLLON_GPMC_CONFIG3_0 0x00030400
	58	+#define APOLLON_GPMC_CONFIG4_0 0x08041586
	59	+#define APOLLON_GPMC_CONFIG5_0 0x020C090E
	60	+#define APOLLON_GPMC_CONFIG6_0 0x00000000
	61	+#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 \| (APOLLON_CS0_BASE >> 24))
	62	+
	63	+#else
	64	+#error "Please configure PRCM schecm"
	65	+#endif
	66	+
	67	+_TEXT_BASE:
	68	+ .word TEXT_BASE /* sdram load addr from config.mk */
	69	+
	70	+.globl lowlevel_init
	71	+lowlevel_init:
	72	+ mov r3, r0 /* save skip information */
	73	+
	74	+ /* Disable watchdog */
	75	+ ldr r0, =WD2_BASE
	76	+ ldr r1, =WD_UNLOCK1
	77	+ str r1, [r0, #WSPR]
	78	+
	79	+ ldr r1, =WD_UNLOCK2
	80	+ str r1, [r0, #WSPR]
	81	+
	82	+#ifdef DEBUG_LED
	83	+ /* LED0 OFF */
	84	+ ldr r0, =0x480000E5 /* ball AA10, mode 3 */
	85	+ mov r1, #0x0b
	86	+ strb r1, [r0]
	87	+#endif
	88	+
	89	+ /* Pin muxing for SDRC */
	90	+ mov r1, #0x00
	91	+ ldr r0, =0x480000A1 /* ball C12, mode 0 */
	92	+ strb r1, [r0]
	93	+
	94	+ ldr r0, =0x48000032 /* ball D11, mode 0 */
	95	+ strb r1, [r0]
	96	+
	97	+ ldr r0, =0x480000A3 /* ball B13, mode 0 */
	98	+ strb r1, [r0]
	99	+
	100	+ /* SDRC setting */
	101	+ ldr r0, =OMAP2420_SDRC_BASE
	102	+ ldr r1, =0x00000010
	103	+ str r1, [r0, #0x10]
	104	+
	105	+ ldr r1, =0x00000100
	106	+ str r1, [r0, #0x44]
	107	+
	108	+ /* SDRC CS0 configuration */
	109	+#ifdef CONFIG_APOLLON_PLUS
	110	+ ldr r1, =0x01702011
	111	+#else
	112	+ ldr r1, =0x00d04011
	113	+#endif
	114	+ str r1, [r0, #0x80]
	115	+
	116	+ ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
	117	+ str r1, [r0, #0x9C]
	118	+
	119	+ ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
	120	+ str r1, [r0, #0xA0]
	121	+
	122	+ ldr r1, =SDRC_RFR_CTRL_0_VAL
	123	+ str r1, [r0, #0xA4]
	124	+
	125	+ ldr r1, =0x00000041
	126	+ str r1, [r0, #0x70]
	127	+
	128	+ /* Manual command sequence */
	129	+ ldr r1, =0x00000007
	130	+ str r1, [r0, #0xA8]
	131	+
	132	+ ldr r1, =0x00000000
	133	+ str r1, [r0, #0xA8]
	134	+
	135	+ ldr r1, =0x00000001
	136	+ str r1, [r0, #0xA8]
	137	+
	138	+ ldr r1, =0x00000002
	139	+ str r1, [r0, #0xA8]
	140	+ str r1, [r0, #0xA8]
	141	+
	142	+ /*
	143	+ * CS0 SDRC Mode register
	144	+ * Burst length = 4 - DDR memory
	145	+ * Serial mode
	146	+ * CAS latency = 3
	147	+ */
	148	+ ldr r1, =0x00000032
	149	+ str r1, [r0, #0x84]
	150	+
	151	+ /* Note: You MUST set EMR values */
	152	+ /* EMR1 & EMR2 */
	153	+ ldr r1, =0x00000000
	154	+ str r1, [r0, #0x88]
	155	+ str r1, [r0, #0x8C]
	156	+
	157	+#ifdef OLD_SDRC_DLLA_CTRL
	158	+ /* SDRC_DLLA_CTRL */
	159	+ ldr r1, =0x00007306
	160	+ str r1, [r0, #0x60]
	161	+
	162	+ ldr r1, =0x00007303
	163	+ str r1, [r0, #0x60]
	164	+#else
	165	+ /* SDRC_DLLA_CTRL */
	166	+ ldr r1, =0x00000506
	167	+ str r1, [r0, #0x60]
	168	+
	169	+ ldr r1, =0x00000503
	170	+ str r1, [r0, #0x60]
	171	+#endif
	172	+
	173	+#ifdef __BROKEN_FEATURE__
	174	+ /* SDRC_DLLB_CTRL */
	175	+ ldr r1, =0x00000506
	176	+ str r1, [r0, #0x68]
	177	+
	178	+ ldr r1, =0x00000503
	179	+ str r1, [r0, #0x68]
	180	+#endif
	181	+
	182	+ /* little delay after init */
	183	+ mov r2, #0x1800
	184	+1:
	185	+ subs r2, r2, #0x1
	186	+ bne 1b
	187	+
	188	+ ldr sp, SRAM_STACK
	189	+ str ip, [sp] /* stash old link register */
	190	+ mov ip, lr /* save link reg across call */
	191	+ mov r0, r3 /* pass skip info to s_init */
	192	+
	193	+ bl s_init /* go setup pll,mux,memory */
	194	+
	195	+ ldr ip, [sp] /* restore save ip */
	196	+ mov lr, ip /* restore link reg */
	197	+
	198	+ /* back to arch calling code */
	199	+ mov pc, lr
	200	+
	201	+ /* the literal pools origin */
	202	+ .ltorg
	203	+
	204	+SRAM_STACK:
	205	+ .word LOW_LEVEL_SRAM_STACK
	1	+/*
	2	+ * (C) Copyright 2005-2008 Samsung Electronics
	3	+ * Kyungmin Park <kyungmin.park@samsung.com>
	4	+ *
	5	+ * Derived from X-loader
	6	+ *
	7	+ * See file CREDITS for list of people who contributed to this
	8	+ * project.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
	27	+OUTPUT_ARCH(arm)
	28	+ENTRY(_start)
	29	+SECTIONS
	30	+{
	31	+ . = 0x00000000;
	32	+
	33	+ . = ALIGN(4);
	34	+ .text :
	35	+ {
	36	+ start.o (.text)
	37	+ *(.text)
	38	+ }
	39	+
	40	+ . = ALIGN(4);
	41	+ .rodata : { *(.rodata) }
	42	+
	43	+ . = ALIGN(4);
	44	+ .data : { *(.data) }
	45	+
	46	+ . = ALIGN(4);
	47	+ .got : { *(.got) }
	48	+
	49	+ . = ALIGN(4);
	50	+ __bss_start = .;
	51	+ .bss : { *(.bss) }
	52	+ _end = .;
	53	+}