Eric Lee / smarc-uboot

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Commit 75b2ec2a22964c7e8c51b2e4c903284fe6013b4f

Authored by Vignesh R
Committed by Jagan Teki
1 parent 7287597870
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

configs: Remove SF_DUAL_FLASH 

SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above
enums yield no user and therefore support seems to be incomplete. Remove
these configs so as to avoid confusion.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Showing 17 changed files with 0 additions and 108 deletions Side-by-side Diff

configs/topic_miamilite_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -40,7 +40,6 @@
40 40 CONFIG_MMC_SDHCI_ZYNQ=y
41 41 CONFIG_SPI_FLASH=y
42 42 CONFIG_SPI_FLASH_BAR=y
43   -CONFIG_SF_DUAL_FLASH=y
44 43 CONFIG_SPI_FLASH_STMICRO=y
45 44 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
46 45 CONFIG_DEBUG_UART_ZYNQ=y
configs/topic_miamiplus_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -39,7 +39,6 @@
39 39 CONFIG_MMC_SDHCI_ZYNQ=y
40 40 CONFIG_SPI_FLASH=y
41 41 CONFIG_SPI_FLASH_BAR=y
42   -CONFIG_SF_DUAL_FLASH=y
43 42 CONFIG_SPI_FLASH_STMICRO=y
44 43 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
45 44 # CONFIG_NETDEVICES is not set
configs/xilinx_zynqmp_mini_qspi_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -54,7 +54,6 @@
54 54 # CONFIG_MMC is not set
55 55 CONFIG_SPI_FLASH=y
56 56 CONFIG_SPI_FLASH_BAR=y
57   -CONFIG_SF_DUAL_FLASH=y
58 57 CONFIG_SPI_FLASH_ISSI=y
59 58 CONFIG_SPI_FLASH_MACRONIX=y
60 59 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zc1232_revA_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -38,7 +38,6 @@
38 38 # CONFIG_MMC is not set
39 39 CONFIG_SPI_FLASH=y
40 40 CONFIG_SPI_FLASH_BAR=y
41   -CONFIG_SF_DUAL_FLASH=y
42 41 CONFIG_SPI_FLASH_ISSI=y
43 42 CONFIG_SPI_FLASH_MACRONIX=y
44 43 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zc1254_revA_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -38,7 +38,6 @@
38 38 # CONFIG_MMC is not set
39 39 CONFIG_SPI_FLASH=y
40 40 CONFIG_SPI_FLASH_BAR=y
41   -CONFIG_SF_DUAL_FLASH=y
42 41 CONFIG_SPI_FLASH_ISSI=y
43 42 CONFIG_SPI_FLASH_MACRONIX=y
44 43 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zc1275_revA_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -38,7 +38,6 @@
38 38 # CONFIG_MMC is not set
39 39 CONFIG_SPI_FLASH=y
40 40 CONFIG_SPI_FLASH_BAR=y
41   -CONFIG_SF_DUAL_FLASH=y
42 41 CONFIG_SPI_FLASH_ISSI=y
43 42 CONFIG_SPI_FLASH_MACRONIX=y
44 43 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zc1275_revB_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -42,7 +42,6 @@
42 42 CONFIG_MMC_SDHCI_ZYNQ=y
43 43 CONFIG_SPI_FLASH=y
44 44 CONFIG_SPI_FLASH_BAR=y
45   -CONFIG_SF_DUAL_FLASH=y
46 45 CONFIG_SPI_FLASH_ISSI=y
47 46 CONFIG_SPI_FLASH_MACRONIX=y
48 47 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -62,7 +62,6 @@
62 62 CONFIG_MMC_SDHCI_ZYNQ=y
63 63 CONFIG_SPI_FLASH=y
64 64 CONFIG_SPI_FLASH_BAR=y
65   -CONFIG_SF_DUAL_FLASH=y
66 65 CONFIG_SPI_FLASH_ISSI=y
67 66 CONFIG_SPI_FLASH_MACRONIX=y
68 67 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -48,7 +48,6 @@
48 48 CONFIG_MMC_SDHCI_ZYNQ=y
49 49 CONFIG_SPI_FLASH=y
50 50 CONFIG_SPI_FLASH_BAR=y
51   -CONFIG_SF_DUAL_FLASH=y
52 51 CONFIG_SPI_FLASH_ISSI=y
53 52 CONFIG_SPI_FLASH_MACRONIX=y
54 53 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -75,7 +75,6 @@
75 75 CONFIG_MMC_SDHCI_ZYNQ=y
76 76 CONFIG_SPI_FLASH=y
77 77 CONFIG_SPI_FLASH_BAR=y
78   -CONFIG_SF_DUAL_FLASH=y
79 78 CONFIG_SPI_FLASH_ISSI=y
80 79 CONFIG_SPI_FLASH_MACRONIX=y
81 80 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zcu102_revA_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -73,7 +73,6 @@
73 73 CONFIG_MMC_SDHCI_ZYNQ=y
74 74 CONFIG_SPI_FLASH=y
75 75 CONFIG_SPI_FLASH_BAR=y
76   -CONFIG_SF_DUAL_FLASH=y
77 76 CONFIG_SPI_FLASH_ISSI=y
78 77 CONFIG_SPI_FLASH_MACRONIX=y
79 78 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zcu102_revB_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -73,7 +73,6 @@
73 73 CONFIG_MMC_SDHCI_ZYNQ=y
74 74 CONFIG_SPI_FLASH=y
75 75 CONFIG_SPI_FLASH_BAR=y
76   -CONFIG_SF_DUAL_FLASH=y
77 76 CONFIG_SPI_FLASH_ISSI=y
78 77 CONFIG_SPI_FLASH_MACRONIX=y
79 78 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zcu104_revA_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -58,7 +58,6 @@
58 58 CONFIG_MMC_SDHCI_ZYNQ=y
59 59 CONFIG_SPI_FLASH=y
60 60 CONFIG_SPI_FLASH_BAR=y
61   -CONFIG_SF_DUAL_FLASH=y
62 61 CONFIG_SPI_FLASH_ISSI=y
63 62 CONFIG_SPI_FLASH_MACRONIX=y
64 63 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zcu104_revC_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -59,7 +59,6 @@
59 59 CONFIG_MMC_SDHCI_ZYNQ=y
60 60 CONFIG_SPI_FLASH=y
61 61 CONFIG_SPI_FLASH_BAR=y
62   -CONFIG_SF_DUAL_FLASH=y
63 62 CONFIG_SPI_FLASH_ISSI=y
64 63 CONFIG_SPI_FLASH_MACRONIX=y
65 64 CONFIG_SPI_FLASH_SPANSION=y
configs/xilinx_zynqmp_zcu106_revA_defconfig
Diff comments   View file @ 75b2ec2
... ... @@ -69,7 +69,6 @@
69 69 CONFIG_MMC_SDHCI_ZYNQ=y
70 70 CONFIG_SPI_FLASH=y
71 71 CONFIG_SPI_FLASH_BAR=y
72   -CONFIG_SF_DUAL_FLASH=y
73 72 CONFIG_SPI_FLASH_ISSI=y
74 73 CONFIG_SPI_FLASH_MACRONIX=y
75 74 CONFIG_SPI_FLASH_SPANSION=y
doc/SPI/README.dual-flash
View file @ 75b2ec2
1   -SPI/QSPI Dual flash connection modes:
2   -=====================================
3   -
4   -This describes how SPI/QSPI flash memories are connected to a given
5   -controller in a single chip select line.
6   -
7   -Current spi_flash framework supports, single flash memory connected
8   -to a given controller with single chip select line, but there are some
9   -hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
10   -connected with a single chip select line from a controller.
11   -
12   -"dual_flash" from include/spi.h describes these types of connection mode
13   -
14   -Possible connections:
15   ---------------------
16   -SF_SINGLE_FLASH:
17   - - single spi flash memory connected with single chip select line.
18   -
19   - +------------+ CS +---------------+
20   - | |----------------------->| |
21   - | Controller | I0[3:0] | Flash memory |
22   - | SPI/QSPI |<======================>| (SPI/QSPI) |
23   - | | CLK | |
24   - | |----------------------->| |
25   - +------------+ +---------------+
26   -
27   -SF_DUAL_STACKED_FLASH:
28   - - dual spi/qspi flash memories are connected with a single chipselect
29   - line and these two memories are operating stacked fasion with shared buses.
30   - - xilinx zynq qspi controller has implemented this feature [1]
31   -
32   - +------------+ CS +---------------+
33   - | |---------------------->| |
34   - | | I0[3:0] | Upper Flash |
35   - | | +=========>| memory |
36   - | | | CLK | (SPI/QSPI) |
37   - | | | +---->| |
38   - | Controller | CS | | +---------------+
39   - | SPI/QSPI |------------|----|---->| |
40   - | | I0[3:0] | | | Lower Flash |
41   - | |<===========+====|====>| memory |
42   - | | CLK | | (SPI/QSPI) |
43   - | |-----------------+---->| |
44   - +------------+ +---------------+
45   -
46   - - two memory flash devices should has same hw part attributes (like size,
47   - vendor..etc)
48   - - Configurations:
49   - on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
50   - Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51   - Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
52   - - Operation:
53   - accessing memories serially like one after another.
54   - by default, if U_PAGE is unset lower memory should accessible,
55   - once user wants to access upper memory need to set U_PAGE.
56   -
57   -SPI_FLASH_CONN_DUALPARALLEL:
58   - - dual spi/qspi flash memories are connected with a single chipselect
59   - line and these two memories are operating parallel with separate buses.
60   - - xilinx zynq qspi controller has implemented this feature [1]
61   -
62   - +-------------+ CS +---------------+
63   - | |---------------------->| |
64   - | | I0[3:0] | Upper Flash |
65   - | |<=====================>| memory |
66   - | | CLK | (SPI/QSPI) |
67   - | |---------------------->| |
68   - | Controller | CS +---------------+
69   - | SPI/QSPI |---------------------->| |
70   - | | I0[3:0] | Lower Flash |
71   - | |<=====================>| memory |
72   - | | CLK | (SPI/QSPI) |
73   - | |---------------------->| |
74   - +-------------+ +---------------+
75   -
76   - - two memory flash devices should has same hw part attributes (like size,
77   - vendor..etc)
78   - - Configurations:
79   - Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
80   - - Operation:
81   - Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
82   - and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
83   -
84   -Note: Technically there is only one CS line from the controller, but
85   -zynq qspi controller has an internal hw logic to enable additional CS
86   -when controller is configured for dual memories.
87   -
88   -[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
89   -
90   ---
91   -Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
92   -05-01-2014.
include/configs/socfpga_stratix10_socdk.h
Diff comments   View file @ 75b2ec2
... ... @@ -57,7 +57,6 @@
57 57 */
58 58 #ifdef CONFIG_CADENCE_QSPI
59 59 /* Enable it if you want to use dual-stacked mode */
60   -#undef CONFIG_SF_DUAL_FLASH
61 60 /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
62 61  
63 62 /* Flash device info */