MPC512x: factor out common code

Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>

MPC512x: factor out common code
Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Wolfgang Denk
1 parent 0549353a6b
Showing 6 changed files with 191 additions and 335 deletions Side-by-side Diff
board/davedenx/aria/aria.c
board/esd/mecp5123/mecp5123.c
board/freescale/mpc5121ads/mpc5121ads.c
cpu/mpc512x/Makefile
cpu/mpc512x/fixed_sdram.c
include/asm-ppc/mpc512x.h
@@ -27,6 +27,7 @@
 #include <command.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/mpc512x.h>
 #include <fdt_support.h>
 #ifdef CONFIG_MISC_INIT_R
 #include <i2c.h>
@@ -34,9 +35,6 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
-extern int mpc5121_diu_init(void);
-extern void ide_set_reset(int idereset);
-
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
 			 CLOCK_SCCR1_LPC_EN |				\
  
@@ -53,14 +51,9 @@
 			 CLOCK_SCCR2_DIU_EN |		\
 			 CLOCK_SCCR2_I2C_EN)
  
-#define CSAW_START(start)	((start) & 0xFFFF0000)
-#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
-
-long int fixed_sdram(void);
-
 int board_early_init_f(void)
 {
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 spridr;
  
 	/*
  
@@ -71,16 +64,9 @@
 		CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
 	);
 	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+	sync_law(&im->sysconf.lpcs2aw);
  
 	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	in_be32(&im->sysconf.lpcs2aw);
-	__asm__ __volatile__ ("isync");
-
-	/*
 	 * Initialize Local Window for the On Board SRAM access
 	 */
 	out_be32(&im->sysconf.lpcs6aw,
  
@@ -88,16 +74,9 @@
 		CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
 	);
 	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
+	sync_law(&im->sysconf.lpcs6aw);
  
 	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	in_be32(&im->sysconf.lpcs6aw);
-	__asm__ __volatile__ ("isync");
-
-	/*
 	 * Configure Flash Speed
 	 */
 	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
@@ -124,100 +103,6 @@
 	return fixed_sdram();
 }
  
-/*
- * fixed sdram init:
- * The board doesn't use memory modules that have serial presence
- * detect or similar mechanism for discovery of the DRAM settings
- */
-long int fixed_sdram (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-	u32 i;
-
-	/* Initialize IO Control */
-	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
-
-	/* Initialize DDR Local Window */
-	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
-	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
-
-	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	in_be32(&im->sysconf.ddrlaw.ar);
-	__asm__ __volatile__ ("isync");
-
-	/* Enable DDR */
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
-
-	/* Initialize DDR Priority Manager */
-	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
-	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
-	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
-	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
-	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
-	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
-	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
-	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
-	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
-	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
-	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
-	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
-	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
-	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
-	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
-	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
-	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
-	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
-	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
-	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
-	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
-	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
-	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
-
-	/* Initialize MDDRC */
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
-	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
-	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
-	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
-
-	/* Initialize DDR */
-	for (i = 0; i < 10; i++)
-		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-
-	/* Start MDDRC */
-	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
-
-	return msize;
-}
-
 int misc_init_r(void)
 {
 	u32 tmp;
@@ -294,7 +179,6 @@
 		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
 	},
 };
-
  
 int checkboard (void)
 {
@@ -28,6 +28,7 @@
 #include <command.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/mpc512x.h>
 #include <fdt_support.h>
  
 DECLARE_GLOBAL_DATA_PTR;
@@ -46,9 +47,6 @@
 #define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
 			 CLOCK_SCCR2_I2C_EN)
  
-#define CSAW_START(start)	((start) & 0xFFFF0000)
-#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
-
 int eeprom_write_enable(unsigned dev_addr, int state)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  
@@ -61,20 +59,9 @@
 	else
 		clrbits_be32(&im->gpio.gpdat, 0x00100000);
  
-return 0;
+	return 0;
 }
  
-/*
- * According to MPC5121e RM, configuring local access windows should
- * be followed by a dummy read of the config register that was
- * modified last and an isync.
- */
-static inline void sync_law(volatile void *addr)
-{
-	in_be32(addr);
-	__asm__ __volatile__ ("isync");
-}
-
 int board_early_init_f(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
@@ -144,93 +131,6 @@
 	setbits_be32(&im->gpio.gpdat, 0x00100000);
  
 	return 0;
-}
-
-/*
- * fixed sdram init:
- * The board doesn't use memory modules that have serial presence
- * detect or similar mechanism for discovery of the DRAM settings
- */
-long int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-	u32 i;
-
-	/* Initialize IO Control */
-	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
-
-	/* Initialize DDR Local Window */
-	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
-	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
-	sync_law(&im->sysconf.ddrlaw.ar);
-
-	/* Enable DDR */
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
-
-	/* Initialize DDR Priority Manager */
-	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
-	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
-	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
-	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
-	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
-	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
-	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
-	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
-	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
-	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
-	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
-	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
-	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
-	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
-	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
-	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
-	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
-	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
-	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
-	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
-	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
-	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
-	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
-
-	/* Initialize MDDRC */
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
-	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
-	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
-	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
-
-	/* Initialize DDR */
-	for (i = 0; i < 10; i++)
-		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-
-	/* Start MDDRC */
-	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
-
-	return msize;
 }
  
 phys_size_t initdram(int board_type)
@@ -26,6 +26,7 @@
 #include <command.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/mpc512x.h>
 #include <fdt_support.h>
 #ifdef CONFIG_MISC_INIT_R
 #include <i2c.h>
@@ -36,9 +37,6 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
-extern int mpc5121_diu_init(void);
-extern void ide_set_reset(int idereset);
-
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
 			 CLOCK_SCCR1_DDR_EN |				\
@@ -56,10 +54,6 @@
 			 CLOCK_SCCR2_MEM_EN |		\
 			 CLOCK_SCCR2_SPDIF_EN)
  
-#define CSAW_START(start)	((start) & 0xFFFF0000)
-#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
-
-long int fixed_sdram(void);
 void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
  
 /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
  
@@ -84,10 +78,10 @@
 	out_8(csreg, v);
 }
  
-int board_early_init_f (void)
+int board_early_init_f(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 lpcaw, spridr;
+	u32 spridr;
  
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
  
@@ -98,16 +92,9 @@
 		CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
 	);
 	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+	sync_law(&im->sysconf.lpcs2aw);
  
 	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	lpcaw = in_be32(&im->sysconf.lpcs6aw);
-	__asm__ __volatile__ ("isync");
-
-	/*
 	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
 	 *
 	 * Without this the flash identification routine fails, as it needs to issue
  
@@ -146,104 +133,11 @@
 	return 0;
 }
  
-phys_size_t initdram (int board_type)
+phys_size_t initdram(int board_type)
 {
 	u32 msize = 0;
  
-	msize = fixed_sdram ();
-
-	return msize;
-}
-
-/*
- * fixed sdram init -- the board doesn't use memory modules that have serial presence
- * detect or similar mechanism for discovery of the DRAM settings
- */
-long int fixed_sdram (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2 (msize);
-	u32 i;
-
-	/* Initialize IO Control */
-	out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
-
-	/* Initialize DDR Local Window */
-	out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
-	out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
-
-	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	in_be32(&im->sysconf.ddrlaw.ar);
-	__asm__ __volatile__ ("isync");
-
-	/* Enable DDR */
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
-
-	/* Initialize DDR Priority Manager */
-	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
-	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
-	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
-	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
-	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
-	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
-	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
-	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
-	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
-	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
-	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
-	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
-	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
-	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
-	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
-	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
-	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
-	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
-	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
-	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
-	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
-	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
-	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
-
-	/* Initialize MDDRC */
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
-	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
-	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
-	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
-
-	/* Initialize DDR */
-	for (i = 0; i < 10; i++)
-		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
-	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
-
-	/* Start MDDRC */
-	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
-	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
+	msize = fixed_sdram();
  
 	return msize;
 }
@@ -27,7 +27,15 @@
 LIB	= $(obj)lib$(CPU).a
  
 START	= start.o
-COBJS-y	:= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
+COBJS-y	:= cpu.o
+COBJS-y	+= traps.o
+COBJS-y += cpu_init.o
+COBJS-y += fixed_sdram.o
+COBJS-y += i2c.o
+COBJS-y += interrupts.o
+COBJS-y += iopin.o
+COBJS-y += serial.o
+COBJS-y += speed.o
 COBJS-${CONFIG_FSL_DIU_FB} += diu.o
 COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
 COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mpc512x.h>
+
+/*
+ * fixed sdram init:
+ * The board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+	u32 i;
+
+	/* Initialize IO Control */
+	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+
+	/* Initialize DDR Local Window */
+	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
+	/* Enable DDR */
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
+
+	/* Initialize DDR Priority Manager */
+	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
+
+	/* Initialize MDDRC */
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
+	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
+	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
+
+	/* Initialize DDR */
+	for (i = 0; i < 10; i++)
+		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	/* Start MDDRC */
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
+
+	return msize;
+}
+/*
+ * include/asm-ppc/mpc512x.h
+ *
+ * Prototypes, etc. for the Freescale MPC512x embedded cpu chips
+ *
+ * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASMPPC_MPC512X_H
+#define __ASMPPC_MPC512X_H
+
+/*
+ * macros for manipulating CSx_START/STOP
+ */
+#define CSAW_START(start)	((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
+
+/*
+ * Inlines
+ */
+
+/*
+ * According to MPC5121e RM, configuring local access windows should
+ * be followed by a dummy read of the config register that was
+ * modified last and an isync.
+ */
+static inline void sync_law(volatile void *addr)
+{
+	in_be32(addr);
+	__asm__ __volatile__ ("isync");
+}
+
+/*
+ * Prototypes
+ */
+extern long int fixed_sdram(void);
+extern int mpc5121_diu_init(void);
+extern void ide_set_reset(int idereset);
+
+#endif /* __ASMPPC_MPC512X_H */
...	...	@@ -27,6 +27,7 @@
27	27	#include <command.h>
28	28	#include <asm/io.h>
29	29	#include <asm/processor.h>
	30	+#include <asm/mpc512x.h>
30	31	#include <fdt_support.h>
31	32	#ifdef CONFIG_MISC_INIT_R
32	33	#include <i2c.h>
...	...	@@ -34,9 +35,6 @@
34	35
35	36	DECLARE_GLOBAL_DATA_PTR;
36	37
37		-extern int mpc5121_diu_init(void);
38		-extern void ide_set_reset(int idereset);
39		-
40	38	/* Clocks in use */
41	39	#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN \| \
42	40	CLOCK_SCCR1_LPC_EN \| \
43	41
...	...	@@ -53,14 +51,9 @@
53	51	CLOCK_SCCR2_DIU_EN \| \
54	52	CLOCK_SCCR2_I2C_EN)
55	53
56		-#define CSAW_START(start) ((start) & 0xFFFF0000)
57		-#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
58		-
59		-long int fixed_sdram(void);
60		-
61	54	int board_early_init_f(void)
62	55	{
63		- volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
	56	+ volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
64	57	u32 spridr;
65	58
66	59	/*
67	60
...	...	@@ -71,16 +64,9 @@
71	64	CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
72	65	);
73	66	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
	67	+ sync_law(&im->sysconf.lpcs2aw);
74	68
75	69	/*
76		- * According to MPC5121e RM, configuring local access windows should
77		- * be followed by a dummy read of the config register that was
78		- * modified last and an isync
79		- */
80		- in_be32(&im->sysconf.lpcs2aw);
81		- __asm__ __volatile__ ("isync");
82		-
83		- /*
84	70	* Initialize Local Window for the On Board SRAM access
85	71	*/
86	72	out_be32(&im->sysconf.lpcs6aw,
87	73
...	...	@@ -88,16 +74,9 @@
88	74	CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
89	75	);
90	76	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
	77	+ sync_law(&im->sysconf.lpcs6aw);
91	78
92	79	/*
93		- * According to MPC5121e RM, configuring local access windows should
94		- * be followed by a dummy read of the config register that was
95		- * modified last and an isync
96		- */
97		- in_be32(&im->sysconf.lpcs6aw);
98		- __asm__ __volatile__ ("isync");
99		-
100		- /*
101	80	* Configure Flash Speed
102	81	*/
103	82	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
...	...	@@ -124,100 +103,6 @@
124	103	return fixed_sdram();
125	104	}
126	105
127		-/*
128		- * fixed sdram init:
129		- * The board doesn't use memory modules that have serial presence
130		- * detect or similar mechanism for discovery of the DRAM settings
131		- */
132		-long int fixed_sdram (void)
133		-{
134		- volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
135		- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
136		- u32 msize_log2 = __ilog2(msize);
137		- u32 i;
138		-
139		- /* Initialize IO Control */
140		- out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
141		-
142		- /* Initialize DDR Local Window */
143		- out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
144		- out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
145		-
146		- /*
147		- * According to MPC5121e RM, configuring local access windows should
148		- * be followed by a dummy read of the config register that was
149		- * modified last and an isync
150		- */
151		- in_be32(&im->sysconf.ddrlaw.ar);
152		- __asm__ __volatile__ ("isync");
153		-
154		- /* Enable DDR */
155		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
156		-
157		- /* Initialize DDR Priority Manager */
158		- out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
159		- out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
160		- out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
161		- out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
162		- out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
163		- out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
164		- out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
165		- out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
166		- out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
167		- out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
168		- out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
169		- out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
170		- out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
171		- out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
172		- out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
173		- out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
174		- out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
175		- out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
176		- out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
177		- out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
178		- out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
179		- out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
180		- out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
181		-
182		- /* Initialize MDDRC */
183		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
184		- out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
185		- out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
186		- out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
187		-
188		- /* Initialize DDR */
189		- for (i = 0; i < 10; i++)
190		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
191		-
192		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
193		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
194		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
195		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
196		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
197		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
198		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
199		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
200		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
201		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
202		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
203		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
204		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
205		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
206		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
207		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
208		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
209		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
210		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
211		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
212		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
213		-
214		- /* Start MDDRC */
215		- out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
216		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
217		-
218		- return msize;
219		-}
220		-
221	106	int misc_init_r(void)
222	107	{
223	108	u32 tmp;
...	...	@@ -294,7 +179,6 @@
294	179	IO_PIN_PUE(1) \| IO_PIN_ST(1) \| IO_PIN_DS(3)
295	180	},
296	181	};
297		-
298	182
299	183	int checkboard (void)
300	184	{
...	...	@@ -28,6 +28,7 @@
28	28	#include <command.h>
29	29	#include <asm/io.h>
30	30	#include <asm/processor.h>
	31	+#include <asm/mpc512x.h>
31	32	#include <fdt_support.h>
32	33
33	34	DECLARE_GLOBAL_DATA_PTR;
...	...	@@ -46,9 +47,6 @@
46	47	#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN \| \
47	48	CLOCK_SCCR2_I2C_EN)
48	49
49		-#define CSAW_START(start) ((start) & 0xFFFF0000)
50		-#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
51		-
52	50	int eeprom_write_enable(unsigned dev_addr, int state)
53	51	{
54	52	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
55	53
...	...	@@ -61,20 +59,9 @@
61	59	else
62	60	clrbits_be32(&im->gpio.gpdat, 0x00100000);
63	61
64		-return 0;
	62	+ return 0;
65	63	}
66	64
67		-/*
68		- * According to MPC5121e RM, configuring local access windows should
69		- * be followed by a dummy read of the config register that was
70		- * modified last and an isync.
71		- */
72		-static inline void sync_law(volatile void *addr)
73		-{
74		- in_be32(addr);
75		- __asm__ __volatile__ ("isync");
76		-}
77		-
78	65	int board_early_init_f(void)
79	66	{
80	67	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
...	...	@@ -144,93 +131,6 @@
144	131	setbits_be32(&im->gpio.gpdat, 0x00100000);
145	132
146	133	return 0;
147		-}
148		-
149		-/*
150		- * fixed sdram init:
151		- * The board doesn't use memory modules that have serial presence
152		- * detect or similar mechanism for discovery of the DRAM settings
153		- */
154		-long int fixed_sdram(void)
155		-{
156		- volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
157		- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
158		- u32 msize_log2 = __ilog2(msize);
159		- u32 i;
160		-
161		- /* Initialize IO Control */
162		- out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
163		-
164		- /* Initialize DDR Local Window */
165		- out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
166		- out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
167		- sync_law(&im->sysconf.ddrlaw.ar);
168		-
169		- /* Enable DDR */
170		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
171		-
172		- /* Initialize DDR Priority Manager */
173		- out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
174		- out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
175		- out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
176		- out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
177		- out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
178		- out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
179		- out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
180		- out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
181		- out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
182		- out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
183		- out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
184		- out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
185		- out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
186		- out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
187		- out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
188		- out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
189		- out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
190		- out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
191		- out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
192		- out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
193		- out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
194		- out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
195		- out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
196		-
197		- /* Initialize MDDRC */
198		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
199		- out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
200		- out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
201		- out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
202		-
203		- /* Initialize DDR */
204		- for (i = 0; i < 10; i++)
205		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
206		-
207		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
208		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
209		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
210		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
211		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
212		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
213		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
214		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
215		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
216		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
217		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
218		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
219		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
220		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
221		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
222		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
223		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
224		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
225		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
226		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
227		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
228		-
229		- /* Start MDDRC */
230		- out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
231		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
232		-
233		- return msize;
234	134	}
235	135
236	136	phys_size_t initdram(int board_type)
...	...	@@ -26,6 +26,7 @@
26	26	#include <command.h>
27	27	#include <asm/io.h>
28	28	#include <asm/processor.h>
	29	+#include <asm/mpc512x.h>
29	30	#include <fdt_support.h>
30	31	#ifdef CONFIG_MISC_INIT_R
31	32	#include <i2c.h>
...	...	@@ -36,9 +37,6 @@
36	37
37	38	DECLARE_GLOBAL_DATA_PTR;
38	39
39		-extern int mpc5121_diu_init(void);
40		-extern void ide_set_reset(int idereset);
41		-
42	40	/* Clocks in use */
43	41	#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN \| \
44	42	CLOCK_SCCR1_DDR_EN \| \
...	...	@@ -56,10 +54,6 @@
56	54	CLOCK_SCCR2_MEM_EN \| \
57	55	CLOCK_SCCR2_SPDIF_EN)
58	56
59		-#define CSAW_START(start) ((start) & 0xFFFF0000)
60		-#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
61		-
62		-long int fixed_sdram(void);
63	57	void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
64	58
65	59	/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
66	60
...	...	@@ -84,10 +78,10 @@
84	78	out_8(csreg, v);
85	79	}
86	80
87		-int board_early_init_f (void)
	81	+int board_early_init_f(void)
88	82	{
89	83	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
90		- u32 lpcaw, spridr;
	84	+ u32 spridr;
91	85
92	86	/*
93	87	* Initialize Local Window for the CPLD registers access (CS2 selects
94	88
...	...	@@ -98,16 +92,9 @@
98	92	CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
99	93	);
100	94	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
	95	+ sync_law(&im->sysconf.lpcs2aw);
101	96
102	97	/*
103		- * According to MPC5121e RM, configuring local access windows should
104		- * be followed by a dummy read of the config register that was
105		- * modified last and an isync
106		- */
107		- lpcaw = in_be32(&im->sysconf.lpcs6aw);
108		- __asm__ __volatile__ ("isync");
109		-
110		- /*
111	98	* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
112	99	*
113	100	* Without this the flash identification routine fails, as it needs to issue
114	101
...	...	@@ -146,104 +133,11 @@
146	133	return 0;
147	134	}
148	135
149		-phys_size_t initdram (int board_type)
	136	+phys_size_t initdram(int board_type)
150	137	{
151	138	u32 msize = 0;
152	139
153		- msize = fixed_sdram ();
154		-
155		- return msize;
156		-}
157		-
158		-/*
159		- * fixed sdram init -- the board doesn't use memory modules that have serial presence
160		- * detect or similar mechanism for discovery of the DRAM settings
161		- */
162		-long int fixed_sdram (void)
163		-{
164		- volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
165		- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
166		- u32 msize_log2 = __ilog2 (msize);
167		- u32 i;
168		-
169		- /* Initialize IO Control */
170		- out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
171		-
172		- /* Initialize DDR Local Window */
173		- out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
174		- out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
175		-
176		- /*
177		- * According to MPC5121e RM, configuring local access windows should
178		- * be followed by a dummy read of the config register that was
179		- * modified last and an isync
180		- */
181		- in_be32(&im->sysconf.ddrlaw.ar);
182		- __asm__ __volatile__ ("isync");
183		-
184		- /* Enable DDR */
185		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
186		-
187		- /* Initialize DDR Priority Manager */
188		- out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
189		- out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
190		- out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
191		- out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
192		- out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
193		- out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
194		- out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
195		- out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
196		- out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
197		- out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
198		- out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
199		- out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
200		- out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
201		- out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
202		- out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
203		- out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
204		- out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
205		- out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
206		- out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
207		- out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
208		- out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
209		- out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
210		- out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
211		-
212		- /* Initialize MDDRC */
213		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
214		- out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
215		- out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
216		- out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
217		-
218		- /* Initialize DDR */
219		- for (i = 0; i < 10; i++)
220		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
221		-
222		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
223		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
224		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
225		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
226		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
227		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
228		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
229		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
230		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
231		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
232		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
233		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
234		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
235		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
236		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
237		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
238		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
239		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
240		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
241		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
242		- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
243		-
244		- /* Start MDDRC */
245		- out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
246		- out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
	140	+ msize = fixed_sdram();
247	141
248	142	return msize;
249	143	}
...	...	@@ -27,7 +27,15 @@
27	27	LIB = $(obj)lib$(CPU).a
28	28
29	29	START = start.o
30		-COBJS-y := traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
	30	+COBJS-y := cpu.o
	31	+COBJS-y += traps.o
	32	+COBJS-y += cpu_init.o
	33	+COBJS-y += fixed_sdram.o
	34	+COBJS-y += i2c.o
	35	+COBJS-y += interrupts.o
	36	+COBJS-y += iopin.o
	37	+COBJS-y += serial.o
	38	+COBJS-y += speed.o
31	39	COBJS-${CONFIG_FSL_DIU_FB} += diu.o
32	40	COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
33	41	COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
	1	+/*
	2	+ * (C) Copyright 2007-2009 DENX Software Engineering
	3	+ *
	4	+ * See file CREDITS for list of people who contributed to this
	5	+ * project.
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or
	8	+ * modify it under the terms of the GNU General Public License as
	9	+ * published by the Free Software Foundation; either version 2 of
	10	+ * the License, or (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+ * MA 02111-1307 USA
	21	+ *
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <asm/io.h>
	26	+#include <asm/mpc512x.h>
	27	+
	28	+/*
	29	+ * fixed sdram init:
	30	+ * The board doesn't use memory modules that have serial presence
	31	+ * detect or similar mechanism for discovery of the DRAM settings
	32	+ */
	33	+long int fixed_sdram(void)
	34	+{
	35	+ volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
	36	+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
	37	+ u32 msize_log2 = __ilog2(msize);
	38	+ u32 i;
	39	+
	40	+ /* Initialize IO Control */
	41	+ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
	42	+
	43	+ /* Initialize DDR Local Window */
	44	+ out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
	45	+ out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
	46	+ sync_law(&im->sysconf.ddrlaw.ar);
	47	+
	48	+ /* Enable DDR */
	49	+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
	50	+
	51	+ /* Initialize DDR Priority Manager */
	52	+ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
	53	+ out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
	54	+ out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
	55	+ out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
	56	+ out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
	57	+ out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
	58	+ out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
	59	+ out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
	60	+ out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
	61	+ out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
	62	+ out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
	63	+ out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
	64	+ out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
	65	+ out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
	66	+ out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
	67	+ out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
	68	+ out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
	69	+ out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
	70	+ out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
	71	+ out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
	72	+ out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
	73	+ out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
	74	+ out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
	75	+
	76	+ /* Initialize MDDRC */
	77	+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
	78	+ out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
	79	+ out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
	80	+ out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
	81	+
	82	+ /* Initialize DDR */
	83	+ for (i = 0; i < 10; i++)
	84	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	85	+
	86	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
	87	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	88	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
	89	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	90	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
	91	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	92	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
	93	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	94	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
	95	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	96	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
	97	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
	98	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
	99	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
	100	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
	101	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
	102	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
	103	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
	104	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
	105	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
	106	+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
	107	+
	108	+ /* Start MDDRC */
	109	+ out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
	110	+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
	111	+
	112	+ return msize;
	113	+}
	1	+/*
	2	+ * include/asm-ppc/mpc512x.h
	3	+ *
	4	+ * Prototypes, etc. for the Freescale MPC512x embedded cpu chips
	5	+ *
	6	+ * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+#ifndef __ASMPPC_MPC512X_H
	27	+#define __ASMPPC_MPC512X_H
	28	+
	29	+/*
	30	+ * macros for manipulating CSx_START/STOP
	31	+ */
	32	+#define CSAW_START(start) ((start) & 0xFFFF0000)
	33	+#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
	34	+
	35	+/*
	36	+ * Inlines
	37	+ */
	38	+
	39	+/*
	40	+ * According to MPC5121e RM, configuring local access windows should
	41	+ * be followed by a dummy read of the config register that was
	42	+ * modified last and an isync.
	43	+ */
	44	+static inline void sync_law(volatile void *addr)
	45	+{
	46	+ in_be32(addr);
	47	+ __asm__ __volatile__ ("isync");
	48	+}
	49	+
	50	+/*
	51	+ * Prototypes
	52	+ */
	53	+extern long int fixed_sdram(void);
	54	+extern int mpc5121_diu_init(void);
	55	+extern void ide_set_reset(int idereset);
	56	+
	57	+#endif /* __ASMPPC_MPC512X_H */