board/bsc9131rdb: Add DSP side tlb and laws

BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>

board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Priyanka Jain · Andy Fleming
1 parent 087cf44fcd
Showing 6 changed files with 29 additions and 0 deletions Side-by-side Diff
README
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_law.h
board/freescale/bsc9131rdb/law.c
board/freescale/bsc9131rdb/tlb.c
include/configs/BSC9131RDB.h
@@ -422,6 +422,13 @@
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
  
+		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+		This value denotes start offset of M2 memory
+		which is directly connected to the DSP core.
+
+		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+		This value denotes start offset of DSP CCSR space.
+
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
  
@@ -494,6 +494,8 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -82,11 +82,16 @@
 #ifndef CONFIG_MPC8641
 	LAW_TRGT_IF_PCIE_1 = 0x02,
 #endif
+#if defined(CONFIG_BSC9131)
+	LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
 	LAW_TRGT_IF_PCIE_3 = 0x03,
 #endif
+#endif
 	LAW_TRGT_IF_LBC = 0x04,
 	LAW_TRGT_IF_CCSR = 0x08,
+	LAW_TRGT_IF_DSP_CCSR = 0x09,
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
 	LAW_TRGT_IF_RIO_2 = 0x0d,
@@ -26,6 +26,10 @@
  
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+		LAW_TRGT_IF_DSP_CCSR),
+	SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
+		LAW_TRGT_IF_OCN_DSP),
 };
  
 int num_law_entries = ARRAY_SIZE(law_table);
@@ -52,6 +52,12 @@
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
  
+	/* CCSRBAR (DSP) */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+		      CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1M, 1),
+
 #if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -153,16 +153,21 @@
  
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
 							/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
  
 /*
  * Memory map
  *
  * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
  * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
+ * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
  * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
  * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
  * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
  * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
+ * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
  * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
  * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
  *
...	...	@@ -422,6 +422,13 @@
422	422	This is the value to write into CCSR offset 0x18600
423	423	according to the A004510 workaround.
424	424
	425	+ CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
	426	+ This value denotes start offset of M2 memory
	427	+ which is directly connected to the DSP core.
	428	+
	429	+ CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
	430	+ This value denotes start offset of DSP CCSR space.
	431	+
425	432	- Generic CPU options:
426	433	CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
427	434
...	...	@@ -494,6 +494,8 @@
494	494	#define CONFIG_TSECV2
495	495	#define CONFIG_SYS_FSL_SEC_COMPAT 4
496	496	#define CONFIG_NUM_DDR_CONTROLLERS 1
	497	+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
	498	+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
497	499	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
498	500	#define CONFIG_NAND_FSL_IFC
499	501	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
...	...	@@ -82,11 +82,16 @@
82	82	#ifndef CONFIG_MPC8641
83	83	LAW_TRGT_IF_PCIE_1 = 0x02,
84	84	#endif
	85	+#if defined(CONFIG_BSC9131)
	86	+ LAW_TRGT_IF_OCN_DSP = 0x03,
	87	+#else
85	88	#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
86	89	LAW_TRGT_IF_PCIE_3 = 0x03,
87	90	#endif
	91	+#endif
88	92	LAW_TRGT_IF_LBC = 0x04,
89	93	LAW_TRGT_IF_CCSR = 0x08,
	94	+ LAW_TRGT_IF_DSP_CCSR = 0x09,
90	95	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
91	96	LAW_TRGT_IF_RIO = 0x0c,
92	97	LAW_TRGT_IF_RIO_2 = 0x0d,
...	...	@@ -26,6 +26,10 @@
26	26
27	27	struct law_entry law_table[] = {
28	28	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
	29	+ SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
	30	+ LAW_TRGT_IF_DSP_CCSR),
	31	+ SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
	32	+ LAW_TRGT_IF_OCN_DSP),
29	33	};
30	34
31	35	int num_law_entries = ARRAY_SIZE(law_table);
...	...	@@ -52,6 +52,12 @@
52	52	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
53	53	0, 1, BOOKE_PAGESZ_1M, 1),
54	54
	55	+ /* CCSRBAR (DSP) */
	56	+ SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
	57	+ CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
	58	+ MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	59	+ 0, 2, BOOKE_PAGESZ_1M, 1),
	60	+
55	61	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_SPL)
56	62	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
57	63	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
...	...	@@ -153,16 +153,21 @@
153	153
154	154	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
155	155	/* CONFIG_SYS_IMMR */
	156	+/* DSP CCSRBAR */
	157	+#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
	158	+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
156	159
157	160	/*
158	161	* Memory map
159	162	*
160	163	* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
161	164	* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
	165	+ * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
162	166	* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
163	167	* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
164	168	* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
165	169	* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
	170	+ * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
166	171	* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
167	172	* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
168	173	*