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Commit 7677d65f6522b1a911ac3a24225ec29709106010

Authored by Bob Liu
Committed by sonic
1 parent ee8259623e
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

blackfin: bf60x: support big cplb page 

BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them.
So that bf609-ezkit can use it's 128M memory.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>

Showing 2 changed files with 44 additions and 6 deletions Side-by-side Diff

arch/blackfin/include/asm/cplb.h
Diff comments   View file @ 7677d65
... ... @@ -46,8 +46,13 @@
46 46 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
47 47  
48 48 /* Data Attibutes*/
49   -
50   -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
  49 +#if defined(__ADSPBF60x__)
  50 +#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
  51 + CPLB_USER_RD | CPLB_VALID)
  52 +#else
  53 +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
  54 + CPLB_USER_RD | CPLB_VALID)
  55 +#endif
51 56 #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
52 57 #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
53 58 #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
54 59  
... ... @@ -59,14 +64,32 @@
59 64 #endif
60 65  
61 66 #ifdef CONFIG_DCACHE_WB /*Write Back Policy */
62   -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  67 +#if defined(__ADSPBF60x__)
  68 +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
  69 + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
  70 + CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  71 +#else
  72 +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
  73 + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
  74 + CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  75 +#endif
63 76 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
64 77 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
65 78 #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
66 79 #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
67 80  
68 81 #else /*Write Through */
69   -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  82 +#if defined(__ADSPBF60x__)
  83 +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
  84 + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
  85 + CPLB_USER_WR | CPLB_VALID | \
  86 + ANOMALY_05000158_WORKAROUND)
  87 +#else
  88 +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
  89 + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
  90 + CPLB_USER_WR | CPLB_VALID | \
  91 + ANOMALY_05000158_WORKAROUND)
  92 +#endif
70 93 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
71 94 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
72 95 #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
arch/blackfin/lib/board.c
Diff comments   View file @ 7677d65
... ... @@ -96,6 +96,13 @@
96 96  
97 97 #define CPLB_PAGE_SIZE (4 * 1024 * 1024)
98 98 #define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
  99 +#if defined(__ADSPBF60x__)
  100 +#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
  101 +#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
  102 +#else
  103 +#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
  104 +#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
  105 +#endif
99 106 void init_cplbtables(void)
100 107 {
101 108 volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
... ... @@ -127,6 +134,11 @@
127 134 icplb_add(0xFFA00000, L1_IMEMORY);
128 135 dcplb_add(0xFF800000, L1_DMEMORY);
129 136 ++i;
  137 +#if defined(__ADSPBF60x__)
  138 + icplb_add(0x0, 0x0);
  139 + dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU);
  140 + ++i;
  141 +#endif
130 142  
131 143 if (CONFIG_MEM_SIZE) {
132 144 uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
133 145  
... ... @@ -150,9 +162,11 @@
150 162 }
151 163 }
152 164  
  165 +#ifndef __ADSPBF60x__
153 166 icplb_add(0x20000000, SDRAM_INON_CHBL);
154 167 dcplb_add(0x20000000, SDRAM_EBIU);
155 168 ++i;
  169 +#endif
156 170  
157 171 /* Add entries for the rest of external RAM up to the bootrom */
158 172 extern_memory = 0;
159 173  
... ... @@ -167,10 +181,11 @@
167 181 ++i;
168 182 #endif
169 183  
170   - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) {
  184 + while (i < 16 && extern_memory <
  185 + (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
171 186 icplb_add(extern_memory, SDRAM_IGENERIC);
172 187 dcplb_add(extern_memory, SDRAM_DGENERIC);
173   - extern_memory += CPLB_PAGE_SIZE;
  188 + extern_memory += CPLB_EX_PAGE_SIZE;
174 189 ++i;
175 190 }
176 191 while (i < 16) {