Commit 76957cb3d621bf664311908e5962e151c633c285
Committed by
Wolfgang Denk
Wolfgang Denk
1 parent
118978c8eb
Exists in
master
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54 other branches
ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But currently 4k/2k is configured. This patch fixes this issue. Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
Showing 2 changed files with 24 additions and 8 deletions Side-by-side Diff
cpu/ppc4xx/4xx_enet.c
| ... | ... | @@ -975,9 +975,10 @@ |
| 975 | 975 | /* set transmit enable & receive enable */ |
| 976 | 976 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
| 977 | 977 | |
| 978 | - /* set receive fifo to 4k and tx fifo to 2k */ | |
| 979 | 978 | mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); |
| 980 | - mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; | |
| 979 | + | |
| 980 | + /* set rx-/tx-fifo size */ | |
| 981 | + mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; | |
| 981 | 982 | |
| 982 | 983 | /* set speed */ |
| 983 | 984 | if (speed == _1000BASET) { |
include/ppc4xx_enet.h
| ... | ... | @@ -356,12 +356,14 @@ |
| 356 | 356 | #define EMAC_M1_IST (0x01000000) |
| 357 | 357 | #define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ |
| 358 | 358 | #define EMAC_M1_MF_100MBPS (0x00400000) |
| 359 | -#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ | |
| 360 | -#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ | |
| 361 | -#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ | |
| 359 | +#define EMAC_M1_RFS_MASK (0x00380000) | |
| 360 | +#define EMAC_M1_RFS_16K (0x00280000) | |
| 361 | +#define EMAC_M1_RFS_8K (0x00200000) | |
| 362 | +#define EMAC_M1_RFS_4K (0x00180000) | |
| 362 | 363 | #define EMAC_M1_RFS_2K (0x00100000) |
| 363 | 364 | #define EMAC_M1_RFS_1K (0x00080000) |
| 364 | -#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ | |
| 365 | +#define EMAC_M1_TX_FIFO_MASK (0x00070000) | |
| 366 | +#define EMAC_M1_TX_FIFO_16K (0x00050000) | |
| 365 | 367 | #define EMAC_M1_TX_FIFO_8K (0x00040000) |
| 366 | 368 | #define EMAC_M1_TX_FIFO_4K (0x00030000) |
| 367 | 369 | #define EMAC_M1_TX_FIFO_2K (0x00020000) |
| 368 | 370 | |
| 369 | 371 | |
| ... | ... | @@ -386,11 +388,15 @@ |
| 386 | 388 | #define EMAC_M1_IST 0x01000000 |
| 387 | 389 | #define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ |
| 388 | 390 | #define EMAC_M1_MF_100MBPS 0x00400000 |
| 389 | -#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ | |
| 391 | +#define EMAC_M1_RFS_MASK 0x00300000 | |
| 392 | +#define EMAC_M1_RFS_4K 0x00300000 | |
| 390 | 393 | #define EMAC_M1_RFS_2K 0x00200000 |
| 391 | 394 | #define EMAC_M1_RFS_1K 0x00100000 |
| 392 | -#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ | |
| 395 | +#define EMAC_M1_RFS_512 0x00000000 | |
| 396 | +#define EMAC_M1_TX_FIFO_MASK 0x000c0000 | |
| 397 | +#define EMAC_M1_TX_FIFO_2K 0x00080000 | |
| 393 | 398 | #define EMAC_M1_TX_FIFO_1K 0x00040000 |
| 399 | +#define EMAC_M1_TX_FIFO_512 0x00000000 | |
| 394 | 400 | #define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ |
| 395 | 401 | #define EMAC_M1_TR0_MULTI 0x00008000 |
| 396 | 402 | #define EMAC_M1_TR1_DEPEND 0x00004000 |
| ... | ... | @@ -399,6 +405,15 @@ |
| 399 | 405 | #define EMAC_M1_JUMBO_ENABLE 0x00001000 |
| 400 | 406 | #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ |
| 401 | 407 | #endif /* defined(CONFIG_440GX) */ |
| 408 | + | |
| 409 | +#define EMAC_MR1_FIFO_MASK (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK) | |
| 410 | +#if defined(CONFIG_405EZ) | |
| 411 | +/* 405EZ only supports 512 bytes fifos */ | |
| 412 | +#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512) | |
| 413 | +#else | |
| 414 | +/* Set receive fifo to 4k and tx fifo to 2k */ | |
| 415 | +#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K) | |
| 416 | +#endif | |
| 402 | 417 | |
| 403 | 418 | /* Transmit Mode Register 0 */ |
| 404 | 419 | #define EMAC_TXM0_GNP0 (0x80000000) |