Eric Lee / smarc-uboot

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Commit 76a14d23c1b33321a9aabf512f5979adeeb30ff4

Authored by Ye Li
1 parent 7595df6453
Exists in smarc-n7.1.2_2.0.0-ga and in 4 other branches smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m

MLK-14484-2 mx7ulp_arm2: Add 10x10 and 14x14 ARM2 codes 

Copy the mx7ulp ARM2 codes from v2016.03 as the base for using
OF_CONTROL and DM drivers.

The 14x14 ARM2 LPDDR3 script is v1.5:
- IMX7ULP1_LPDDR3_320MHz_512MB_32bit_V1.5.inc

The 10x10 ARM2 LPDDR2 script is v1.1:
- IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.1.inc

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 10 changed files with 1232 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx7ulp/Kconfig
Diff comments   View file @ 76a14d2
... ... @@ -16,12 +16,21 @@
16 16 prompt "MX7ULP board select"
17 17 optional
18 18  
  19 +config TARGET_MX7ULP_10X10_ARM2
  20 + bool "Support mx7ulp 10x10 validation board"
  21 + select MX7ULP
  22 +
  23 +config TARGET_MX7ULP_14X14_ARM2
  24 + bool "Support mx7ulp 14x14 validation board"
  25 + select MX7ULP
  26 +
19 27 config TARGET_MX7ULP_EVK
20 28 bool "Support mx7ulp EVK board"
21 29 select MX7ULP
22 30  
23 31 endchoice
24 32  
  33 +source "board/freescale/mx7ulp_arm2/Kconfig"
25 34 source "board/freescale/mx7ulp_evk/Kconfig"
26 35  
27 36 endif
board/freescale/mx7ulp_arm2/Kconfig
Diff comments   View file @ 76a14d2
  1 +if TARGET_MX7ULP_10X10_ARM2 || TARGET_MX7ULP_14X14_ARM2
  2 +
  3 +config SYS_BOARD
  4 + default "mx7ulp_arm2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx7ulp_arm2"
  11 +
  12 +endif
board/freescale/mx7ulp_arm2/Makefile
Diff comments   View file @ 76a14d2
  1 +# (C) Copyright 2016 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx7ulp_arm2.o
board/freescale/mx7ulp_arm2/imximage.cfg
Diff comments   View file @ 76a14d2
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +BOOT_FROM sd
  25 +
  26 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  27 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  28 +PLUGIN board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
  29 +#else
  30 +
  31 +#ifdef CONFIG_SECURE_BOOT
  32 +CSF CONFIG_CSF_SIZE
  33 +#endif
  34 +/*
  35 + * Device Configuration Data (DCD)
  36 + *
  37 + * Each entry must have the format:
  38 + * Addr-type Address Value
  39 + *
  40 + * where:
  41 + * Addr-type register length (1,2 or 4 bytes)
  42 + * Address absolute address of the register
  43 + * value value to be stored in the register
  44 + */
  45 +DATA 4 0x403f00e0 0x00000000
  46 +DATA 4 0x403e0040 0x01000020
  47 +DATA 4 0x403e050c 0x80808080
  48 +DATA 4 0x403e050c 0x8080801E
  49 +CHECK_BITS_SET 4 0x403e050c 0x00000040
  50 +DATA 4 0x403E0030 0x00000001
  51 +DATA 4 0x403e0040 0x11000020
  52 +DATA 4 0x403f00e0 0x42000000
  53 +
  54 +DATA 4 0x40B300AC 0x40000000
  55 +
  56 +DATA 4 0x40AD0128 0x00040000
  57 +DATA 4 0x40AD00F8 0x00000000
  58 +DATA 4 0x40AD00D8 0x00000180
  59 +DATA 4 0x40AD0108 0x00000180
  60 +DATA 4 0x40AD0104 0x00000180
  61 +DATA 4 0x40AD0124 0x00010000
  62 +DATA 4 0x40AD0080 0x0000018C
  63 +DATA 4 0x40AD0084 0x0000018C
  64 +DATA 4 0x40AD0088 0x0000018C
  65 +DATA 4 0x40AD008C 0x0000018C
  66 +
  67 +DATA 4 0x40AD0120 0x00010000
  68 +DATA 4 0x40AD010C 0x00000180
  69 +DATA 4 0x40AD0110 0x00000180
  70 +DATA 4 0x40AD0114 0x00000180
  71 +DATA 4 0x40AD0118 0x00000180
  72 +DATA 4 0x40AD0090 0x00000180
  73 +DATA 4 0x40AD0094 0x00000180
  74 +DATA 4 0x40AD0098 0x00000180
  75 +DATA 4 0x40AD009C 0x00000180
  76 +
  77 +DATA 4 0x40AD00E0 0x00040000
  78 +DATA 4 0x40AD00E4 0x00040000
  79 +
  80 +DATA 4 0x40AB001C 0x00008000
  81 +DATA 4 0x40AB0800 0xA1390003
  82 +DATA 4 0x40AB085C 0x0D3900A0
  83 +DATA 4 0x40AB0890 0x00400000
  84 +
  85 +DATA 4 0x40AB0848 0x39373939
  86 +DATA 4 0x40AB0850 0x2F313D36
  87 +DATA 4 0x40AB081C 0x33333333
  88 +DATA 4 0x40AB0820 0x33333333
  89 +DATA 4 0x40AB0824 0x33333333
  90 +DATA 4 0x40AB0828 0x33333333
  91 +
  92 +DATA 4 0x40AB08C0 0x24922492
  93 +DATA 4 0x40AB08B8 0x00000800
  94 +
  95 +DATA 4 0x40AB0004 0x00020052
  96 +DATA 4 0x40AB000C 0x424642F3
  97 +DATA 4 0x40AB0010 0x00100A22
  98 +DATA 4 0x40AB0038 0x00120556
  99 +DATA 4 0x40AB0014 0x00C700DA
  100 +DATA 4 0x40AB0018 0x00211718
  101 +DATA 4 0x40AB002C 0x0F9F26D2
  102 +DATA 4 0x40AB0030 0x009F0E10
  103 +DATA 4 0x40AB0040 0x0000004F
  104 +DATA 4 0x40AB0000 0x84190000
  105 +
  106 +DATA 4 0x40AB001C 0x00008010
  107 +DATA 4 0x40AB001C 0x003F8030
  108 +DATA 4 0x40AB001C 0xFF0A8030
  109 +DATA 4 0x40AB001C 0x04028030
  110 +DATA 4 0x40AB001C 0x83018030
  111 +DATA 4 0x40AB001C 0x01038030
  112 +
  113 +DATA 4 0x40AB083C 0x20000000
  114 +
  115 +DATA 4 0x40AB0020 0x00001800
  116 +DATA 4 0x40AB0800 0xA1310003
  117 +DATA 4 0x40AB001C 0x00000000
  118 +
  119 +#endif
board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg
Diff comments   View file @ 76a14d2
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +BOOT_FROM sd
  25 +
  26 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  27 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  28 +PLUGIN board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
  29 +#else
  30 +
  31 +#ifdef CONFIG_SECURE_BOOT
  32 +CSF CONFIG_CSF_SIZE
  33 +#endif
  34 +/*
  35 + * Device Configuration Data (DCD)
  36 + *
  37 + * Each entry must have the format:
  38 + * Addr-type Address Value
  39 + *
  40 + * where:
  41 + * Addr-type register length (1,2 or 4 bytes)
  42 + * Address absolute address of the register
  43 + * value value to be stored in the register
  44 + */
  45 +DATA 4 0x403f00e0 0x00000000
  46 +DATA 4 0x403e0040 0x01000020
  47 +DATA 4 0x403e050c 0x80808080
  48 +DATA 4 0x403e050c 0x8080801E
  49 +CHECK_BITS_SET 4 0x403e050c 0x00000040
  50 +DATA 4 0x403E0030 0x00000001
  51 +DATA 4 0x403e0040 0x11000020
  52 +DATA 4 0x403f00e0 0x42000000
  53 +
  54 +DATA 4 0x40B300AC 0x40000000
  55 +
  56 +DATA 4 0x40AD0128 0x00040000
  57 +DATA 4 0x40AD00F8 0x00000000
  58 +DATA 4 0x40AD00D8 0x0000018C
  59 +DATA 4 0x40AD0108 0x00000180
  60 +DATA 4 0x40AD0104 0x00000180
  61 +DATA 4 0x40AD0124 0x00010000
  62 +DATA 4 0x40AD0080 0x0000018C
  63 +DATA 4 0x40AD0084 0x0000018C
  64 +DATA 4 0x40AD0088 0x0000018C
  65 +DATA 4 0x40AD008C 0x0000018C
  66 +
  67 +DATA 4 0x40AD0120 0x00010000
  68 +DATA 4 0x40AD010C 0x00000180
  69 +DATA 4 0x40AD0110 0x00000180
  70 +DATA 4 0x40AD0114 0x00000180
  71 +DATA 4 0x40AD0118 0x00000180
  72 +DATA 4 0x40AD0090 0x00000180
  73 +DATA 4 0x40AD0094 0x00000180
  74 +DATA 4 0x40AD0098 0x00000180
  75 +DATA 4 0x40AD009C 0x00000180
  76 +
  77 +DATA 4 0x40AD00E0 0x00040000
  78 +DATA 4 0x40AD00E4 0x00040000
  79 +
  80 +DATA 4 0x40AB001C 0x00008000
  81 +DATA 4 0x40AB0800 0xA1390003
  82 +DATA 4 0x40AB085C 0x0D3900A0
  83 +DATA 4 0x40AB0890 0x00400000
  84 +
  85 +DATA 4 0x40AB0848 0x40404040
  86 +DATA 4 0x40AB0850 0x40404040
  87 +DATA 4 0x40AB081C 0x33333333
  88 +DATA 4 0x40AB0820 0x33333333
  89 +DATA 4 0x40AB0824 0x33333333
  90 +DATA 4 0x40AB0828 0x33333333
  91 +
  92 +DATA 4 0x40AB08C0 0x24922492
  93 +DATA 4 0x40AB08B8 0x00000800
  94 +
  95 +DATA 4 0x40AB0004 0x00020052
  96 +DATA 4 0x40AB000C 0x292C42F3
  97 +DATA 4 0x40AB0010 0x00100A22
  98 +DATA 4 0x40AB0038 0x00120556
  99 +DATA 4 0x40AB0014 0x00C700DB
  100 +DATA 4 0x40AB0018 0x00211708
  101 +DATA 4 0x40AB002C 0x0F9F26D2
  102 +DATA 4 0x40AB0030 0x009F0E10
  103 +DATA 4 0x40AB0040 0x0000003F
  104 +DATA 4 0x40AB0000 0xC3110000
  105 +
  106 +DATA 4 0x40AB001C 0x00008010
  107 +DATA 4 0x40AB001C 0x00008018
  108 +DATA 4 0x40AB001C 0x003F8030
  109 +DATA 4 0x40AB001C 0x003F8038
  110 +DATA 4 0x40AB001C 0xFF0A8030
  111 +DATA 4 0x40AB001C 0xFF0A8038
  112 +DATA 4 0x40AB001C 0x04028030
  113 +DATA 4 0x40AB001C 0x04028038
  114 +DATA 4 0x40AB001C 0x82018030
  115 +DATA 4 0x40AB001C 0x82018038
  116 +DATA 4 0x40AB001C 0x01038030
  117 +DATA 4 0x40AB001C 0x01038038
  118 +
  119 +DATA 4 0x40AB083C 0x20000000
  120 +
  121 +DATA 4 0x40AB0020 0x00001800
  122 +DATA 4 0x40AB0800 0xA1390003
  123 +DATA 4 0x40AB0004 0x00020052
  124 +DATA 4 0x40AB0404 0x00011006
  125 +DATA 4 0x40AB001C 0x00000000
  126 +
  127 +#endif
board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
Diff comments   View file @ 76a14d2
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <asm/io.h>
  9 +#include <asm/arch/clock.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/arch/mx7ulp-pins.h>
  12 +#include <asm/arch/iomux.h>
  13 +#include <asm/gpio.h>
  14 +#include <fsl_esdhc.h>
  15 +#include <mmc.h>
  16 +#include <usb.h>
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE)
  21 +#define ESDHC_CD_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_PUS_UP)
  22 +
  23 +#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
  24 +
  25 +#define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE)
  26 +
  27 +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE)
  28 +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE)
  29 +
  30 +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE)
  31 +
  32 +#define QSPI_PAD_CTRL0 (PAD_CTL_PUS_UP | PAD_CTL_DSE \
  33 + | PAD_CTL_OBE_ENABLE)
  34 +
  35 +
  36 +int dram_init(void)
  37 +{
  38 + gd->ram_size = PHYS_SDRAM_SIZE;
  39 +
  40 + return 0;
  41 +}
  42 +
  43 +static int mx7ulp_board_rev(void)
  44 +{
  45 + return 0x41;
  46 +}
  47 +
  48 +u32 get_board_rev(void)
  49 +{
  50 + int rev = mx7ulp_board_rev();
  51 +
  52 + return (get_cpu_rev() & ~(0xF << 8)) | rev;
  53 +}
  54 +
  55 +static iomux_cfg_t const lpuart4_pads[] = {
  56 + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  57 + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  58 +};
  59 +
  60 +/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 ARM2, depends on rework*/
  61 +static iomux_cfg_t const lpuart6_pads[] = {
  62 + MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63 + MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  64 +};
  65 +
  66 +static void setup_iomux_uart(void)
  67 +{
  68 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  69 + mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart4_pads));
  70 +#else
  71 + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads));
  72 +#endif
  73 +}
  74 +
  75 +#ifdef CONFIG_USB_EHCI_MX7
  76 +
  77 +static iomux_cfg_t const usb_otg1_pads[] = {
  78 +
  79 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  80 + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */
  81 + MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */
  82 +#else
  83 + /*Need rework for ID and PWR_EN pins on 14x14 ARM2*/
  84 + MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */
  85 + MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */
  86 +#endif
  87 +};
  88 +
  89 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  90 +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 0)
  91 +#define OTG0_PWR_EN IMX_GPIO_NR(3, 1)
  92 +#else
  93 +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 18)
  94 +#define OTG0_PWR_EN IMX_GPIO_NR(1, 31)
  95 +#endif
  96 +static void setup_usb(void)
  97 +{
  98 + mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads,
  99 + ARRAY_SIZE(usb_otg1_pads));
  100 +
  101 + gpio_request(OTG0_ID_GPIO, "otg_id");
  102 + gpio_direction_input(OTG0_ID_GPIO);
  103 +}
  104 +
  105 +/*Needs to override the ehci power if controlled by GPIO */
  106 +int board_ehci_power(int port, int on)
  107 +{
  108 + switch (port) {
  109 + case 0:
  110 + if (on)
  111 + gpio_direction_output(OTG0_PWR_EN, 1);
  112 + else
  113 + gpio_direction_output(OTG0_PWR_EN, 0);
  114 + break;
  115 + default:
  116 + printf("MXC USB port %d not yet supported\n", port);
  117 + return -EINVAL;
  118 + }
  119 +
  120 + return 0;
  121 +}
  122 +
  123 +int board_usb_phy_mode(int port)
  124 +{
  125 + int ret = 0;
  126 +
  127 + if (port == 0) {
  128 + ret = gpio_get_value(OTG0_ID_GPIO);
  129 +
  130 + if (ret)
  131 + return USB_INIT_DEVICE;
  132 + else
  133 + return USB_INIT_HOST;
  134 + }
  135 +
  136 + return USB_INIT_HOST;
  137 +}
  138 +
  139 +#endif
  140 +
  141 +
  142 +int board_early_init_f(void)
  143 +{
  144 + setup_iomux_uart();
  145 +
  146 + return 0;
  147 +}
  148 +
  149 +#ifdef CONFIG_FSL_QSPI
  150 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  151 +static iomux_cfg_t const quadspi_pads[] = {
  152 + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  153 + MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  154 + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  155 + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  156 + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  157 + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  158 + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  159 +
  160 + MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  161 +};
  162 +
  163 +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 5)
  164 +#else
  165 +/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/
  166 +static iomux_cfg_t const quadspi_pads[] = {
  167 + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  168 + MX7ULP_PAD_PTB9__QSPIA_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  169 + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  170 + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  171 + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  172 + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  173 + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  174 +
  175 + MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  176 +};
  177 +
  178 +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 12)
  179 +
  180 +#endif
  181 +int board_qspi_init(void)
  182 +{
  183 + u32 val;
  184 + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
  185 + /* enable clock */
  186 + val = readl(PCC1_RBASE + 0x94);
  187 +
  188 + if (!(val & 0x20000000)) {
  189 + writel(0x03000003, (PCC1_RBASE + 0x94));
  190 + writel(0x43000003, (PCC1_RBASE + 0x94));
  191 + }
  192 +
  193 + gpio_request(QSPI_RST_GPIO, "qspi_reset");
  194 + gpio_direction_output(QSPI_RST_GPIO, 0);
  195 + mdelay(10);
  196 + gpio_direction_output(QSPI_RST_GPIO, 1);
  197 + return 0;
  198 +}
  199 +#endif
  200 +
  201 +int board_init(void)
  202 +{
  203 + /* address of boot parameters */
  204 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  205 +
  206 +#ifdef CONFIG_USB_EHCI_MX7
  207 + setup_usb();
  208 +#endif
  209 +
  210 +#ifdef CONFIG_FSL_QSPI
  211 + board_qspi_init();
  212 +#endif
  213 +
  214 + return 0;
  215 +}
  216 +
  217 +#ifdef CONFIG_FSL_ESDHC
  218 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  219 + {USDHC0_RBASE, 0, 8},
  220 + {USDHC1_RBASE, 0},
  221 +};
  222 +
  223 +static iomux_cfg_t const usdhc0_emmc_pads[] = {
  224 + MX7ULP_PAD_PTD0__SDHC0_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  225 + MX7ULP_PAD_PTD1__SDHC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  226 + MX7ULP_PAD_PTD2__SDHC0_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  227 + MX7ULP_PAD_PTD3__SDHC0_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  228 + MX7ULP_PAD_PTD4__SDHC0_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  229 + MX7ULP_PAD_PTD5__SDHC0_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  230 + MX7ULP_PAD_PTD6__SDHC0_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  231 + MX7ULP_PAD_PTD7__SDHC0_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  232 + MX7ULP_PAD_PTD8__SDHC0_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  233 + MX7ULP_PAD_PTD9__SDHC0_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  234 + MX7ULP_PAD_PTD10__SDHC0_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  235 + MX7ULP_PAD_PTD11__SDHC0_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  236 +};
  237 +
  238 +static iomux_cfg_t const usdhc1_pads[] = {
  239 + MX7ULP_PAD_PTE11__SDHC1_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  240 + MX7ULP_PAD_PTE3__SDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  241 + MX7ULP_PAD_PTE2__SDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  242 + MX7ULP_PAD_PTE9__SDHC1_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  243 + MX7ULP_PAD_PTE8__SDHC1_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  244 + MX7ULP_PAD_PTE7__SDHC1_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  245 + MX7ULP_PAD_PTE6__SDHC1_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  246 + MX7ULP_PAD_PTE4__SDHC1_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  247 + MX7ULP_PAD_PTE5__SDHC1_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  248 + MX7ULP_PAD_PTE0__SDHC1_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  249 + MX7ULP_PAD_PTE1__SDHC1_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  250 + MX7ULP_PAD_PTE10__SDHC1_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  251 +
  252 + MX7ULP_PAD_PTE13__PTE13 | MUX_PAD_CTRL(ESDHC_CD_GPIO_PAD_CTRL), /*CD*/
  253 +};
  254 +
  255 +#define USDHC0_CD_GPIO IMX_GPIO_NR(5, 13)
  256 +
  257 +int board_mmc_init(bd_t *bis)
  258 +{
  259 + int i, ret;
  260 + /*
  261 + * According to the board_mmc_init() the following map is done:
  262 + * (U-Boot device node) (Physical Port)
  263 + * mmc0 USDHC0
  264 + * mmc1 USDHC1
  265 + */
  266 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  267 + switch (i) {
  268 + case 0:
  269 + mx7ulp_iomux_setup_multiple_pads(usdhc0_emmc_pads, ARRAY_SIZE(usdhc0_emmc_pads));
  270 + init_clk_usdhc(0);
  271 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  272 +
  273 + break;
  274 + case 1:
  275 + mx7ulp_iomux_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  276 + init_clk_usdhc(1);
  277 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  278 +
  279 + gpio_request(USDHC0_CD_GPIO, "usdhc1_cd");
  280 + gpio_direction_input(USDHC0_CD_GPIO);
  281 + break;
  282 + default:
  283 + printf("Warning: you configured more USDHC controllers"
  284 + "(%d) than supported by the board\n", i + 1);
  285 + return -EINVAL;
  286 + }
  287 +
  288 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  289 + if (ret)
  290 + return ret;
  291 + }
  292 +
  293 + return 0;
  294 +}
  295 +
  296 +int board_mmc_getcd(struct mmc *mmc)
  297 +{
  298 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  299 + int ret = 0;
  300 +
  301 + switch (cfg->esdhc_base) {
  302 + case USDHC0_RBASE:
  303 + ret = 1;
  304 + break;
  305 + case USDHC1_RBASE:
  306 + ret = !gpio_get_value(USDHC0_CD_GPIO);
  307 + break;
  308 + }
  309 + return ret;
  310 +}
  311 +#endif
  312 +
  313 +
  314 +int board_late_init(void)
  315 +{
  316 + return 0;
  317 +}
  318 +
  319 +int checkboard(void)
  320 +{
  321 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  322 + printf("Board: i.MX7ULP 10x10 ARM2 board\n");
  323 +#else
  324 + printf("Board: i.MX7ULP 14x14 ARM2 board\n");
  325 +#endif
  326 + return 0;
  327 +}
board/freescale/mx7ulp_arm2/plugin.S
Diff comments   View file @ 76a14d2
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <config.h>
  9 +
  10 +.macro imx7ulp_ddr_freq_decrease
  11 + ldr r2, =0x403f0000
  12 + ldr r3, =0x00000000
  13 + str r3, [r2, #0xe0]
  14 +
  15 + ldr r2, =0x403e0000
  16 + ldr r3, =0x01000020
  17 + str r3, [r2, #0x40]
  18 +
  19 + ldr r3, =0x80808080
  20 + str r3, [r2, #0x50c]
  21 + ldr r3, =0x8080801E
  22 + str r3, [r2, #0x50c]
  23 +
  24 + ldr r3, =0x00000040
  25 +wait2:
  26 + ldr r4, [r2, #0x50c]
  27 + and r4, r3
  28 + cmp r4, r3
  29 + bne wait2
  30 +
  31 + ldr r3, =0x00000001
  32 + str r3, [r2, #0x30]
  33 + ldr r3, =0x11000020
  34 + str r3, [r2, #0x40]
  35 +
  36 + ldr r2, =0x403f0000
  37 + ldr r3, =0x42000000
  38 + str r3, [r2, #0xe0]
  39 +
  40 +.endm
  41 +
  42 +.macro imx7ulp_arm2_lpddr3_setting
  43 +
  44 + imx7ulp_ddr_freq_decrease
  45 +
  46 + /* Enable MMDC PCC clock */
  47 + ldr r2, =0x40b30000
  48 + ldr r3, =0x40000000
  49 + str r3, [r2, #0xac]
  50 +
  51 + /* Configure DDR pad */
  52 + ldr r0, =0x40ad0000
  53 + ldr r1, =0x00040000
  54 + str r1, [r0, #0x128]
  55 + ldr r1, =0x0
  56 + str r1, [r0, #0xf8]
  57 + ldr r1, =0x00000180
  58 + str r1, [r0, #0xd8]
  59 + ldr r1, =0x00000180
  60 + str r1, [r0, #0x108]
  61 + ldr r1, =0x00000180
  62 + str r1, [r0, #0x104]
  63 + ldr r1, =0x00010000
  64 + str r1, [r0, #0x124]
  65 + ldr r1, =0x0000018C
  66 + str r1, [r0, #0x80]
  67 + ldr r1, =0x0000018C
  68 + str r1, [r0, #0x84]
  69 + ldr r1, =0x0000018C
  70 + str r1, [r0, #0x88]
  71 + ldr r1, =0x0000018C
  72 + str r1, [r0, #0x8c]
  73 +
  74 + ldr r1, =0x00010000
  75 + str r1, [r0, #0x120]
  76 + ldr r1, =0x00000180
  77 + str r1, [r0, #0x10c]
  78 + ldr r1, =0x00000180
  79 + str r1, [r0, #0x110]
  80 + ldr r1, =0x00000180
  81 + str r1, [r0, #0x114]
  82 + ldr r1, =0x00000180
  83 + str r1, [r0, #0x118]
  84 + ldr r1, =0x00000180
  85 + str r1, [r0, #0x90]
  86 + ldr r1, =0x00000180
  87 + str r1, [r0, #0x94]
  88 + ldr r1, =0x00000180
  89 + str r1, [r0, #0x98]
  90 + ldr r1, =0x00000180
  91 + str r1, [r0, #0x9c]
  92 + ldr r1, =0x00040000
  93 + str r1, [r0, #0xe0]
  94 + ldr r1, =0x00040000
  95 + str r1, [r0, #0xe4]
  96 +
  97 + ldr r0, =0x40ab0000
  98 + ldr r1, =0x00008000
  99 + str r1, [r0, #0x1c]
  100 + ldr r1, =0xA1390003
  101 + str r1, [r0, #0x800]
  102 + ldr r1, =0x0D3900A0
  103 + str r1, [r0, #0x85c]
  104 + ldr r1, =0x00400000
  105 + str r1, [r0, #0x890]
  106 +
  107 + ldr r1, =0x39373939
  108 + str r1, [r0, #0x848]
  109 + ldr r1, =0x2F313D36
  110 + str r1, [r0, #0x850]
  111 + ldr r1, =0x33333333
  112 + str r1, [r0, #0x81c]
  113 + ldr r1, =0x33333333
  114 + str r1, [r0, #0x820]
  115 + ldr r1, =0x33333333
  116 + str r1, [r0, #0x824]
  117 + ldr r1, =0x33333333
  118 + str r1, [r0, #0x828]
  119 +
  120 + ldr r1, =0x24922492
  121 + str r1, [r0, #0x8c0]
  122 + ldr r1, =0x00000800
  123 + str r1, [r0, #0x8b8]
  124 +
  125 + ldr r1, =0x00020052
  126 + str r1, [r0, #0x4]
  127 + ldr r1, =0x424642F3
  128 + str r1, [r0, #0xc]
  129 + ldr r1, =0x00100A22
  130 + str r1, [r0, #0x10]
  131 + ldr r1, =0x00120556
  132 + str r1, [r0, #0x38]
  133 + ldr r1, =0x00C700DA
  134 + str r1, [r0, #0x14]
  135 + ldr r1, =0x00211718
  136 + str r1, [r0, #0x18]
  137 +
  138 + ldr r1, =0x0F9F26D2
  139 + str r1, [r0, #0x2c]
  140 + ldr r1, =0x009F0E10
  141 + str r1, [r0, #0x30]
  142 + ldr r1, =0x0000004F
  143 + str r1, [r0, #0x40]
  144 + ldr r1, =0x84190000
  145 + str r1, [r0, #0x0]
  146 +
  147 + ldr r1, =0x00008010
  148 + str r1, [r0, #0x1c]
  149 + ldr r1, =0x003F8030
  150 + str r1, [r0, #0x1c]
  151 + ldr r1, =0xFF0A8030
  152 + str r1, [r0, #0x1c]
  153 + ldr r1, =0x04028030
  154 + str r1, [r0, #0x1c]
  155 + ldr r1, =0x83018030
  156 + str r1, [r0, #0x1c]
  157 + ldr r1, =0x01038030
  158 + str r1, [r0, #0x1c]
  159 +
  160 + ldr r1, =0x20000000
  161 + str r1, [r0, #0x83c]
  162 +
  163 + ldr r1, =0x00001800
  164 + str r1, [r0, #0x20]
  165 + ldr r1, =0xA1310003
  166 + str r1, [r0, #0x800]
  167 + ldr r1, =0x00000000
  168 + str r1, [r0, #0x1c]
  169 +
  170 +.endm
  171 +
  172 +.macro imx7ulp_arm2_lpddr2_setting
  173 +
  174 + imx7ulp_ddr_freq_decrease
  175 +
  176 + /* Enable MMDC PCC clock */
  177 + ldr r2, =0x40b30000
  178 + ldr r3, =0x40000000
  179 + str r3, [r2, #0xac]
  180 +
  181 + /* Configure DDR pad */
  182 + ldr r0, =0x40ad0000
  183 + ldr r1, =0x00040000
  184 + str r1, [r0, #0x128]
  185 + ldr r1, =0x0
  186 + str r1, [r0, #0xf8]
  187 + ldr r1, =0x0000018C
  188 + str r1, [r0, #0xd8]
  189 + ldr r1, =0x00000180
  190 + str r1, [r0, #0x108]
  191 + ldr r1, =0x00000180
  192 + str r1, [r0, #0x104]
  193 + ldr r1, =0x00010000
  194 + str r1, [r0, #0x124]
  195 + ldr r1, =0x0000018C
  196 + str r1, [r0, #0x80]
  197 + ldr r1, =0x0000018C
  198 + str r1, [r0, #0x84]
  199 + ldr r1, =0x0000018C
  200 + str r1, [r0, #0x88]
  201 + ldr r1, =0x0000018C
  202 + str r1, [r0, #0x8c]
  203 +
  204 + ldr r1, =0x00010000
  205 + str r1, [r0, #0x120]
  206 + ldr r1, =0x00000180
  207 + str r1, [r0, #0x10c]
  208 + ldr r1, =0x00000180
  209 + str r1, [r0, #0x110]
  210 + ldr r1, =0x00000180
  211 + str r1, [r0, #0x114]
  212 + ldr r1, =0x00000180
  213 + str r1, [r0, #0x118]
  214 + ldr r1, =0x00000180
  215 + str r1, [r0, #0x90]
  216 + ldr r1, =0x00000180
  217 + str r1, [r0, #0x94]
  218 + ldr r1, =0x00000180
  219 + str r1, [r0, #0x98]
  220 + ldr r1, =0x00000180
  221 + str r1, [r0, #0x9c]
  222 + ldr r1, =0x00040000
  223 + str r1, [r0, #0xe0]
  224 + ldr r1, =0x00040000
  225 + str r1, [r0, #0xe4]
  226 +
  227 + ldr r0, =0x40ab0000
  228 + ldr r1, =0x00008000
  229 + str r1, [r0, #0x1c]
  230 + ldr r1, =0xA1390003
  231 + str r1, [r0, #0x800]
  232 + ldr r1, =0x0D3900A0
  233 + str r1, [r0, #0x85c]
  234 + ldr r1, =0x00400000
  235 + str r1, [r0, #0x890]
  236 +
  237 + ldr r1, =0x40404040
  238 + str r1, [r0, #0x848]
  239 + ldr r1, =0x40404040
  240 + str r1, [r0, #0x850]
  241 + ldr r1, =0x33333333
  242 + str r1, [r0, #0x81c]
  243 + ldr r1, =0x33333333
  244 + str r1, [r0, #0x820]
  245 + ldr r1, =0x33333333
  246 + str r1, [r0, #0x824]
  247 + ldr r1, =0x33333333
  248 + str r1, [r0, #0x828]
  249 +
  250 + ldr r1, =0x24922492
  251 + str r1, [r0, #0x8c0]
  252 + ldr r1, =0x00000800
  253 + str r1, [r0, #0x8b8]
  254 +
  255 + ldr r1, =0x00020052
  256 + str r1, [r0, #0x4]
  257 + ldr r1, =0x292C42F3
  258 + str r1, [r0, #0xc]
  259 + ldr r1, =0x00100A22
  260 + str r1, [r0, #0x10]
  261 + ldr r1, =0x00120556
  262 + str r1, [r0, #0x38]
  263 + ldr r1, =0x00C700DB
  264 + str r1, [r0, #0x14]
  265 + ldr r1, =0x00211708
  266 + str r1, [r0, #0x18]
  267 +
  268 + ldr r1, =0x0F9F26D2
  269 + str r1, [r0, #0x2c]
  270 + ldr r1, =0x009F0E10
  271 + str r1, [r0, #0x30]
  272 + ldr r1, =0x0000003F
  273 + str r1, [r0, #0x40]
  274 + ldr r1, =0xC3110000
  275 + str r1, [r0, #0x0]
  276 +
  277 + ldr r1, =0x00008010
  278 + str r1, [r0, #0x1c]
  279 + ldr r1, =0x00008018
  280 + str r1, [r0, #0x1c]
  281 + ldr r1, =0x003F8030
  282 + str r1, [r0, #0x1c]
  283 + ldr r1, =0x003F8038
  284 + str r1, [r0, #0x1c]
  285 + ldr r1, =0xFF0A8030
  286 + str r1, [r0, #0x1c]
  287 + ldr r1, =0xFF0A8038
  288 + str r1, [r0, #0x1c]
  289 + ldr r1, =0x04028030
  290 + str r1, [r0, #0x1c]
  291 + ldr r1, =0x04028038
  292 + str r1, [r0, #0x1c]
  293 + ldr r1, =0x82018030
  294 + str r1, [r0, #0x1c]
  295 + ldr r1, =0x82018038
  296 + str r1, [r0, #0x1c]
  297 + ldr r1, =0x01038030
  298 + str r1, [r0, #0x1c]
  299 + ldr r1, =0x01038038
  300 + str r1, [r0, #0x1c]
  301 +
  302 + ldr r1, =0x20000000
  303 + str r1, [r0, #0x83c]
  304 +
  305 + ldr r1, =0x00001800
  306 + str r1, [r0, #0x20]
  307 + ldr r1, =0xA1390003
  308 + str r1, [r0, #0x800]
  309 + ldr r1, =0x00020052
  310 + str r1, [r0, #0x4]
  311 + ldr r1, =0x00011006
  312 + str r1, [r0, #0x404]
  313 + ldr r1, =0x00000000
  314 + str r1, [r0, #0x1c]
  315 +
  316 +.endm
  317 +
  318 +
  319 +.macro imx7ulp_clock_gating
  320 +.endm
  321 +
  322 +.macro imx7ulp_qos_setting
  323 +.endm
  324 +
  325 +.macro imx7ulp_ddr_setting
  326 +#if defined (CONFIG_TARGET_MX7ULP_10X10_ARM2)
  327 + imx7ulp_arm2_lpddr2_setting
  328 +#else
  329 + imx7ulp_arm2_lpddr3_setting
  330 +#endif
  331 +.endm
  332 +
  333 +/* include the common plugin code here */
  334 +#include <asm/arch/mx7ulp_plugin.S>
configs/mx7ulp_10x10_arm2_defconfig
Diff comments   View file @ 76a14d2
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX7ULP=y
  4 +CONFIG_TARGET_MX7ULP_10X10_ARM2=y
  5 +CONFIG_SYS_MALLOC_F=y
  6 +CONFIG_SYS_MALLOC_F_LEN=0x400
  7 +CONFIG_DM=y
  8 +CONFIG_DM_SERIAL=y
  9 +CONFIG_DM_GPIO=y
  10 +CONFIG_IMX_RGPIO2P=y
configs/mx7ulp_14x14_arm2_defconfig
Diff comments   View file @ 76a14d2
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage.cfg"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX7ULP=y
  4 +CONFIG_TARGET_MX7ULP_14X14_ARM2=y
  5 +CONFIG_SYS_MALLOC_F=y
  6 +CONFIG_SYS_MALLOC_F_LEN=0x400
  7 +CONFIG_DM=y
  8 +CONFIG_DM_SERIAL=y
  9 +CONFIG_DM_GPIO=y
  10 +CONFIG_IMX_RGPIO2P=y
include/configs/mx7ulp_arm2.h
Diff comments   View file @ 76a14d2
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX7ULP ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX7ULP_ARM2_CONFIG_H
  10 +#define __MX7ULP_ARM2_CONFIG_H
  11 +
  12 +#include <linux/sizes.h>
  13 +#include <asm/arch/imx-regs.h>
  14 +
  15 +/*Uncomment it to use plugin boot*/
  16 +/*#define CONFIG_USE_PLUGIN*/
  17 +
  18 +/*Uncomment it to use secure boot*/
  19 +/*#define CONFIG_SECURE_BOOT*/
  20 +
  21 +#ifdef CONFIG_SECURE_BOOT
  22 +#ifndef CONFIG_CSF_SIZE
  23 +#define CONFIG_CSF_SIZE 0x4000
  24 +#endif
  25 +#endif
  26 +
  27 +#define CONFIG_SYS_VSNPRINTF
  28 +#define CONFIG_BOARD_POSTCLK_INIT
  29 +#define CONFIG_IMX_FIXED_IVT_OFFSET
  30 +#define CONFIG_SYS_BOOTM_LEN 0x1000000
  31 +
  32 +#define SRC_BASE_ADDR CMC1_RBASE
  33 +#define IRAM_BASE_ADDR OCRAM_0_BASE
  34 +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
  35 +
  36 +/* Fuses */
  37 +#define CONFIG_CMD_FUSE
  38 +#define CONFIG_MXC_OCOTP
  39 +
  40 +/* MMC Configs */
  41 +#define CONFIG_MMC
  42 +#define CONFIG_CMD_MMC
  43 +#define CONFIG_GENERIC_MMC
  44 +#define CONFIG_BOUNCE_BUFFER
  45 +#define CONFIG_FSL_ESDHC
  46 +#define CONFIG_FSL_USDHC
  47 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  48 +
  49 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  50 +
  51 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  52 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  53 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  54 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  55 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  56 +
  57 +#define CONFIG_ENV_OFFSET (12 * SZ_64K)
  58 +#define CONFIG_ENV_IS_IN_MMC
  59 +#define CONFIG_ENV_SIZE SZ_8K
  60 +
  61 +#define CONFIG_CMD_FAT
  62 +#define CONFIG_DOS_PARTITION
  63 +
  64 +/* Using ULP WDOG for reset */
  65 +#define WDOG_BASE_ADDR WDG1_RBASE
  66 +#define CONFIG_ULP_WATCHDOG
  67 +
  68 +
  69 +#define CONFIG_SYS_ARCH_TIMER
  70 +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
  71 +
  72 +#define CONFIG_DISPLAY_CPUINFO
  73 +#define CONFIG_DISPLAY_BOARDINFO
  74 +
  75 +/* uncomment for PLUGIN mode support */
  76 +/* #define CONFIG_USE_PLUGIN */
  77 +
  78 +/* uncomment for SECURE mode support */
  79 +/* #define CONFIG_SECURE_BOOT */
  80 +
  81 +#define CONFIG_INITRD_TAG
  82 +#define CONFIG_CMDLINE_TAG
  83 +#define CONFIG_SETUP_MEMORY_TAGS
  84 +/*#define CONFIG_REVISION_TAG*/
  85 +
  86 +/* Size of malloc() pool */
  87 +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
  88 +
  89 +#define CONFIG_BOARD_LATE_INIT
  90 +#define CONFIG_BOARD_EARLY_INIT_F
  91 +
  92 +/* UART */
  93 +#define CONFIG_FSL_LPUART
  94 +#define CONFIG_LPUART_32LE_REG
  95 +
  96 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  97 +#define LPUART_BASE LPUART6_RBASE
  98 +#else
  99 +#define LPUART_BASE LPUART4_RBASE
  100 +#endif
  101 +
  102 +/* allow to overwrite serial and ethaddr */
  103 +#define CONFIG_ENV_OVERWRITE
  104 +#define CONFIG_CONS_INDEX 1
  105 +#define CONFIG_BAUDRATE 115200
  106 +
  107 +
  108 +#undef CONFIG_CMD_IMLS
  109 +#define CONFIG_SYS_LONGHELP
  110 +#define CONFIG_AUTO_COMPLETE
  111 +#define CONFIG_SYS_HUSH_PARSER
  112 +
  113 +#define CONFIG_BOOTDELAY 1
  114 +#define CONFIG_SYS_CACHELINE_SIZE 64
  115 +
  116 +/* Miscellaneous configurable options */
  117 +#define CONFIG_SYS_PROMPT "=> "
  118 +#define CONFIG_SYS_CBSIZE 512
  119 +
  120 +/* Print Buffer Size */
  121 +#define CONFIG_SYS_MAXARGS 256
  122 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  123 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  124 +
  125 +#define CONFIG_CMDLINE_EDITING
  126 +#define CONFIG_STACKSIZE SZ_8K
  127 +
  128 +/* Physical Memory Map */
  129 +#define CONFIG_NR_DRAM_BANKS 1
  130 +
  131 +#define CONFIG_SYS_TEXT_BASE 0x67800000
  132 +#define PHYS_SDRAM 0x60000000
  133 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  134 +#define PHYS_SDRAM_SIZE SZ_1G /*LPDDR2 1G*/
  135 +#define CONFIG_SYS_MEMTEST_END 0x9E000000
  136 +#else
  137 +#define PHYS_SDRAM_SIZE SZ_512M
  138 +#define CONFIG_SYS_MEMTEST_END 0x7E000000
  139 +#endif
  140 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  141 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  142 +#define CONFIG_CMD_BOOTZ
  143 +#define CONFIG_OF_LIBFDT
  144 +
  145 +#define CONFIG_LOADADDR 0x60800000
  146 +
  147 +#define CONFIG_CMD_MEMTEST
  148 +
  149 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  150 +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-10x10-arm2.dtb"
  151 +#else
  152 +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-14x14-arm2.dtb"
  153 +#endif
  154 +
  155 +#define CONFIG_MFG_NAND_PARTITION
  156 +
  157 +#define CONFIG_MFG_ENV_SETTINGS \
  158 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  159 + "rdinit=/linuxrc " \
  160 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  161 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  162 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  163 + "g_mass_storage.iSerialNumber=\"\" "\
  164 + CONFIG_MFG_NAND_PARTITION \
  165 + "\0" \
  166 + "initrd_addr=0x63800000\0" \
  167 + "initrd_high=0xffffffff\0" \
  168 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  169 +
  170 +
  171 +#define CONFIG_EXTRA_ENV_SETTINGS \
  172 + CONFIG_MFG_ENV_SETTINGS \
  173 + "script=boot.scr\0" \
  174 + "image=zImage\0" \
  175 + "console=ttyLP0\0" \
  176 + "fdt_high=0xffffffff\0" \
  177 + "initrd_high=0xffffffff\0" \
  178 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  179 + "fdt_addr=0x63000000\0" \
  180 + "boot_fdt=try\0" \
  181 + "earlycon=lpuart32,0x402D0010\0" \
  182 + "ip_dyn=yes\0" \
  183 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  184 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  185 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  186 + "mmcautodetect=yes\0" \
  187 + "mmcargs=setenv bootargs console=${console},${baudrate} " \
  188 + "root=${mmcroot}\0" \
  189 + "loadbootscript=" \
  190 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  191 + "bootscript=echo Running bootscript from mmc ...; " \
  192 + "source\0" \
  193 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  194 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  195 + "mmcboot=echo Booting from mmc ...; " \
  196 + "run mmcargs; " \
  197 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  198 + "if run loadfdt; then " \
  199 + "bootz ${loadaddr} - ${fdt_addr}; " \
  200 + "else " \
  201 + "if test ${boot_fdt} = try; then " \
  202 + "bootz; " \
  203 + "else " \
  204 + "echo WARN: Cannot load the DT; " \
  205 + "fi; " \
  206 + "fi; " \
  207 + "else " \
  208 + "bootz; " \
  209 + "fi;\0" \
  210 +
  211 +#define CONFIG_BOOTCOMMAND \
  212 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  213 + "if run loadbootscript; then " \
  214 + "run bootscript; " \
  215 + "else " \
  216 + "if run loadimage; then " \
  217 + "run mmcboot; " \
  218 + "fi; " \
  219 + "fi; " \
  220 + "fi"
  221 +
  222 +
  223 +#define CONFIG_SYS_HZ 1000
  224 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  225 +
  226 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  227 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
  228 +
  229 +#define CONFIG_SYS_INIT_SP_OFFSET \
  230 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  231 +#define CONFIG_SYS_INIT_SP_ADDR \
  232 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  233 +
  234 +/* FLASH and environment organization */
  235 +#define CONFIG_SYS_NO_FLASH
  236 +
  237 +#ifndef CONFIG_SYS_DCACHE_OFF
  238 +#define CONFIG_CMD_CACHE
  239 +#endif
  240 +
  241 +/* USB Configs */
  242 +#define CONFIG_CMD_USB
  243 +#define CONFIG_USB_EHCI
  244 +#define CONFIG_USB_EHCI_MX7
  245 +#define CONFIG_USB_STORAGE
  246 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  247 +#define CONFIG_USB_HOST_ETHER
  248 +#define CONFIG_USB_ETHER_ASIX
  249 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  250 +#define CONFIG_MXC_USB_FLAGS 0
  251 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  252 +
  253 +/* QSPI configs */
  254 +#define CONFIG_FSL_QSPI
  255 +#ifdef CONFIG_FSL_QSPI
  256 +#define CONFIG_CMD_SF
  257 +#define CONFIG_SPI_FLASH
  258 +#define CONFIG_SPI_FLASH_STMICRO
  259 +#define CONFIG_SPI_FLASH_BAR
  260 +#define CONFIG_SYS_FSL_QSPI_AHB
  261 +#define CONFIG_SF_DEFAULT_BUS 0
  262 +#define CONFIG_SF_DEFAULT_CS 0
  263 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  264 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  265 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  266 +#define FSL_QSPI_FLASH_NUM 2
  267 +#define FSL_QSPI_FLASH_SIZE SZ_32M
  268 +#else
  269 +#define FSL_QSPI_FLASH_NUM 1
  270 +#define FSL_QSPI_FLASH_SIZE SZ_64M
  271 +#endif
  272 +#define QSPI0_BASE_ADDR 0x410A5000
  273 +#define QSPI0_AMBA_BASE 0xC0000000
  274 +#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR
  275 +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE
  276 +#endif
  277 +
  278 +#endif /* __CONFIG_H */