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Commit 773f5f63dc0db5e39b4782947e761479ecf1bef2

Authored by Masahiro Yamada
1 parent 4c642e6829
Exists in smarc_8mq_lf_v2020.04 and in 22 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoC 

The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB
memory footprint, which is significant in SPL.

There are PHY parameters for 5 boards, but they are actually not
board specific, but SoC specific.  After all, we just need to have
2 patterns, for LD20 and LD21.  Also, the shift values are small
enough to become "short" type instead of "int".  This change will
save about 3 KB memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Showing 1 changed file with 79 additions and 175 deletions Side-by-side Diff

arch/arm/mach-uniphier/dram/umc-ld20.c
Diff comments   View file @ 773f5f6
1 1 /*
2   - * Copyright (C) 2016 Socionext Inc.
  2 + * Copyright (C) 2016-2017 Socionext Inc.
3 3 *
4   - * based on commit 1f6feb76e7f9753f51955444e422486521f9b3a3 of Diag
  4 + * based on commit e732175d0b0dbc2a3855cb8ac791c538666b6fd4 of Diag
5 5 *
6 6 * SPDX-License-Identifier: GPL-2.0+
7 7 */
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
... ... @@ -77,191 +77,95 @@
77 77 0x00000140, 0x00000180, 0x00000140
78 78 };
79 79  
80   -static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
81   - { /* LD20 reference */
82   - {
83   - 2, 1, 0, 1, 2, 1, 1, 1,
84   - 2, 1, 1, 2, 1, 1, 1, 1,
85   - 1, 2, 1, 1, 1, 2, 1, 1,
86   - 2, 2, 0, 1, 1, 2, 2, 1,
87   - },
88   - {
89   - 1, 1, 0, 1, 2, 2, 1, 1,
90   - 1, 1, 1, 1, 1, 1, 1, 1,
91   - 1, 1, 0, 0, 1, 1, 0, 0,
92   - 0, 1, 1, 1, 2, 1, 2, 1,
93   - },
94   - {
95   - 2, 2, 0, 2, 1, 1, 2, 1,
96   - 1, 1, 0, 1, 1, -1, 1, 1,
97   - 2, 2, 2, 2, 1, 1, 1, 1,
98   - 1, 1, 1, 0, 2, 2, 1, 2,
99   - },
  80 +static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = {
  81 + {
  82 + 2, 1, 0, 1, 2, 1, 1, 1,
  83 + 2, 1, 1, 2, 1, 1, 1, 1,
  84 + 1, 2, 1, 1, 1, 2, 1, 1,
  85 + 2, 2, 0, 1, 1, 2, 2, 1,
100 86 },
101   - { /* LD20 TV */
102   - {
103   - 2, 1, 0, 1, 2, 1, 1, 1,
104   - 2, 1, 1, 2, 1, 1, 1, 1,
105   - 1, 2, 1, 1, 1, 2, 1, 1,
106   - 2, 2, 0, 1, 1, 2, 2, 1,
107   - },
108   - {
109   - 1, 1, 0, 1, 2, 2, 1, 1,
110   - 1, 1, 1, 1, 1, 1, 1, 1,
111   - 1, 1, 0, 0, 1, 1, 0, 0,
112   - 0, 1, 1, 1, 2, 1, 2, 1,
113   - },
114   - {
115   - 2, 2, 0, 2, 1, 1, 2, 1,
116   - 1, 1, 0, 1, 1, -1, 1, 1,
117   - 2, 2, 2, 2, 1, 1, 1, 1,
118   - 1, 1, 1, 0, 2, 2, 1, 2,
119   - },
  87 + {
  88 + 1, 1, 0, 1, 2, 2, 1, 1,
  89 + 1, 1, 1, 1, 1, 1, 1, 1,
  90 + 1, 1, 0, 0, 1, 1, 0, 0,
  91 + 0, 1, 1, 1, 2, 1, 2, 1,
120 92 },
121   - { /* LD20 TV C1 */
122   - {
123   - 2, 1, 0, 1, 2, 1, 1, 1,
124   - 2, 1, 1, 2, 1, 1, 1, 1,
125   - 1, 2, 1, 1, 1, 2, 1, 1,
126   - 2, 2, 0, 1, 1, 2, 2, 1,
127   - },
128   - {
129   - 1, 1, 0, 1, 2, 2, 1, 1,
130   - 1, 1, 1, 1, 1, 1, 1, 1,
131   - 1, 1, 0, 0, 1, 1, 0, 0,
132   - 0, 1, 1, 1, 2, 1, 2, 1,
133   - },
134   - {
135   - 2, 2, 0, 2, 1, 1, 2, 1,
136   - 1, 1, 0, 1, 1, -1, 1, 1,
137   - 2, 2, 2, 2, 1, 1, 1, 1,
138   - 1, 1, 1, 0, 2, 2, 1, 2,
139   - },
  93 + {
  94 + 2, 2, 0, 2, 1, 1, 2, 1,
  95 + 1, 1, 0, 1, 1, -1, 1, 1,
  96 + 2, 2, 2, 2, 1, 1, 1, 1,
  97 + 1, 1, 1, 0, 2, 2, 1, 2,
140 98 },
141   - { /* LD21 reference */
142   - {
143   - 1, 1, 0, 1, 1, 1, 1, 1,
144   - 1, 0, 0, 0, 1, 1, 0, 2,
145   - 1, 1, 0, 0, 1, 1, 1, 1,
146   - 1, 0, 0, 0, 1, 0, 0, 1,
147   - },
148   - { 1, 0, 2, 1, 1, 1, 1, 0,
149   - 1, 0, 0, 1, 0, 1, 0, 0,
150   - 1, 0, 1, 0, 1, 1, 1, 0,
151   - 1, 1, 1, 1, 0, 1, 0, 0,
152   - },
153   - /* No CH2 */
  99 +};
  100 +
  101 +static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = {
  102 + {
  103 + 1, 1, 0, 1, 1, 1, 1, 1,
  104 + 1, 0, 0, 0, 1, 1, 0, 2,
  105 + 1, 1, 0, 0, 1, 1, 1, 1,
  106 + 1, 0, 0, 0, 1, 0, 0, 1,
154 107 },
155   - { /* LD21 TV */
156   - {
157   - 1, 1, 0, 1, 1, 1, 1, 1,
158   - 1, 0, 0, 0, 1, 1, 0, 2,
159   - 1, 1, 0, 0, 1, 1, 1, 1,
160   - 1, 0, 0, 0, 1, 0, 0, 1,
161   - },
162   - { 1, 0, 2, 1, 1, 1, 1, 0,
163   - 1, 0, 0, 1, 0, 1, 0, 0,
164   - 1, 0, 1, 0, 1, 1, 1, 0,
165   - 1, 1, 1, 1, 0, 1, 0, 0,
166   - },
167   - /* No CH2 */
  108 + { 1, 0, 2, 1, 1, 1, 1, 0,
  109 + 1, 0, 0, 1, 0, 1, 0, 0,
  110 + 1, 0, 1, 0, 1, 1, 1, 0,
  111 + 1, 1, 1, 1, 0, 1, 0, 0,
168 112 },
  113 + /* No CH2 */
169 114 };
170 115  
171   -static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
172   - { /* LD20 reference */
173   - {
174   - 3, 3, 3, 2, 3, 2, 0, 2,
175   - 2, 3, 3, 1, 2, 2, 2, 2,
176   - 2, 2, 2, 2, 0, 1, 1, 1,
177   - 2, 2, 2, 2, 3, 0, 2, 2,
178   - },
179   - {
180   - 2, 2, 1, 1, -1, 1, 1, 1,
181   - 2, 0, 2, 2, 2, 1, 0, 2,
182   - 2, 1, 2, 1, 0, 1, 1, 1,
183   - 2, 2, 2, 2, 2, 2, 2, 2,
184   - },
185   - {
186   - 2, 2, 3, 2, 1, 2, 2, 2,
187   - 2, 3, 4, 2, 3, 4, 3, 3,
188   - 2, 2, 1, 2, 1, 1, 1, 1,
189   - 2, 2, 2, 2, 1, 2, 2, 1,
190   - },
  116 +static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = {
  117 + ddrphy_op_dq_shift_val_ld20, /* LD20 reference */
  118 + ddrphy_op_dq_shift_val_ld20, /* LD20 TV */
  119 + ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */
  120 + ddrphy_op_dq_shift_val_ld21, /* LD21 reference */
  121 + ddrphy_op_dq_shift_val_ld21, /* LD21 TV */
  122 +};
  123 +
  124 +static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = {
  125 + {
  126 + 3, 3, 3, 2, 3, 2, 0, 2,
  127 + 2, 3, 3, 1, 2, 2, 2, 2,
  128 + 2, 2, 2, 2, 0, 1, 1, 1,
  129 + 2, 2, 2, 2, 3, 0, 2, 2,
191 130 },
192   - { /* LD20 TV */
193   - {
194   - 3, 3, 3, 2, 3, 2, 0, 2,
195   - 2, 3, 3, 1, 2, 2, 2, 2,
196   - 2, 2, 2, 2, 0, 1, 1, 1,
197   - 2, 2, 2, 2, 3, 0, 2, 2,
198   - },
199   - {
200   - 2, 2, 1, 1, -1, 1, 1, 1,
201   - 2, 0, 2, 2, 2, 1, 0, 2,
202   - 2, 1, 2, 1, 0, 1, 1, 1,
203   - 2, 2, 2, 2, 2, 2, 2, 2,
204   - },
205   - {
206   - 2, 2, 3, 2, 1, 2, 2, 2,
207   - 2, 3, 4, 2, 3, 4, 3, 3,
208   - 2, 2, 1, 2, 1, 1, 1, 1,
209   - 2, 2, 2, 2, 1, 2, 2, 1,
210   - },
  131 + {
  132 + 2, 2, 1, 1, -1, 1, 1, 1,
  133 + 2, 0, 2, 2, 2, 1, 0, 2,
  134 + 2, 1, 2, 1, 0, 1, 1, 1,
  135 + 2, 2, 2, 2, 2, 2, 2, 2,
211 136 },
212   - { /* LD20 TV C1 */
213   - {
214   - 3, 3, 3, 2, 3, 2, 0, 2,
215   - 2, 3, 3, 1, 2, 2, 2, 2,
216   - 2, 2, 2, 2, 0, 1, 1, 1,
217   - 2, 2, 2, 2, 3, 0, 2, 2,
218   - },
219   - {
220   - 2, 2, 1, 1, -1, 1, 1, 1,
221   - 2, 0, 2, 2, 2, 1, 0, 2,
222   - 2, 1, 2, 1, 0, 1, 1, 1,
223   - 2, 2, 2, 2, 2, 2, 2, 2,
224   - },
225   - {
226   - 2, 2, 3, 2, 1, 2, 2, 2,
227   - 2, 3, 4, 2, 3, 4, 3, 3,
228   - 2, 2, 1, 2, 1, 1, 1, 1,
229   - 2, 2, 2, 2, 1, 2, 2, 1,
230   - },
  137 + {
  138 + 2, 2, 3, 2, 1, 2, 2, 2,
  139 + 2, 3, 4, 2, 3, 4, 3, 3,
  140 + 2, 2, 1, 2, 1, 1, 1, 1,
  141 + 2, 2, 2, 2, 1, 2, 2, 1,
231 142 },
232   - { /* LD21 reference */
233   - {
234   - 2, 2, 2, 2, 1, 2, 2, 2,
235   - 2, 3, 3, 2, 2, 2, 2, 2,
236   - 2, 1, 2, 2, 1, 1, 1, 1,
237   - 2, 2, 2, 3, 1, 2, 2, 2,
238   - },
239   - {
240   - 3, 4, 4, 1, 0, 1, 1, 1,
241   - 1, 2, 1, 2, 2, 3, 3, 2,
242   - 1, 0, 2, 1, 1, 0, 1, 0,
243   - 0, 1, 0, 0, 1, 1, 0, 1,
244   - },
245   - /* No CH2 */
  143 +};
  144 +
  145 +static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = {
  146 + {
  147 + 2, 2, 2, 2, 1, 2, 2, 2,
  148 + 2, 3, 3, 2, 2, 2, 2, 2,
  149 + 2, 1, 2, 2, 1, 1, 1, 1,
  150 + 2, 2, 2, 3, 1, 2, 2, 2,
246 151 },
247   - { /* LD21 TV */
248   - {
249   - 2, 2, 2, 2, 1, 2, 2, 2,
250   - 2, 3, 3, 2, 2, 2, 2, 2,
251   - 2, 1, 2, 2, 1, 1, 1, 1,
252   - 2, 2, 2, 3, 1, 2, 2, 2,
253   - },
254   - {
255   - 3, 4, 4, 1, 0, 1, 1, 1,
256   - 1, 2, 1, 2, 2, 3, 3, 2,
257   - 1, 0, 2, 1, 1, 0, 1, 0,
258   - 0, 1, 0, 0, 1, 1, 0, 1,
259   - },
260   - /* No CH2 */
  152 + {
  153 + 3, 4, 4, 1, 0, 1, 1, 1,
  154 + 1, 2, 1, 2, 2, 3, 3, 2,
  155 + 1, 0, 2, 1, 1, 0, 1, 0,
  156 + 0, 1, 0, 0, 1, 1, 0, 1,
261 157 },
  158 + /* No CH2 */
262 159 };
263 160  
264   -/* DDR PHY */
  161 +static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = {
  162 + ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */
  163 + ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */
  164 + ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */
  165 + ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */
  166 + ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */
  167 +};
  168 +
265 169 static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
266 170 unsigned int bit)
267 171 {
... ... @@ -380,7 +284,7 @@
380 284 }
381 285  
382 286 static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
383   - u32 mask, u32 incr, int shift_val)
  287 + u32 mask, u32 incr, short shift_val)
384 288 {
385 289 u32 tmp;
386 290 int val;
... ... @@ -403,7 +307,7 @@
403 307  
404 308 static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
405 309 u32 mask, u32 incr, u32 override,
406   - const int *shift_val_array)
  310 + const short *shift_val_array)
407 311 {
408 312 u32 tmp;
409 313 int dx, bit;