ARM: DTS: stm32: add MMC nodes for stm32f746-disco and stm32f769-disco

Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746 and STM32F769 discovery boards There is a hardware issue on these boards, it misses a pullup on the GPIO line used as card detect to allow correct SD card detection. As workaround, cd-gpios property is not present in DT. So SD card is always considered present in the slot. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>

ARM: DTS: stm32: add MMC nodes for stm32f746-disco and stm32f769-disco
Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746 and STM32F769 discovery boards There is a hardware issue on these boards, it misses a pullup on the GPIO line used as card detect to allow correct SD card detection. As workaround, cd-gpios property is not present in DT. So SD card is always considered present in the slot. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard · Tom Rini
1 parent 45be08822f
Showing 4 changed files with 127 additions and 1 deletions Side-by-side Diff
arch/arm/dts/stm32f746-disco.dts
arch/arm/dts/stm32f746.dtsi
arch/arm/dts/stm32f769-disco.dts
include/dt-bindings/pinctrl/stm32f746-pinfunc.h
@@ -65,6 +65,7 @@
 	aliases {
 		serial0 = &usart1;
 		spi0 = &qspi;
+		mmc0 = &sdio;
 		/* Aliases for gpios so as to use sequence */
 		gpio0 = &gpioa;
 		gpio1 = &gpiob;
@@ -237,5 +238,16 @@
 			memory-map = <0x90000000 0x1000000>;
 			reg = <0>;
 	};
+};
+
+&sdio {
+	status = "okay";
+	cd-gpios = <&gpioc 13 0>;
+	cd-inverted;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_pins_od>;
+	bus-width = <4>;
+	max-frequency = <25000000>;
 };
@@ -234,6 +234,91 @@
 				u-boot,dm-pre-reloc;
 			};
  
+			sdio_pins: sdio_pins@0 {
+				pins {
+					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
+						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
+						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
+						 <STM32F746_PC12_FUNC_SDMMC1_CK>,
+						 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od: sdio_pins_od@0 {
+				pins1 {
+					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
+						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
+						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
+						 <STM32F746_PC12_FUNC_SDMMC1_CK>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_b: sdio_pins_b@0 {
+				pins {
+					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
+						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
+						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
+						 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
+						 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od_b: sdio_pins_od_b@0 {
+				pins1 {
+					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
+						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
+						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
+						 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+
+		};
+		sdio: sdio@40012c00 {
+			compatible = "st,stm32f4xx-sdio";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc 0 171>;
+			interrupts = <49>;
+			status = "disabled";
+			pinctrl-0 = <&sdio_pins>;
+			pinctrl-1 = <&sdio_pins_od>;
+			pinctrl-names = "default", "opendrain";
+			max-frequency = <48000000>;
+		};
+
+		sdio2: sdio2@40011c00 {
+			compatible = "st,stm32f4xx-sdio";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc 0 167>;
+			interrupts = <103>;
+			status = "disabled";
+			pinctrl-0 = <&sdio_pins_b>;
+			pinctrl-1 = <&sdio_pins_od_b>;
+			pinctrl-names = "default", "opendrain";
+			max-frequency = <48000000>;
 		};
 	};
 };
@@ -60,6 +60,7 @@
 	aliases {
 		serial0 = &usart1;
 		spi0 = &qspi;
+		mmc0 = &sdio2;
 		/* Aliases for gpios so as to use sequence */
 		gpio0 = &gpioa;
 		gpio1 = &gpiob;
@@ -251,5 +252,16 @@
 			memory-map = <0x90000000 0x1000000>;
 			reg = <0>;
 	};
+};
+
+&sdio2 {
+	status = "okay";
+	cd-gpios = <&gpioi 15 0>;
+	cd-inverted;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins_b>;
+	pinctrl-1 = <&sdio_pins_od_b>;
+	bus-width = <4>;
+	max-frequency = <25000000>;
 };
@@ -154,7 +154,6 @@
 #define STM32F746_PA15_FUNC_EVENTOUT 0xf10
 #define STM32F746_PA15_FUNC_ANALOG 0xf11
  
-
 #define STM32F746_PB0_FUNC_GPIO 0x1000
 #define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
 #define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
@@ -188,6 +187,9 @@
 #define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
 #define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
 #define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+
+#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b
+
 #define STM32F746_PB3_FUNC_EVENTOUT 0x1310
 #define STM32F746_PB3_FUNC_ANALOG 0x1311
  
@@ -197,6 +199,9 @@
 #define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
 #define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
 #define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
+
+#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b
+
 #define STM32F746_PB4_FUNC_EVENTOUT 0x1410
 #define STM32F746_PB4_FUNC_ANALOG 0x1411
  
@@ -505,6 +510,9 @@
 #define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
 #define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
 #define STM32F746_PD6_FUNC_USART2_RX 0x3608
+
+#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c
+
 #define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
 #define STM32F746_PD6_FUNC_DCMI_D10 0x360e
 #define STM32F746_PD6_FUNC_LCD_B2 0x360f
@@ -514,6 +522,9 @@
 #define STM32F746_PD7_FUNC_GPIO 0x3700
 #define STM32F746_PD7_FUNC_USART2_CK 0x3708
 #define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
+
+#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c
+
 #define STM32F746_PD7_FUNC_FMC_NE1 0x370d
 #define STM32F746_PD7_FUNC_EVENTOUT 0x3710
 #define STM32F746_PD7_FUNC_ANALOG 0x3711
@@ -893,6 +904,9 @@
 #define STM32F746_PG9_FUNC_USART6_RX 0x6909
 #define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
 #define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
+
+#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c
+
 #define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
 #define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
 #define STM32F746_PG9_FUNC_EVENTOUT 0x6910
@@ -901,6 +915,9 @@
 #define STM32F746_PG10_FUNC_GPIO 0x6a00
 #define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
 #define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
+
+#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c
+
 #define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
 #define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
 #define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
...	...	@@ -65,6 +65,7 @@
65	65	aliases {
66	66	serial0 = &usart1;
67	67	spi0 = &qspi;
	68	+ mmc0 = &sdio;
68	69	/* Aliases for gpios so as to use sequence */
69	70	gpio0 = &gpioa;
70	71	gpio1 = &gpiob;
...	...	@@ -237,5 +238,16 @@
237	238	memory-map = <0x90000000 0x1000000>;
238	239	reg = <0>;
239	240	};
	241	+};
	242	+
	243	+&sdio {
	244	+ status = "okay";
	245	+ cd-gpios = <&gpioc 13 0>;
	246	+ cd-inverted;
	247	+ pinctrl-names = "default", "opendrain";
	248	+ pinctrl-0 = <&sdio_pins>;
	249	+ pinctrl-1 = <&sdio_pins_od>;
	250	+ bus-width = <4>;
	251	+ max-frequency = <25000000>;
240	252	};
...	...	@@ -234,6 +234,91 @@
234	234	u-boot,dm-pre-reloc;
235	235	};
236	236
	237	+ sdio_pins: sdio_pins@0 {
	238	+ pins {
	239	+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
	240	+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
	241	+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
	242	+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
	243	+ <STM32F746_PC12_FUNC_SDMMC1_CK>,
	244	+ <STM32F746_PD2_FUNC_SDMMC1_CMD>;
	245	+ drive-push-pull;
	246	+ slew-rate = <2>;
	247	+ };
	248	+ };
	249	+
	250	+ sdio_pins_od: sdio_pins_od@0 {
	251	+ pins1 {
	252	+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
	253	+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
	254	+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
	255	+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
	256	+ <STM32F746_PC12_FUNC_SDMMC1_CK>;
	257	+ drive-push-pull;
	258	+ slew-rate = <2>;
	259	+ };
	260	+
	261	+ pins2 {
	262	+ pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
	263	+ drive-open-drain;
	264	+ slew-rate = <2>;
	265	+ };
	266	+ };
	267	+
	268	+ sdio_pins_b: sdio_pins_b@0 {
	269	+ pins {
	270	+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
	271	+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
	272	+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
	273	+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
	274	+ <STM32F769_PD6_FUNC_SDMMC2_CLK>,
	275	+ <STM32F769_PD7_FUNC_SDMMC2_CMD>;
	276	+ drive-push-pull;
	277	+ slew-rate = <2>;
	278	+ };
	279	+ };
	280	+
	281	+ sdio_pins_od_b: sdio_pins_od_b@0 {
	282	+ pins1 {
	283	+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
	284	+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
	285	+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
	286	+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
	287	+ <STM32F769_PD6_FUNC_SDMMC2_CLK>;
	288	+ drive-push-pull;
	289	+ slew-rate = <2>;
	290	+ };
	291	+
	292	+ pins2 {
	293	+ pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
	294	+ drive-open-drain;
	295	+ slew-rate = <2>;
	296	+ };
	297	+ };
	298	+
	299	+ };
	300	+ sdio: sdio@40012c00 {
	301	+ compatible = "st,stm32f4xx-sdio";
	302	+ reg = <0x40012c00 0x400>;
	303	+ clocks = <&rcc 0 171>;
	304	+ interrupts = <49>;
	305	+ status = "disabled";
	306	+ pinctrl-0 = <&sdio_pins>;
	307	+ pinctrl-1 = <&sdio_pins_od>;
	308	+ pinctrl-names = "default", "opendrain";
	309	+ max-frequency = <48000000>;
	310	+ };
	311	+
	312	+ sdio2: sdio2@40011c00 {
	313	+ compatible = "st,stm32f4xx-sdio";
	314	+ reg = <0x40011c00 0x400>;
	315	+ clocks = <&rcc 0 167>;
	316	+ interrupts = <103>;
	317	+ status = "disabled";
	318	+ pinctrl-0 = <&sdio_pins_b>;
	319	+ pinctrl-1 = <&sdio_pins_od_b>;
	320	+ pinctrl-names = "default", "opendrain";
	321	+ max-frequency = <48000000>;
237	322	};
238	323	};
239	324	};
...	...	@@ -60,6 +60,7 @@
60	60	aliases {
61	61	serial0 = &usart1;
62	62	spi0 = &qspi;
	63	+ mmc0 = &sdio2;
63	64	/* Aliases for gpios so as to use sequence */
64	65	gpio0 = &gpioa;
65	66	gpio1 = &gpiob;
...	...	@@ -251,5 +252,16 @@
251	252	memory-map = <0x90000000 0x1000000>;
252	253	reg = <0>;
253	254	};
	255	+};
	256	+
	257	+&sdio2 {
	258	+ status = "okay";
	259	+ cd-gpios = <&gpioi 15 0>;
	260	+ cd-inverted;
	261	+ pinctrl-names = "default", "opendrain";
	262	+ pinctrl-0 = <&sdio_pins_b>;
	263	+ pinctrl-1 = <&sdio_pins_od_b>;
	264	+ bus-width = <4>;
	265	+ max-frequency = <25000000>;
254	266	};
...	...	@@ -154,7 +154,6 @@
154	154	#define STM32F746_PA15_FUNC_EVENTOUT 0xf10
155	155	#define STM32F746_PA15_FUNC_ANALOG 0xf11
156	156
157		-
158	157	#define STM32F746_PB0_FUNC_GPIO 0x1000
159	158	#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
160	159	#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
...	...	@@ -188,6 +187,9 @@
188	187	#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
189	188	#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
190	189	#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
	190	+
	191	+#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b
	192	+
191	193	#define STM32F746_PB3_FUNC_EVENTOUT 0x1310
192	194	#define STM32F746_PB3_FUNC_ANALOG 0x1311
193	195
...	...	@@ -197,6 +199,9 @@
197	199	#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
198	200	#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
199	201	#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
	202	+
	203	+#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b
	204	+
200	205	#define STM32F746_PB4_FUNC_EVENTOUT 0x1410
201	206	#define STM32F746_PB4_FUNC_ANALOG 0x1411
202	207
...	...	@@ -505,6 +510,9 @@
505	510	#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
506	511	#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
507	512	#define STM32F746_PD6_FUNC_USART2_RX 0x3608
	513	+
	514	+#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c
	515	+
508	516	#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
509	517	#define STM32F746_PD6_FUNC_DCMI_D10 0x360e
510	518	#define STM32F746_PD6_FUNC_LCD_B2 0x360f
...	...	@@ -514,6 +522,9 @@
514	522	#define STM32F746_PD7_FUNC_GPIO 0x3700
515	523	#define STM32F746_PD7_FUNC_USART2_CK 0x3708
516	524	#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
	525	+
	526	+#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c
	527	+
517	528	#define STM32F746_PD7_FUNC_FMC_NE1 0x370d
518	529	#define STM32F746_PD7_FUNC_EVENTOUT 0x3710
519	530	#define STM32F746_PD7_FUNC_ANALOG 0x3711
...	...	@@ -893,6 +904,9 @@
893	904	#define STM32F746_PG9_FUNC_USART6_RX 0x6909
894	905	#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
895	906	#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
	907	+
	908	+#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c
	909	+
896	910	#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
897	911	#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
898	912	#define STM32F746_PG9_FUNC_EVENTOUT 0x6910
...	...	@@ -901,6 +915,9 @@
901	915	#define STM32F746_PG10_FUNC_GPIO 0x6a00
902	916	#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
903	917	#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
	918	+
	919	+#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c
	920	+
904	921	#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
905	922	#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
906	923	#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f