Eric Lee / smarc-uboot

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Commit 779e975117a75e91fcebe226a63104dbfb924ab1

Authored by Stefan Roese
1 parent c5a172a5fd
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Add initial Zeus (PPC405EP) board support 

Signed-off-by: Stefan Roese <sr@denx.de>

Showing 16 changed files with 1344 additions and 44 deletions Side-by-side Diff

... ... @@ -293,6 +293,7 @@
293 293 walnut PPC405GP
294 294 yellowstone PPC440GR
295 295 yosemite PPC440EP
  296 + zeus PPC405EP
296 297  
297 298 P3M750 PPC750FX/GX/GL
298 299  
... ... @@ -91,7 +91,7 @@
91 91 sc3 sequoia sequoia_nand taihu \
92 92 taishan VOH405 VOM405 W7OLMC \
93 93 W7OLMG walnut WUH405 XPEDITE1K \
94   - yellowstone yosemite yucca \
  94 + yellowstone yosemite yucca zeus \
95 95 "
96 96  
97 97 #########################################################################
... ... @@ -1294,6 +1294,9 @@
1294 1294 yucca_config: unconfig
1295 1295 @$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
1296 1296  
  1297 +zeus_config: unconfig
  1298 + @$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
  1299 +
1297 1300 #########################################################################
1298 1301 ## MPC8220 Systems
1299 1302 #########################################################################
board/amcc/bubinga/bubinga.c
Diff comments   View file @ 779e975
... ... @@ -20,11 +20,13 @@
20 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 21 * MA 02111-1307 USA
22 22 */
23   -long int spd_sdram(void);
24 23  
25 24 #include <common.h>
26 25 #include <asm/processor.h>
  26 +#include <asm/io.h>
27 27  
  28 +long int spd_sdram(void);
  29 +
28 30 int board_early_init_f(void)
29 31 {
30 32 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
... ... @@ -33,6 +35,15 @@
33 35 mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
34 36 mtdcr(uictr, 0x00000010); /* set int trigger levels */
35 37 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
  38 +
  39 + /*
  40 + * Configure CPC0_PCI to enable PerWE as output
  41 + * and enable the internal PCI arbiter if selected
  42 + */
  43 + if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
  44 + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
  45 + else
  46 + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
36 47  
37 48 return 0;
38 49 }
board/amcc/taihu/taihu.c
Diff comments   View file @ 779e975
... ... @@ -50,6 +50,12 @@
50 50 mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
51 51 mtebc(pb3cr, CFG_EBC_PB3CR);
52 52  
  53 + /*
  54 + * Configure CPC0_PCI to enable PerWE as output
  55 + * and enable the internal PCI arbiter
  56 + */
  57 + mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
  58 +
53 59 return 0;
54 60 }
55 61  
  1 +#
  2 +# (C) Copyright 2007
  3 +# Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).a
  27 +
  28 +COBJS = $(BOARD).o update.o
  29 +SOBJS =
  30 +
  31 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  32 +OBJS := $(addprefix $(obj),$(COBJS))
  33 +SOBJS := $(addprefix $(obj),$(SOBJS))
  34 +
  35 +$(LIB): $(OBJS) $(SOBJS)
  36 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
  37 +
  38 +clean:
  39 + rm -f $(SOBJS) $(OBJS)
  40 +
  41 +distclean: clean
  42 + rm -f $(LIB) core *.bak .depend
  43 +
  44 +#########################################################################
  45 +
  46 +# defines $(obj).depend target
  47 +include $(SRCTREE)/rules.mk
  48 +
  49 +sinclude $(obj).depend
  50 +
  51 +#########################################################################
board/zeus/config.mk
Diff comments   View file @ 779e975
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +TEXT_BASE = 0xFFFC0000
board/zeus/u-boot.lds
Diff comments   View file @ 779e975
  1 +/*
  2 + * (C) Copyright 2000
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_ARCH(powerpc)
  25 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  26 +/* Do we need any of these for elf?
  27 + __DYNAMIC = 0; */
  28 +SECTIONS
  29 +{
  30 + .resetvec 0xFFFFFFFC :
  31 + {
  32 + *(.resetvec)
  33 + } = 0xffff
  34 +
  35 + /* Read-only sections, merged into text segment: */
  36 + . = + SIZEOF_HEADERS;
  37 + .interp : { *(.interp) }
  38 + .hash : { *(.hash) }
  39 + .dynsym : { *(.dynsym) }
  40 + .dynstr : { *(.dynstr) }
  41 + .rel.text : { *(.rel.text) }
  42 + .rela.text : { *(.rela.text) }
  43 + .rel.data : { *(.rel.data) }
  44 + .rela.data : { *(.rela.data) }
  45 + .rel.rodata : { *(.rel.rodata) }
  46 + .rela.rodata : { *(.rela.rodata) }
  47 + .rel.got : { *(.rel.got) }
  48 + .rela.got : { *(.rela.got) }
  49 + .rel.ctors : { *(.rel.ctors) }
  50 + .rela.ctors : { *(.rela.ctors) }
  51 + .rel.dtors : { *(.rel.dtors) }
  52 + .rela.dtors : { *(.rela.dtors) }
  53 + .rel.bss : { *(.rel.bss) }
  54 + .rela.bss : { *(.rela.bss) }
  55 + .rel.plt : { *(.rel.plt) }
  56 + .rela.plt : { *(.rela.plt) }
  57 + .init : { *(.init) }
  58 + .plt : { *(.plt) }
  59 + .text :
  60 + {
  61 + cpu/ppc4xx/start.o (.text)
  62 +
  63 + *(.text)
  64 + *(.fixup)
  65 + *(.got1)
  66 + }
  67 + _etext = .;
  68 + PROVIDE (etext = .);
  69 + .rodata :
  70 + {
  71 + *(.rodata)
  72 + *(.rodata1)
  73 + *(.rodata.str1.4)
  74 + }
  75 + .fini : { *(.fini) } =0
  76 + .ctors : { *(.ctors) }
  77 + .dtors : { *(.dtors) }
  78 +
  79 + /* Read-write section, merged into data segment: */
  80 + . = (. + 0x00FF) & 0xFFFFFF00;
  81 + _erotext = .;
  82 + PROVIDE (erotext = .);
  83 + .reloc :
  84 + {
  85 + *(.got)
  86 + _GOT2_TABLE_ = .;
  87 + *(.got2)
  88 + _FIXUP_TABLE_ = .;
  89 + *(.fixup)
  90 + }
  91 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  92 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  93 +
  94 + .data :
  95 + {
  96 + *(.data)
  97 + *(.data1)
  98 + *(.sdata)
  99 + *(.sdata2)
  100 + *(.dynamic)
  101 + CONSTRUCTORS
  102 + }
  103 + _edata = .;
  104 + PROVIDE (edata = .);
  105 +
  106 + . = .;
  107 + __u_boot_cmd_start = .;
  108 + .u_boot_cmd : { *(.u_boot_cmd) }
  109 + __u_boot_cmd_end = .;
  110 +
  111 + . = .;
  112 + __start___ex_table = .;
  113 + __ex_table : { *(__ex_table) }
  114 + __stop___ex_table = .;
  115 +
  116 + . = ALIGN(256);
  117 + __init_begin = .;
  118 + .text.init : { *(.text.init) }
  119 + .data.init : { *(.data.init) }
  120 + . = ALIGN(256);
  121 + __init_end = .;
  122 +
  123 + __bss_start = .;
  124 + .bss :
  125 + {
  126 + *(.sbss) *(.scommon)
  127 + *(.dynbss)
  128 + *(.bss)
  129 + *(COMMON)
  130 + }
  131 + _end = . ;
  132 + PROVIDE (end = .);
  133 +}
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <config.h>
  25 +#include <common.h>
  26 +#include <command.h>
  27 +#include <asm/processor.h>
  28 +#include <asm/io.h>
  29 +#include <asm/gpio.h>
  30 +#include <i2c.h>
  31 +
  32 +#if defined(CONFIG_ZEUS)
  33 +
  34 +u8 buf_zeus_ce[] = {
  35 +/*00 01 02 03 04 05 06 07 */
  36 + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  37 +/*08 09 0a 0b 0c 0d 0e 0f */
  38 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  39 +/*10 11 12 13 14 15 16 17 */
  40 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  41 +/*18 19 1a 1b 1c 1d 1e 1f */
  42 + 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
  43 +
  44 +u8 buf_zeus_pe[] = {
  45 +
  46 +/* CPU_CLOCK_DIV 1 = 00
  47 + CPU_PLB_FREQ_DIV 3 = 10
  48 + OPB_PLB_FREQ_DIV 2 = 01
  49 + EBC_PLB_FREQ_DIV 2 = 00
  50 + MAL_PLB_FREQ_DIV 1 = 00
  51 + PCI_PLB_FRQ_DIV 3 = 10
  52 + PLL_PLLOUTA = IS SET
  53 + PLL_OPERATING = IS NOT SET
  54 + PLL_FDB_MUL 10 = 1010
  55 + PLL_FWD_DIV_A 3 = 101
  56 + PLL_FWD_DIV_B 3 = 101
  57 + TUNE = 0x2be */
  58 +/*00 01 02 03 04 05 06 07 */
  59 + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  60 +/*08 09 0a 0b 0c 0d 0e 0f */
  61 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  62 +/*10 11 12 13 14 15 16 17 */
  63 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  64 +/*18 19 1a 1b 1c 1d 1e 1f */
  65 + 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
  66 +
  67 +static int update_boot_eeprom(void)
  68 +{
  69 + u32 len = 0x20;
  70 + u8 chip = CFG_I2C_EEPROM_ADDR;
  71 + u8 *pbuf;
  72 + u8 base;
  73 + int i;
  74 +
  75 + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
  76 + pbuf = buf_zeus_pe;
  77 + base = 0x40;
  78 + } else {
  79 + pbuf = buf_zeus_ce;
  80 + base = 0x00;
  81 + }
  82 +
  83 + for (i = 0; i < len; i++, base++) {
  84 + if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
  85 + printf("i2c_write fail\n");
  86 + return 1;
  87 + }
  88 + udelay(11000);
  89 + }
  90 +
  91 + return 0;
  92 +}
  93 +
  94 +int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
  95 +{
  96 + return update_boot_eeprom();
  97 +}
  98 +
  99 +U_BOOT_CMD (
  100 + update_boot_eeprom, 1, 1, do_update_boot_eeprom,
  101 + "update_boot_eeprom - update boot eeprom content\n",
  102 + NULL
  103 +);
  104 +
  105 +#endif
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <malloc.h>
  27 +#include <environment.h>
  28 +#include <logbuff.h>
  29 +#include <post.h>
  30 +
  31 +#include <asm/processor.h>
  32 +#include <asm/io.h>
  33 +#include <asm/gpio.h>
  34 +
  35 +DECLARE_GLOBAL_DATA_PTR;
  36 +
  37 +#define REBOOT_MAGIC 0x07081967
  38 +#define REBOOT_NOP 0x00000000
  39 +#define REBOOT_DO_POST 0x00000001
  40 +
  41 +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  42 +extern env_t *env_ptr;
  43 +extern uchar default_environment[];
  44 +
  45 +ulong flash_get_size(ulong base, int banknum);
  46 +void env_crc_update(void);
  47 +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  48 +
  49 +static u32 start_time;
  50 +
  51 +int board_early_init_f(void)
  52 +{
  53 + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
  54 + mtdcr(uicer, 0x00000000); /* disable all ints */
  55 + mtdcr(uiccr, 0x00000000);
  56 + mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
  57 + mtdcr(uictr, 0x00000000); /* set int trigger levels */
  58 + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
  59 + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  60 +
  61 + /*
  62 + * Configure CPC0_PCI to enable PerWE as output
  63 + */
  64 + mtdcr(cpc0_pci, CPC0_PCI_SPE);
  65 +
  66 + return 0;
  67 +}
  68 +
  69 +int misc_init_r(void)
  70 +{
  71 + u32 pbcr;
  72 + int size_val = 0;
  73 + u32 post_magic;
  74 + u32 post_val;
  75 +
  76 + post_magic = in_be32((void *)CFG_POST_MAGIC);
  77 + post_val = in_be32((void *)CFG_POST_VAL);
  78 + if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
  79 + /*
  80 + * Set special bootline bootparameter to pass this POST boot
  81 + * mode to Linux to reset the username/password
  82 + */
  83 + setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
  84 +
  85 + /*
  86 + * Normally don't run POST tests, only when enabled
  87 + * via the sw-reset button. So disable further tests
  88 + * upon next bootup here.
  89 + */
  90 + out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
  91 + } else {
  92 + /*
  93 + * Only run POST when initiated via the sw-reset button mechanism
  94 + */
  95 + post_word_store(0);
  96 + }
  97 +
  98 + /*
  99 + * Get current time
  100 + */
  101 + start_time = get_timer(0);
  102 +
  103 + /*
  104 + * FLASH stuff...
  105 + */
  106 +
  107 + /* Re-do sizing to get full correct info */
  108 +
  109 + /* adjust flash start and offset */
  110 + mfebc(pb0cr, pbcr);
  111 + switch (gd->bd->bi_flashsize) {
  112 + case 1 << 20:
  113 + size_val = 0;
  114 + break;
  115 + case 2 << 20:
  116 + size_val = 1;
  117 + break;
  118 + case 4 << 20:
  119 + size_val = 2;
  120 + break;
  121 + case 8 << 20:
  122 + size_val = 3;
  123 + break;
  124 + case 16 << 20:
  125 + size_val = 4;
  126 + break;
  127 + case 32 << 20:
  128 + size_val = 5;
  129 + break;
  130 + case 64 << 20:
  131 + size_val = 6;
  132 + break;
  133 + case 128 << 20:
  134 + size_val = 7;
  135 + break;
  136 + }
  137 + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
  138 + mtebc(pb0cr, pbcr);
  139 +
  140 + /*
  141 + * Re-check to get correct base address
  142 + */
  143 + flash_get_size(gd->bd->bi_flashstart, 0);
  144 +
  145 + /* Monitor protection ON by default */
  146 + (void)flash_protect(FLAG_PROTECT_SET,
  147 + -CFG_MONITOR_LEN,
  148 + 0xffffffff,
  149 + &flash_info[0]);
  150 +
  151 + /* Env protection ON by default */
  152 + (void)flash_protect(FLAG_PROTECT_SET,
  153 + CFG_ENV_ADDR_REDUND,
  154 + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
  155 + &flash_info[0]);
  156 +
  157 + return 0;
  158 +}
  159 +
  160 +/*
  161 + * Check Board Identity:
  162 + */
  163 +int checkboard(void)
  164 +{
  165 + char *s = getenv("serial#");
  166 +
  167 + puts("Board: Zeus-");
  168 +
  169 + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
  170 + puts("PE");
  171 + else
  172 + puts("CE");
  173 +
  174 + puts(" of BulletEndPoint");
  175 +
  176 + if (s != NULL) {
  177 + puts(", serial# ");
  178 + puts(s);
  179 + }
  180 + putc('\n');
  181 +
  182 + /* both LED's off */
  183 + gpio_write_bit(CFG_GPIO_LED_RED, 0);
  184 + gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
  185 + udelay(10000);
  186 + /* and on again */
  187 + gpio_write_bit(CFG_GPIO_LED_RED, 1);
  188 + gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
  189 +
  190 + return (0);
  191 +}
  192 +
  193 +static u32 detect_sdram_size(void)
  194 +{
  195 + u32 val;
  196 + u32 size;
  197 +
  198 + mfsdram(mem_mb0cf, val);
  199 + size = (4 << 20) << ((val & 0x000e0000) >> 17);
  200 +
  201 + /*
  202 + * Check if 2nd bank is enabled too
  203 + */
  204 + mfsdram(mem_mb1cf, val);
  205 + if (val & 1)
  206 + size += (4 << 20) << ((val & 0x000e0000) >> 17);
  207 +
  208 + return size;
  209 +}
  210 +
  211 +long int initdram (int board_type)
  212 +{
  213 + return detect_sdram_size();
  214 +}
  215 +
  216 +#if defined(CFG_DRAM_TEST)
  217 +int testdram(void)
  218 +{
  219 + unsigned long *mem = (unsigned long *)0;
  220 + const unsigned long kend = (1024 / sizeof(unsigned long));
  221 + unsigned long k, n;
  222 + unsigned long msr;
  223 + unsigned long total_kbytes;
  224 +
  225 + total_kbytes = detect_sdram_size();
  226 +
  227 + msr = mfmsr();
  228 + mtmsr(msr & ~(MSR_EE));
  229 +
  230 + for (k = 0; k < total_kbytes ;
  231 + ++k, mem += (1024 / sizeof(unsigned long))) {
  232 + if ((k & 1023) == 0) {
  233 + printf("%3d MB\r", k / 1024);
  234 + }
  235 +
  236 + memset(mem, 0xaaaaaaaa, 1024);
  237 + for (n = 0; n < kend; ++n) {
  238 + if (mem[n] != 0xaaaaaaaa) {
  239 + printf("SDRAM test fails at: %08x\n",
  240 + (uint) & mem[n]);
  241 + return 1;
  242 + }
  243 + }
  244 +
  245 + memset(mem, 0x55555555, 1024);
  246 + for (n = 0; n < kend; ++n) {
  247 + if (mem[n] != 0x55555555) {
  248 + printf("SDRAM test fails at: %08x\n",
  249 + (uint) & mem[n]);
  250 + return 1;
  251 + }
  252 + }
  253 + }
  254 + printf("SDRAM test passes\n");
  255 + mtmsr(msr);
  256 +
  257 + return 0;
  258 +}
  259 +#endif
  260 +
  261 +static int default_env_var(char *buf, char *var)
  262 +{
  263 + char *ptr;
  264 + char *val;
  265 +
  266 + /*
  267 + * Find env variable
  268 + */
  269 + ptr = strstr(buf + 4, var);
  270 + if (ptr == NULL) {
  271 + printf("ERROR: %s not found!\n", var);
  272 + return -1;
  273 + }
  274 + ptr += strlen(var) + 1;
  275 +
  276 + /*
  277 + * Now the ethaddr needs to be updated in the "normal"
  278 + * environment storage -> redundant flash.
  279 + */
  280 + val = ptr;
  281 + setenv(var, val);
  282 + printf("Updated %s from eeprom to %s!\n", var, val);
  283 +
  284 + return 0;
  285 +}
  286 +
  287 +static int restore_default(void)
  288 +{
  289 + char *buf;
  290 + char *buf_save;
  291 + u32 crc;
  292 +
  293 + /*
  294 + * Unprotect and erase environment area
  295 + */
  296 + flash_protect(FLAG_PROTECT_CLEAR,
  297 + CFG_ENV_ADDR_REDUND,
  298 + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
  299 + &flash_info[0]);
  300 +
  301 + flash_sect_erase(CFG_ENV_ADDR_REDUND,
  302 + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1);
  303 +
  304 + /*
  305 + * Now restore default environment from U-Boot image
  306 + * -> ipaddr, serverip...
  307 + */
  308 + memset(env_ptr, 0, sizeof(env_t));
  309 + memcpy(env_ptr->data, default_environment, ENV_SIZE);
  310 +#ifdef CFG_REDUNDAND_ENVIRONMENT
  311 + env_ptr->flags = 0xFF;
  312 +#endif
  313 + env_crc_update();
  314 + gd->env_valid = 1;
  315 +
  316 + /*
  317 + * Read board specific values from I2C EEPROM
  318 + * and set env variables accordingly
  319 + * -> ethaddr, eth1addr, serial#
  320 + */
  321 + buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
  322 + if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
  323 + (u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
  324 + puts("\nError reading EEPROM!\n");
  325 + } else {
  326 + crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
  327 + if (crc != *(u32 *)buf) {
  328 + printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf);
  329 + return -1;
  330 + }
  331 +
  332 + default_env_var(buf, "ethaddr");
  333 + buf += 8 + 18;
  334 + default_env_var(buf, "eth1addr");
  335 + buf += 9 + 18;
  336 + default_env_var(buf, "serial#");
  337 + }
  338 +
  339 + /*
  340 + * Finally save updated env variables back to flash
  341 + */
  342 + saveenv();
  343 +
  344 + free(buf_save);
  345 +
  346 + return 0;
  347 +}
  348 +
  349 +int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  350 +{
  351 + char *buf;
  352 + char *buf_save;
  353 + char str[32];
  354 + u32 crc;
  355 + char var[32];
  356 +
  357 + if (argc < 4) {
  358 + puts("ERROR!\n");
  359 + return -1;
  360 + }
  361 +
  362 + buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
  363 + memset(buf, 0, FACTORY_RESET_ENV_SIZE);
  364 +
  365 + strcpy(var, "ethaddr");
  366 + printf("Setting %s to %s\n", var, argv[1]);
  367 + sprintf(str, "%s=%s", var, argv[1]);
  368 + strcpy(buf + 4, str);
  369 + buf += strlen(str) + 1;
  370 +
  371 + strcpy(var, "eth1addr");
  372 + printf("Setting %s to %s\n", var, argv[2]);
  373 + sprintf(str, "%s=%s", var, argv[2]);
  374 + strcpy(buf + 4, str);
  375 + buf += strlen(str) + 1;
  376 +
  377 + strcpy(var, "serial#");
  378 + printf("Setting %s to %s\n", var, argv[3]);
  379 + sprintf(str, "%s=%s", var, argv[3]);
  380 + strcpy(buf + 4, str);
  381 +
  382 + crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
  383 + *(u32 *)buf_save = crc;
  384 +
  385 + if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
  386 + (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
  387 + puts("\nError writing EEPROM!\n");
  388 + return -1;
  389 + }
  390 +
  391 + free(buf_save);
  392 +
  393 + return 0;
  394 +}
  395 +
  396 +U_BOOT_CMD(
  397 + setdef, 4, 1, do_set_default,
  398 + "setdef - write board-specific values to EEPROM (ethaddr...)\n",
  399 + "ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
  400 + );
  401 +
  402 +static inline int sw_reset_pressed(void)
  403 +{
  404 + return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
  405 +}
  406 +
  407 +int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
  408 +{
  409 + int delta;
  410 + int count = 0;
  411 + int post = 0;
  412 + int factory_reset = 0;
  413 +
  414 + if (!sw_reset_pressed()) {
  415 + printf("SW-Reset already high (Button released)\n");
  416 + printf("-> No action taken!\n");
  417 + return 0;
  418 + }
  419 +
  420 + printf("Waiting for SW-Reset button to be released.");
  421 +
  422 + while (1) {
  423 + delta = get_timer(start_time);
  424 + if (!sw_reset_pressed())
  425 + break;
  426 +
  427 + if ((delta > CFG_TIME_POST) && !post) {
  428 + printf("\nWhen released now, POST tests will be started.");
  429 + gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
  430 + post = 1;
  431 + }
  432 +
  433 + if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
  434 + printf("\nWhen released now, factory default values"
  435 + " will be restored.");
  436 + gpio_write_bit(CFG_GPIO_LED_RED, 0);
  437 + factory_reset = 1;
  438 + }
  439 +
  440 + udelay(1000);
  441 + if (!(count++ % 1000))
  442 + printf(".");
  443 + }
  444 +
  445 +
  446 + printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
  447 +
  448 + if (delta > CFG_TIME_FACTORY_RESET) {
  449 + printf("Starting factory reset value restoration...\n");
  450 +
  451 + /*
  452 + * Restore default setting
  453 + */
  454 + restore_default();
  455 +
  456 + /*
  457 + * Reset the board for default to become valid
  458 + */
  459 + do_reset(NULL, 0, 0, NULL);
  460 +
  461 + return 0;
  462 + }
  463 +
  464 + if (delta > CFG_TIME_POST) {
  465 + printf("Starting POST configuration...\n");
  466 +
  467 + /*
  468 + * Enable POST upon next bootup
  469 + */
  470 + out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
  471 + out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
  472 + post_bootmode_init();
  473 +
  474 + /*
  475 + * Reset the logbuffer for a clean start
  476 + */
  477 + logbuff_reset();
  478 +
  479 + do_reset(NULL, 0, 0, NULL);
  480 +
  481 + return 0;
  482 + }
  483 +
  484 + return 0;
  485 +}
  486 +
  487 +U_BOOT_CMD (
  488 + chkreset, 1, 1, do_chkreset,
  489 + "chkreset- Check for status of SW-reset button and act accordingly\n",
  490 + NULL
  491 +);
  492 +
  493 +#if defined(CONFIG_POST)
  494 +/*
  495 + * Returns 1 if keys pressed to start the power-on long-running tests
  496 + * Called from board_init_f().
  497 + */
  498 +int post_hotkeys_pressed(void)
  499 +{
  500 + u32 post_magic;
  501 + u32 post_val;
  502 +
  503 + post_magic = in_be32((void *)CFG_POST_MAGIC);
  504 + post_val = in_be32((void *)CFG_POST_VAL);
  505 +
  506 + if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
  507 + return 1;
  508 + else
  509 + return 0;
  510 +}
  511 +#endif /* CONFIG_POST */
... ... @@ -187,14 +187,14 @@
187 187 /*
188 188 * Disable memory controller.
189 189 */
190   - mtsdram0(mem_mcopt1, 0x00000000);
  190 + mtsdram(mem_mcopt1, 0x00000000);
191 191  
192 192 /*
193 193 * Set MB0CF for bank 0.
194 194 */
195   - mtsdram0(mem_mb0cf, mb0cf[i].reg);
196   - mtsdram0(mem_sdtr1, sdtr1);
197   - mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
  195 + mtsdram(mem_mb0cf, mb0cf[i].reg);
  196 + mtsdram(mem_sdtr1, sdtr1);
  197 + mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
198 198  
199 199 udelay(200);
200 200  
... ... @@ -203,7 +203,7 @@
203 203 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
204 204 * read/prefetch.
205 205 */
206   - mtsdram0(mem_mcopt1, 0x80800000);
  206 + mtsdram(mem_mcopt1, 0x80800000);
207 207  
208 208 udelay(10000);
209 209  
210 210  
... ... @@ -215,10 +215,21 @@
215 215 #ifdef CONFIG_SDRAM_BANK1
216 216 u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
217 217  
218   - mtsdram0(mem_mcopt1, 0x00000000);
219   - mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
220   - mtsdram0(mem_mcopt1, 0x80800000);
  218 + mtsdram(mem_mcopt1, 0x00000000);
  219 + mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
  220 + mtsdram(mem_mcopt1, 0x80800000);
221 221 udelay(10000);
  222 +
  223 + /*
  224 + * Check if 2nd bank is really available.
  225 + * If the size not equal to the size of the first
  226 + * bank, then disable the 2nd bank completely.
  227 + */
  228 + if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
  229 + mb0cf[i].size) {
  230 + mtsdram(mem_mb1cf, 0);
  231 + mtsdram(mem_mcopt1, 0);
  232 + }
222 233 #endif
223 234 return;
224 235 }
... ... @@ -29,8 +29,6 @@
29 29  
30 30 #include <config.h>
31 31  
32   -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
33   -
34 32 #define ONE_BILLION 1000000000
35 33  
36 34 struct sdram_conf_s {
... ... @@ -1869,40 +1869,9 @@
1869 1869 ori r3,r3,CFG_EBC_PB4CR@l
1870 1870 mtdcr ebccfgd,r3
1871 1871 #endif
1872   -#ifdef CONFIG_TAIHU
1873   - mfdcr r4, CPC0_BOOT
1874   - andi. r5, r4, CPC0_BOOT_SEP@l
1875   - bne strap_0 /* serial eeprom present */
1876   -#endif
1877 1872  
1878   -#ifndef CFG_CPC0_PCI
1879   - li r3,CPC0_PCI_HOST_CFG_EN
1880   -#ifdef CONFIG_BUBINGA
1881 1873 /*
1882 1874 !-----------------------------------------------------------------------
1883   - ! Check FPGA for PCI internal/external arbitration
1884   - ! If board is set to internal arbitration, update cpc0_pci
1885   - !-----------------------------------------------------------------------
1886   - */
1887   - addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1888   - ori r5,r5,FPGA_REG1@l
1889   - lbz r5,0x0(r5) /* read to get PCI arb selection */
1890   - andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1891   - beq ..pci_cfg_set /* if not set, then bypass reg write*/
1892   -#endif
1893   - ori r3,r3,CPC0_PCI_ARBIT_EN
1894   -#ifdef CONFIG_TAIHU
1895   - ori r3,r3,CPC0_PCI_SPE
1896   -#endif
1897   -#else /* CFG_CPC0_PCI */
1898   - li r3,CFG_CPC0_PCI
1899   -#endif /* CFG_CPC0_PCI */
1900   -..pci_cfg_set:
1901   - mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1902   -
1903   -strap_0:
1904   - /*
1905   - !-----------------------------------------------------------------------
1906 1875 ! Check to see if chip is in bypass mode.
1907 1876 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1908 1877 ! CPU reset Otherwise, skip this step and keep going.
... ... @@ -1966,6 +1935,21 @@
1966 1935 bne _pci_66mhz
1967 1936 #endif /* CONFIG_TAIHU */
1968 1937  
  1938 +#if defined(CONFIG_ZEUS)
  1939 + mfdcr r4, CPC0_BOOT
  1940 + andi. r5, r4, CPC0_BOOT_SEP@l
  1941 + bne strap_1 /* serial eeprom present */
  1942 + lis r3,0x0000
  1943 + addi r3,r3,0x3030
  1944 + lis r4,0x8042
  1945 + addi r4,r4,0x223e
  1946 + b 1f
  1947 +strap_1:
  1948 + mfdcr r3, CPC0_PLLMR0
  1949 + mfdcr r4, CPC0_PLLMR1
  1950 + b 1f
  1951 +#endif
  1952 +
1969 1953 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1970 1954 ori r3,r3,PLLMR0_DEFAULT@l /* */
1971 1955 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1972 1956  
... ... @@ -1982,9 +1966,9 @@
1982 1966 strap_1:
1983 1967 mfdcr r3, CPC0_PLLMR0
1984 1968 mfdcr r4, CPC0_PLLMR1
1985   -1:
1986 1969 #endif /* CONFIG_TAIHU */
1987 1970  
  1971 +1:
1988 1972 b pll_write /* Write the CPC0_PLLMR with new value */
1989 1973  
1990 1974 pll_done:
  1 +
  2 +Storage of the board specific values (ethaddr...)
  3 +-------------------------------------------------
  4 +
  5 +The board specific environment variables that should be unique
  6 +for each individual board, can be stored in the I2C EEPROM. This
  7 +will be done from offset 0x80 with the length of 0x80 bytes. The
  8 +following command can be used to store the values here:
  9 +
  10 +=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
  11 +
  12 + ethaddr eth1addr serial#
  13 +
  14 +Now those 3 values are stored into the I2C EEPROM. A CRC is added
  15 +to make sure that the values get not corrupted.
  16 +
  17 +
  18 +SW-Reset Pushbutton handling:
  19 +-----------------------------
  20 +
  21 +The SW-reset push button is connected to a GPIO input too. This
  22 +way U-Boot can "see" how long the SW-reset was pressed, and a
  23 +specific action can be taken. Two different actions are supported:
  24 +
  25 +a) Release after more than 5 seconds and less then 10 seconds:
  26 + -> Run POST
  27 +
  28 + Please note, that the POST test will take a while (approx. 1 min
  29 + on the 128MByte board). This is mainly due to the system memory
  30 + test.
  31 +
  32 +b) Release after more than 10 seconds:
  33 + -> Restore factory default settings
  34 +
  35 + The factory default values are restored. The default environment
  36 + variables are restored (ipaddr, serverip...) and the board
  37 + specific values (ethaddr, eth1addr and serial#) are restored
  38 + to the environment from the I2C EEPROM. Also a bootline parameter
  39 + is added to the Linux bootline to signal the Linux kernel upon
  40 + the next startup, that the factory defaults should be restored.
  41 +
  42 +The command to check this sw-reset status and act accordingly is
  43 +
  44 +=> chkreset
  45 +
  46 +This command is added to the default "bootcmd", so that it is called
  47 +automatically upon startup.
  48 +
  49 +Also, the 2 LED's are used to indicate the current status of this
  50 +command (time passed since pushing the button). When the POST test
  51 +will be run, the green LED will be switched off, and when the
  52 +factory restore will be initiated, the reg LED will be switched off.
  53 +
  54 +
  55 +Loggin of POST results:
  56 +-----------------------
  57 +
  58 +The results of the POST tests are logged in a logbuffer located at the end
  59 +of the onboard memory. It can be accessed with the U-Boot command "log":
  60 +
  61 +=> log show
  62 +<4>POST memory PASSED
  63 +<4>POST cache PASSED
  64 +<4>POST cpu PASSED
  65 +<4>POST uart PASSED
  66 +<4>POST ethernet PASSED
  67 +
  68 +The DENX Linux kernel tree has support for this log buffer included. Exactly
  69 +this buffer is used for logging of all kernel messages too. By enabling the
  70 +compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
  71 +can access the U-Boot log messages from Linux too.
  72 +
  73 +2007-08-10, Stefan Roese <sr@denx.de>
include/configs/zeus.h
Diff comments   View file @ 779e975
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/************************************************************************
  25 + * zeus.h - configuration for Zeus board
  26 + ***********************************************************************/
  27 +#ifndef __CONFIG_H
  28 +#define __CONFIG_H
  29 +
  30 +/*-----------------------------------------------------------------------
  31 + * High Level Configuration Options
  32 + *----------------------------------------------------------------------*/
  33 +#define CONFIG_ZEUS 1 /* Board is Zeus */
  34 +#define CONFIG_4xx 1 /* ... PPC4xx family */
  35 +#define CONFIG_405EP 1 /* Specifc 405EP support*/
  36 +
  37 +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  38 +
  39 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  40 +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  41 +
  42 +#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
  43 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
  44 +
  45 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  46 +
  47 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  48 +
  49 +#define CONFIG_MII 1 /* MII PHY management */
  50 +#define CONFIG_PHY_ADDR 0x01 /* PHY address */
  51 +#define CONFIG_HAS_ETH1 1
  52 +#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
  53 +#define CONFIG_NET_MULTI 1
  54 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
  55 +#define CONFIG_PHY_RESET 1
  56 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
  57 +
  58 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  59 + CFG_CMD_ASKENV | \
  60 + CFG_CMD_CACHE | \
  61 + CFG_CMD_DHCP | \
  62 + CFG_CMD_DIAG | \
  63 + CFG_CMD_EEPROM | \
  64 + CFG_CMD_ELF | \
  65 + CFG_CMD_I2C | \
  66 + CFG_CMD_IRQ | \
  67 + CFG_CMD_LOG | \
  68 + CFG_CMD_MII | \
  69 + CFG_CMD_NET | \
  70 + CFG_CMD_NFS | \
  71 + CFG_CMD_PING | \
  72 + CFG_CMD_REGINFO)
  73 +
  74 +/* POST support */
  75 +#define CONFIG_POST (CFG_POST_MEMORY | \
  76 + CFG_POST_CPU | \
  77 + CFG_POST_CACHE | \
  78 + CFG_POST_UART | \
  79 + CFG_POST_ETHER)
  80 +
  81 +#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
  82 +
  83 +/* Define here the base-addresses of the UARTs to test in POST */
  84 +#define CFG_POST_UART_TABLE {UART0_BASE}
  85 +
  86 +#define CONFIG_LOGBUFFER
  87 +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
  88 +
  89 +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
  90 +
  91 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  92 +#include <cmd_confdefs.h>
  93 +
  94 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  95 +
  96 +/*-----------------------------------------------------------------------
  97 + * SDRAM
  98 + *----------------------------------------------------------------------*/
  99 +/*
  100 + * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  101 + */
  102 +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  103 +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
  104 +
  105 +/* SDRAM timings used in datasheet */
  106 +#define CFG_SDRAM_CL 3 /* CAS latency */
  107 +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
  108 +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
  109 +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
  110 +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
  111 +
  112 +/*-----------------------------------------------------------------------
  113 + * Serial Port
  114 + *----------------------------------------------------------------------*/
  115 +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
  116 +#define CFG_BASE_BAUD 691200
  117 +#define CONFIG_BAUDRATE 115200
  118 +#define CONFIG_SERIAL_MULTI
  119 +
  120 +/* The following table includes the supported baudrates */
  121 +#define CFG_BAUDRATE_TABLE \
  122 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  123 +
  124 +/*-----------------------------------------------------------------------
  125 + * Miscellaneous configurable options
  126 + *----------------------------------------------------------------------*/
  127 +#define CFG_LONGHELP /* undef to save memory */
  128 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  129 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  130 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  131 +#else
  132 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  133 +#endif
  134 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  135 +#define CFG_MAXARGS 16 /* max number of command args */
  136 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  137 +
  138 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  139 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  140 +
  141 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  142 +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  143 +
  144 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  145 +
  146 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  147 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  148 +
  149 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  150 +#define CONFIG_LOOPW 1 /* enable loopw command */
  151 +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  152 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  153 +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  154 +
  155 +/*-----------------------------------------------------------------------
  156 + * I2C
  157 + *----------------------------------------------------------------------*/
  158 +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  159 +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
  160 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  161 +#define CFG_I2C_SLAVE 0x7F
  162 +
  163 +/* these are for the ST M24C02 2kbit serial i2c eeprom */
  164 +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
  165 +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  166 +/* mask of address bits that overflow into the "EEPROM chip address" */
  167 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
  168 +
  169 +#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
  170 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
  171 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  172 +
  173 +/*
  174 + * The layout of the I2C EEPROM, used for bootstrap setup and for board-
  175 + * specific values, like ethaddr... that can be restored via the sw-reset
  176 + * button
  177 + */
  178 +#define FACTORY_RESET_I2C_EEPROM 0x50
  179 +#define FACTORY_RESET_ENV_OFFS 0x80
  180 +#define FACTORY_RESET_ENV_SIZE 0x80
  181 +
  182 +/*-----------------------------------------------------------------------
  183 + * Start addresses for the final memory configuration
  184 + * (Set up by the startup code)
  185 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  186 + */
  187 +#define CFG_SDRAM_BASE 0x00000000
  188 +#define CFG_FLASH_BASE 0xFF000000
  189 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  190 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  191 +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
  192 +
  193 +/*
  194 + * For booting Linux, the board info and command line data
  195 + * have to be in the first 8 MB of memory, since this is
  196 + * the maximum mapped by the Linux kernel during initialization.
  197 + */
  198 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  199 +
  200 +/*-----------------------------------------------------------------------
  201 + * FLASH organization
  202 + */
  203 +#define CFG_FLASH_CFI /* The flash is CFI compatible */
  204 +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
  205 +
  206 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
  207 +
  208 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  209 +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  210 +
  211 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  212 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  213 +
  214 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  215 +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
  216 +
  217 +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  218 +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
  219 +
  220 +#ifdef CFG_ENV_IS_IN_FLASH
  221 +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  222 +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
  223 +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  224 +
  225 +/* Address and size of Redundant Environment Sector */
  226 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
  227 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  228 +#endif
  229 +
  230 +/*-----------------------------------------------------------------------
  231 + * Cache Configuration
  232 + */
  233 +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
  234 +#define CFG_CACHELINE_SIZE 32 /* ... */
  235 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  236 +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  237 +#endif
  238 +
  239 +/*-----------------------------------------------------------------------
  240 + * Definitions for initial stack pointer and data area (in data cache)
  241 + */
  242 +/* use on chip memory (OCM) for temperary stack until sdram is tested */
  243 +#define CFG_TEMP_STACK_OCM 1
  244 +
  245 +/* On Chip Memory location */
  246 +#define CFG_OCM_DATA_ADDR 0xF8000000
  247 +#define CFG_OCM_DATA_SIZE 0x1000
  248 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
  249 +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  250 +
  251 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  252 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  253 +/* reserve some memory for POST and BOOT limit info */
  254 +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
  255 +
  256 +/* extra data in OCM */
  257 +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
  258 +#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
  259 +#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
  260 +
  261 +/*-----------------------------------------------------------------------
  262 + * External Bus Controller (EBC) Setup
  263 + */
  264 +
  265 +/* Memory Bank 0 (Flash 16M) initialization */
  266 +#define CFG_EBC_PB0AP 0x05815600
  267 +#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
  268 +
  269 +/*-----------------------------------------------------------------------
  270 + * Definitions for GPIO setup (PPC405EP specific)
  271 + *
  272 + * GPIO0[0] - External Bus Controller BLAST output
  273 + * GPIO0[1-9] - Instruction trace outputs
  274 + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  275 + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
  276 + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  277 + * GPIO0[24-27] - UART0 control signal inputs/outputs
  278 + * GPIO0[28-29] - UART1 data signal input/output
  279 + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  280 + */
  281 +#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
  282 +#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
  283 +#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
  284 +#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
  285 +#define CFG_GPIO0_TSRH 0x00000000
  286 +#define CFG_GPIO0_TSRL 0x00000000
  287 +#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
  288 +#define CFG_GPIO0_ODR 0x00000000
  289 +
  290 +#define CFG_GPIO_SW_RESET 1
  291 +#define CFG_GPIO_ZEUS_PE 12
  292 +#define CFG_GPIO_LED_RED 22
  293 +#define CFG_GPIO_LED_GREEN 23
  294 +
  295 +/* Time in milli-seconds */
  296 +#define CFG_TIME_POST 5000
  297 +#define CFG_TIME_FACTORY_RESET 10000
  298 +
  299 +/*
  300 + * Internal Definitions
  301 + *
  302 + * Boot Flags
  303 + */
  304 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  305 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  306 +
  307 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  308 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  309 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  310 +#endif
  311 +
  312 +/* ENVIRONMENT VARS */
  313 +
  314 +#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
  315 +#define CONFIG_IPADDR 192.168.1.10
  316 +#define CONFIG_SERVERIP 192.168.1.100
  317 +#define CONFIG_GATEWAYIP 192.168.1.100
  318 +#define CONFIG_ETHADDR 50:00:00:00:06:00
  319 +#define CONFIG_ETH1ADDR 50:00:00:00:06:01
  320 +#if 0
  321 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  322 +#else
  323 +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
  324 +#endif
  325 +
  326 +#define CONFIG_EXTRA_ENV_SETTINGS \
  327 + "logversion=2\0" \
  328 + "hostname=zeus\0" \
  329 + "netdev=eth0\0" \
  330 + "ethact=ppc_4xx_eth0\0" \
  331 + "netmask=255.255.255.0\0" \
  332 + "ramdisk_size=50000\0" \
  333 + "nfsargs=setenv bootargs root=/dev/nfs rw" \
  334 + " nfsroot=${serverip}:${rootpath}\0" \
  335 + "ramargs=setenv bootargs root=/dev/ram rw" \
  336 + " ramdisk=${ramdisk_size}\0" \
  337 + "addip=setenv bootargs ${bootargs} " \
  338 + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  339 + ":${hostname}:${netdev}:off panic=1\0" \
  340 + "addtty=setenv bootargs ${bootargs} console=ttyS0," \
  341 + "${baudrate}\0" \
  342 + "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
  343 + "run nfsargs addip addtty;bootm\0" \
  344 + "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
  345 + "tftp ${ramdisk_mem_addr} ${file_fs};" \
  346 + "run ramargs addip addtty;" \
  347 + "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
  348 + "rootpath=/target_fs/zeus\0" \
  349 + "kernel_fl_addr=ff000000\0" \
  350 + "kernel_mem_addr=200000\0" \
  351 + "ramdisk_fl_addr=ff300000\0" \
  352 + "ramdisk_mem_addr=4000000\0" \
  353 + "uboot_fl_addr=fffc0000\0" \
  354 + "uboot_mem_addr=100000\0" \
  355 + "file_uboot=/zeus/u-boot.bin\0" \
  356 + "tftp_uboot=tftp 100000 ${file_uboot}\0" \
  357 + "update_uboot=protect off fffc0000 ffffffff;" \
  358 + "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
  359 + "protect on fffc0000 ffffffff\0" \
  360 + "upd_uboot=run tftp_uboot;run update_uboot\0" \
  361 + "file_kernel=/zeus/uImage_ba\0" \
  362 + "tftp_kernel=tftp 100000 ${file_kernel}\0" \
  363 + "update_kernel=protect off ff000000 ff17ffff;" \
  364 + "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
  365 + "upd_kernel=run tftp_kernel;run update_kernel\0" \
  366 + "file_fs=/zeus/rootfs_ba.img\0" \
  367 + "tftp_fs=tftp 100000 ${file_fs}\0" \
  368 + "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
  369 + "cp.b 100000 ff300000 580000\0" \
  370 + "upd_fs=run tftp_fs;run update_fs\0" \
  371 + "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
  372 + "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
  373 + ""
  374 +
  375 +#endif /* __CONFIG_H */
... ... @@ -541,6 +541,18 @@
541 541 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
542 542 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
543 543 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  544 +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  545 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  546 + PLL_MALDIV_1 | PLL_PCIDIV_3)
  547 +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
  548 + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  549 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  550 +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  551 + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  552 + PLL_MALDIV_1 | PLL_PCIDIV_1)
  553 +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
  554 + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  555 + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
544 556  
545 557 /*
546 558 * PLL Voltage Controlled Oscillator (VCO) definitions
... ... @@ -1226,6 +1238,8 @@
1226 1238 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
1227 1239 #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
1228 1240  
  1241 +#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
  1242 +#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
1229 1243  
1230 1244 #ifndef __ASSEMBLY__
1231 1245