Eric Lee / smarc-uboot

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Commit 77c07e7ed36cae250a3562ee4bed0fa537960354

Authored by Tom Rini
2 parents c4d323793b a200ebea63
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq 

Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.

Showing 48 changed files Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 77c07e7
... ... @@ -89,7 +89,7 @@
89 89 config ARCH_LS1088A
90 90 bool
91 91 select ARMV8_SET_SMPEN
92   - select ARM_ERRATA_855873
  92 + select ARM_ERRATA_855873 if !TFABOOT
93 93 select FSL_LSCH3
94 94 select SYS_FSL_SRDS_1
95 95 select SYS_HAS_SERDES
... ... @@ -98,11 +98,11 @@
98 98 select SYS_FSL_DDR_VER_50
99 99 select SYS_FSL_EC1
100 100 select SYS_FSL_EC2
101   - select SYS_FSL_ERRATUM_A009803
102   - select SYS_FSL_ERRATUM_A009942
103   - select SYS_FSL_ERRATUM_A010165
104   - select SYS_FSL_ERRATUM_A008511
105   - select SYS_FSL_ERRATUM_A008850
  101 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  102 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  103 + select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  104 + select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  105 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT
106 106 select SYS_FSL_ERRATUM_A009007
107 107 select SYS_FSL_HAS_CCI400
108 108 select SYS_FSL_HAS_DDR4
109 109  
110 110  
... ... @@ -145,20 +145,20 @@
145 145 select SYS_FSL_SRDS_2
146 146 select FSL_TZASC_1
147 147 select FSL_TZASC_2
148   - select SYS_FSL_ERRATUM_A008336
149   - select SYS_FSL_ERRATUM_A008511
150   - select SYS_FSL_ERRATUM_A008514
  148 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT
  149 + select SYS_FSL_ERRATUM_A008511 if !TFABOOT
  150 + select SYS_FSL_ERRATUM_A008514 if !TFABOOT
151 151 select SYS_FSL_ERRATUM_A008585
152 152 select SYS_FSL_ERRATUM_A008997
153 153 select SYS_FSL_ERRATUM_A009007
154 154 select SYS_FSL_ERRATUM_A009008
155 155 select SYS_FSL_ERRATUM_A009635
156   - select SYS_FSL_ERRATUM_A009663
  156 + select SYS_FSL_ERRATUM_A009663 if !TFABOOT
157 157 select SYS_FSL_ERRATUM_A009798
158 158 select SYS_FSL_ERRATUM_A009801
159   - select SYS_FSL_ERRATUM_A009803
160   - select SYS_FSL_ERRATUM_A009942
161   - select SYS_FSL_ERRATUM_A010165
  159 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT
  160 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  161 + select SYS_FSL_ERRATUM_A010165 if !TFABOOT
162 162 select SYS_FSL_ERRATUM_A009203
163 163 select ARCH_EARLY_INIT_R
164 164 select BOARD_EARLY_INIT_F
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 77c07e7
... ... @@ -51,7 +51,9 @@
51 51 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
52 52 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
53 53 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  54 + CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
54 55 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  56 + CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
55 57 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
56 58 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
57 59 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
... ... @@ -675,7 +677,7 @@
675 677 break;
676 678 case RCW_SRC_EMMC_VAL:
677 679 /* RCW SRC EMMC */
678   - src = BOOT_SOURCE_SD_MMC2;
  680 + src = BOOT_SOURCE_SD_MMC;
679 681 break;
680 682 case RCW_SRC_I2C1_VAL:
681 683 /* RCW SRC I2C1 Extended */
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
Diff comments   View file @ 77c07e7
... ... @@ -327,7 +327,7 @@
327 327 memcpy((char *)tmp, p, len);
328 328  
329 329 val = fdt32_to_cpu(tmp[0][6]);
330   - if (rev > REV1_0) {
  330 + if (rev == REV1_0) {
331 331 tmp[1][6] = cpu_to_fdt32(val + 1);
332 332 tmp[2][6] = cpu_to_fdt32(val + 2);
333 333 tmp[3][6] = cpu_to_fdt32(val + 3);
arch/arm/cpu/armv8/fsl-layerscape/soc.c
Diff comments   View file @ 77c07e7
... ... @@ -684,7 +684,7 @@
684 684 #endif
685 685  
686 686 #ifdef CONFIG_TFABOOT
687   -#define MAX_BOOTCMD_SIZE 256
  687 +#define MAX_BOOTCMD_SIZE 512
688 688  
689 689 int fsl_setenv_bootcmd(void)
690 690 {
... ... @@ -812,6 +812,17 @@
812 812 fsl_setenv_bootcmd();
813 813 fsl_setenv_mcinitcmd();
814 814 }
  815 +
  816 + /*
  817 + * If the boot mode is secure, default environment is not present then
  818 + * setenv command needs to be run by default
  819 + */
  820 +#ifdef CONFIG_CHAIN_OF_TRUST
  821 + if ((fsl_check_boot_mode_secure() == 1)) {
  822 + fsl_setenv_bootcmd();
  823 + fsl_setenv_mcinitcmd();
  824 + }
  825 +#endif
815 826 #endif
816 827 #ifdef CONFIG_QSPI_AHB_INIT
817 828 qspi_ahb_init();
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
Diff comments   View file @ 77c07e7
... ... @@ -56,4 +56,8 @@
56 56 reg = <1>;
57 57 };
58 58 };
  59 +
  60 +&sata {
  61 + status = "okay";
  62 +};
arch/arm/dts/ls1021a-iot.dtsi
Diff comments   View file @ 77c07e7
... ... @@ -12,9 +12,9 @@
12 12 model = "LS1021A IOT Board";
13 13  
14 14 aliases {
15   - enet2_rgmii_phy = &rgmii_phy1;
16   - enet0_sgmii_phy = &sgmii_phy2;
17   - enet1_sgmii_phy = &sgmii_phy0;
  15 + enet2-rgmii-phy = &rgmii_phy1;
  16 + enet0-sgmii-phy = &sgmii_phy2;
  17 + enet1-sgmii-phy = &sgmii_phy0;
18 18 spi0 = &qspi;
19 19 spi1 = &dspi1;
20 20 };
arch/arm/dts/ls1021a-qds.dtsi
Diff comments   View file @ 77c07e7
... ... @@ -11,11 +11,11 @@
11 11 model = "LS1021A QDS Board";
12 12  
13 13 aliases {
14   - enet0_rgmii_phy = &rgmii_phy1;
15   - enet1_rgmii_phy = &rgmii_phy2;
16   - enet2_rgmii_phy = &rgmii_phy3;
17   - enet0_sgmii_phy = &sgmii_phy1c;
18   - enet1_sgmii_phy = &sgmii_phy1d;
  14 + enet0-rgmii-phy = &rgmii_phy1;
  15 + enet1-rgmii-phy = &rgmii_phy2;
  16 + enet2-rgmii-phy = &rgmii_phy3;
  17 + enet0-sgmii-phy = &sgmii_phy1c;
  18 + enet1-sgmii-phy = &sgmii_phy1d;
19 19 spi0 = &qspi;
20 20 spi1 = &dspi0;
21 21 };
arch/arm/dts/ls1021a-twr.dtsi
Diff comments   View file @ 77c07e7
... ... @@ -11,9 +11,9 @@
11 11 model = "LS1021A TWR Board";
12 12  
13 13 aliases {
14   - enet2_rgmii_phy = &rgmii_phy1;
15   - enet0_sgmii_phy = &sgmii_phy2;
16   - enet1_sgmii_phy = &sgmii_phy0;
  14 + enet2-rgmii-phy = &rgmii_phy1;
  15 + enet0-sgmii-phy = &sgmii_phy2;
  16 + enet1-sgmii-phy = &sgmii_phy0;
17 17 spi0 = &qspi;
18 18 spi1 = &dspi1;
19 19 };
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
Diff comments   View file @ 77c07e7
... ... @@ -55,7 +55,11 @@
55 55 CONFIG_SYS_FSL_ESDHC_ADDR)
56 56  
57 57 #define SET_QDMA_ICID(compat, streamid) \
58   - SET_SCFG_ICID(compat, streamid, dma_icid,\
  58 + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
  59 + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
  60 + QDMA_BASE_ADDR), \
  61 + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
  62 + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
59 63 QDMA_BASE_ADDR)
60 64  
61 65 #define SET_EDMA_ICID(streamid) \
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Diff comments   View file @ 77c07e7
... ... @@ -94,6 +94,7 @@
94 94 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
95 95  
96 96 #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
  97 +#define QMAN_CQSIDR_REG 0x20a80
97 98  
98 99 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
99 100 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
arch/arm/include/asm/arch-fsl-layerscape/soc.h
Diff comments   View file @ 77c07e7
... ... @@ -80,6 +80,9 @@
80 80 #define SVR_LS1012A 0x870400
81 81 #define SVR_LS1043A 0x879200
82 82 #define SVR_LS1023A 0x879208
  83 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
  84 +#define SVR_LS1043A_P23 0x879202
  85 +#define SVR_LS1023A_P23 0x87920A
83 86 #define SVR_LS1046A 0x870700
84 87 #define SVR_LS1026A 0x870708
85 88 #define SVR_LS1048A 0x870320
board/freescale/ls1046aqds/eth.c
Diff comments   View file @ 77c07e7
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2016 Freescale Semiconductor, Inc.
  4 + * Copyright 2018 NXP
4 5 */
5 6  
6 7 #include <common.h>
... ... @@ -153,6 +154,9 @@
153 154 enum fm_port port, int offset)
154 155 {
155 156 struct fixed_link f_link;
  157 + const u32 *handle;
  158 + const char *prop = NULL;
  159 + int off;
156 160  
157 161 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
158 162 switch (port) {
... ... @@ -208,16 +212,27 @@
208 212 "qsgmii");
209 213 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
210 214 (port == FM1_10GEC1 || port == FM1_10GEC2)) {
211   - /* XFI interface */
212   - f_link.phy_id = cpu_to_fdt32(port);
213   - f_link.duplex = cpu_to_fdt32(1);
214   - f_link.link_speed = cpu_to_fdt32(10000);
215   - f_link.pause = 0;
216   - f_link.asym_pause = 0;
217   - /* no PHY for XFI */
218   - fdt_delprop(fdt, offset, "phy-handle");
219   - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
220   - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
  215 + handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
  216 + prop = NULL;
  217 + if (handle) {
  218 + off = fdt_node_offset_by_phandle(fdt,
  219 + fdt32_to_cpu(*handle));
  220 + prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
  221 + }
  222 + if (!prop || strcmp(prop, "10gbase-kr")) {
  223 + /* XFI interface */
  224 + f_link.phy_id = cpu_to_fdt32(port);
  225 + f_link.duplex = cpu_to_fdt32(1);
  226 + f_link.link_speed = cpu_to_fdt32(10000);
  227 + f_link.pause = 0;
  228 + f_link.asym_pause = 0;
  229 + /* no PHY for XFI */
  230 + fdt_delprop(fdt, offset, "phy-handle");
  231 + fdt_setprop(fdt, offset, "fixed-link", &f_link,
  232 + sizeof(f_link));
  233 + fdt_setprop_string(fdt, offset, "phy-connection-type",
  234 + "xgmii");
  235 + }
221 236 }
222 237 }
223 238  
board/freescale/ls1088a/MAINTAINERS
Diff comments   View file @ 77c07e7
1 1 LS1088ARDB BOARD
2 2 M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
3 3 M: Ashish Kumar <Ashish.Kumar@nxp.com>
  4 +M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
4 5 S: Maintained
5 6 F: board/freescale/ls1088a/
6 7 F: include/configs/ls1088ardb.h
7 8 F: configs/ls1088ardb_qspi_defconfig
8 9 F: configs/ls1088ardb_sdcard_qspi_defconfig
  10 +F: configs/ls1088ardb_tfa_defconfig
  11 +F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
9 12  
10 13 LS1088AQDS BOARD
11 14 M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
12 15 M: Ashish Kumar <Ashish.Kumar@nxp.com>
  16 +M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
13 17 S: Maintained
14 18 F: board/freescale/ls1088a/
15 19 F: include/configs/ls1088aqds.h
... ... @@ -17,6 +21,7 @@
17 21 F: configs/ls1088aqds_sdcard_qspi_defconfig
18 22 F: configs/ls1088aqds_defconfig
19 23 F: configs/ls1088aqds_sdcard_ifc_defconfig
  24 +F: configs/ls1088aqds_tfa_defconfig
20 25  
21 26 LS1088AQDS_QSPI_SECURE_BOOT BOARD
22 27 M: Udit Agarwal <udit.agarwal@nxp.com>
board/freescale/ls1088a/ddr.c
Diff comments   View file @ 77c07e7
... ... @@ -111,7 +111,17 @@
111 111 DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
112 112 }
113 113  
  114 +#ifdef CONFIG_TFABOOT
  115 +int fsl_initdram(void)
  116 +{
  117 + gd->ram_size = tfa_get_dram_size();
114 118  
  119 + if (!gd->ram_size)
  120 + gd->ram_size = fsl_ddr_sdram_size();
  121 +
  122 + return 0;
  123 +}
  124 +#else
115 125 int fsl_initdram(void)
116 126 {
117 127 puts("Initializing DDR....using SPD\n");
... ... @@ -123,4 +133,5 @@
123 133 #endif
124 134 return 0;
125 135 }
  136 +#endif /* CONFIG_TFABOOT */
board/freescale/ls1088a/ls1088a.c
Diff comments   View file @ 77c07e7
... ... @@ -28,6 +28,121 @@
28 28  
29 29 DECLARE_GLOBAL_DATA_PTR;
30 30  
  31 +#ifdef CONFIG_TARGET_LS1088AQDS
  32 +#ifdef CONFIG_TFABOOT
  33 +struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  34 + {
  35 + "nor0",
  36 + CONFIG_SYS_NOR0_CSPR_EARLY,
  37 + CONFIG_SYS_NOR0_CSPR_EXT,
  38 + CONFIG_SYS_NOR_AMASK,
  39 + CONFIG_SYS_NOR_CSOR,
  40 + {
  41 + CONFIG_SYS_NOR_FTIM0,
  42 + CONFIG_SYS_NOR_FTIM1,
  43 + CONFIG_SYS_NOR_FTIM2,
  44 + CONFIG_SYS_NOR_FTIM3
  45 + },
  46 + 0,
  47 + CONFIG_SYS_NOR0_CSPR,
  48 + 0,
  49 + },
  50 + {
  51 + "nor1",
  52 + CONFIG_SYS_NOR1_CSPR_EARLY,
  53 + CONFIG_SYS_NOR0_CSPR_EXT,
  54 + CONFIG_SYS_NOR_AMASK_EARLY,
  55 + CONFIG_SYS_NOR_CSOR,
  56 + {
  57 + CONFIG_SYS_NOR_FTIM0,
  58 + CONFIG_SYS_NOR_FTIM1,
  59 + CONFIG_SYS_NOR_FTIM2,
  60 + CONFIG_SYS_NOR_FTIM3
  61 + },
  62 + 0,
  63 + CONFIG_SYS_NOR1_CSPR,
  64 + CONFIG_SYS_NOR_AMASK,
  65 + },
  66 + {
  67 + "nand",
  68 + CONFIG_SYS_NAND_CSPR,
  69 + CONFIG_SYS_NAND_CSPR_EXT,
  70 + CONFIG_SYS_NAND_AMASK,
  71 + CONFIG_SYS_NAND_CSOR,
  72 + {
  73 + CONFIG_SYS_NAND_FTIM0,
  74 + CONFIG_SYS_NAND_FTIM1,
  75 + CONFIG_SYS_NAND_FTIM2,
  76 + CONFIG_SYS_NAND_FTIM3
  77 + },
  78 + },
  79 + {
  80 + "fpga",
  81 + CONFIG_SYS_FPGA_CSPR,
  82 + CONFIG_SYS_FPGA_CSPR_EXT,
  83 + SYS_FPGA_AMASK,
  84 + CONFIG_SYS_FPGA_CSOR,
  85 + {
  86 + SYS_FPGA_CS_FTIM0,
  87 + SYS_FPGA_CS_FTIM1,
  88 + SYS_FPGA_CS_FTIM2,
  89 + SYS_FPGA_CS_FTIM3
  90 + },
  91 + 0,
  92 + SYS_FPGA_CSPR_FINAL,
  93 + 0,
  94 + }
  95 +};
  96 +
  97 +struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  98 + {
  99 + "nand",
  100 + CONFIG_SYS_NAND_CSPR,
  101 + CONFIG_SYS_NAND_CSPR_EXT,
  102 + CONFIG_SYS_NAND_AMASK,
  103 + CONFIG_SYS_NAND_CSOR,
  104 + {
  105 + CONFIG_SYS_NAND_FTIM0,
  106 + CONFIG_SYS_NAND_FTIM1,
  107 + CONFIG_SYS_NAND_FTIM2,
  108 + CONFIG_SYS_NAND_FTIM3
  109 + },
  110 + },
  111 + {
  112 + "reserved",
  113 + },
  114 + {
  115 + "fpga",
  116 + CONFIG_SYS_FPGA_CSPR,
  117 + CONFIG_SYS_FPGA_CSPR_EXT,
  118 + SYS_FPGA_AMASK,
  119 + CONFIG_SYS_FPGA_CSOR,
  120 + {
  121 + SYS_FPGA_CS_FTIM0,
  122 + SYS_FPGA_CS_FTIM1,
  123 + SYS_FPGA_CS_FTIM2,
  124 + SYS_FPGA_CS_FTIM3
  125 + },
  126 + 0,
  127 + SYS_FPGA_CSPR_FINAL,
  128 + 0,
  129 + }
  130 +};
  131 +
  132 +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  133 +{
  134 + enum boot_src src = get_boot_src();
  135 +
  136 + if (src == BOOT_SOURCE_QSPI_NOR)
  137 + regs_info->regs = ifc_cfg_qspi_nor_boot;
  138 + else
  139 + regs_info->regs = ifc_cfg_ifc_nor_boot;
  140 +
  141 + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  142 +}
  143 +#endif /* CONFIG_TFABOOT */
  144 +#endif /* CONFIG_TARGET_LS1088AQDS */
  145 +
31 146 int board_early_init_f(void)
32 147 {
33 148 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
... ... @@ -88,6 +203,9 @@
88 203 #if !defined(CONFIG_SPL_BUILD)
89 204 int checkboard(void)
90 205 {
  206 +#ifdef CONFIG_TFABOOT
  207 + enum boot_src src = get_boot_src();
  208 +#endif
91 209 char buf[64];
92 210 u8 sw;
93 211 static const char *const freq[] = {"100", "125", "156.25",
94 212  
... ... @@ -117,9 +235,14 @@
117 235 sw = QIXIS_READ(brdcfg[0]);
118 236 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
119 237  
  238 +#ifdef CONFIG_TFABOOT
  239 + if (src == BOOT_SOURCE_SD_MMC)
  240 + puts("SD card\n");
  241 +#else
120 242 #ifdef CONFIG_SD_BOOT
121 243 puts("SD card\n");
122 244 #endif
  245 +#endif /* CONFIG_TFABOOT */
123 246 switch (sw) {
124 247 #ifdef CONFIG_TARGET_LS1088AQDS
125 248 case 0:
... ... @@ -535,7 +658,8 @@
535 658 return;
536 659 }
537 660  
538   - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
  661 + if (get_mc_boot_status() == 0 &&
  662 + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
539 663 fdt_status_okay(fdt, offset);
540 664 else
541 665 fdt_status_fail(fdt, offset);
... ... @@ -546,6 +670,10 @@
546 670 void fsl_fdt_fixup_flash(void *fdt)
547 671 {
548 672 int offset;
  673 +#ifdef CONFIG_TFABOOT
  674 + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  675 + u32 val;
  676 +#endif
549 677  
550 678 /*
551 679 * IFC-NOR and QSPI are muxed on SoC.
... ... @@ -553,6 +681,37 @@
553 681 * disable QSPI node in dts in case QSPI is not enabled.
554 682 */
555 683  
  684 +#ifdef CONFIG_TFABOOT
  685 + enum boot_src src = get_boot_src();
  686 + bool disable_ifc = false;
  687 +
  688 + switch (src) {
  689 + case BOOT_SOURCE_IFC_NOR:
  690 + disable_ifc = false;
  691 + break;
  692 + case BOOT_SOURCE_QSPI_NOR:
  693 + disable_ifc = true;
  694 + break;
  695 + default:
  696 + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  697 + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  698 + disable_ifc = true;
  699 + break;
  700 + }
  701 +
  702 + if (disable_ifc) {
  703 + offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  704 +
  705 + if (offset < 0)
  706 + offset = fdt_path_offset(fdt, "/ifc/nor");
  707 + } else {
  708 + offset = fdt_path_offset(fdt, "/soc/quadspi");
  709 +
  710 + if (offset < 0)
  711 + offset = fdt_path_offset(fdt, "/quadspi");
  712 + }
  713 +
  714 +#else
556 715 #ifdef CONFIG_FSL_QSPI
557 716 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
558 717  
... ... @@ -564,6 +723,7 @@
564 723 if (offset < 0)
565 724 offset = fdt_path_offset(fdt, "/quadspi");
566 725 #endif
  726 +#endif
567 727 if (offset < 0)
568 728 return;
569 729  
... ... @@ -613,4 +773,38 @@
613 773 }
614 774 #endif
615 775 #endif /* defined(CONFIG_SPL_BUILD) */
  776 +
  777 +#ifdef CONFIG_TFABOOT
  778 +#ifdef CONFIG_MTD_NOR_FLASH
  779 +int is_flash_available(void)
  780 +{
  781 + char *env_hwconfig = env_get("hwconfig");
  782 + enum boot_src src = get_boot_src();
  783 + int is_nor_flash_available = 1;
  784 +
  785 + switch (src) {
  786 + case BOOT_SOURCE_IFC_NOR:
  787 + is_nor_flash_available = 1;
  788 + break;
  789 + case BOOT_SOURCE_QSPI_NOR:
  790 + is_nor_flash_available = 0;
  791 + break;
  792 + /*
  793 + * In Case of SD boot,if qspi is defined in env_hwconfig
  794 + * disable nor flash probe.
  795 + */
  796 + default:
  797 + if (hwconfig_f("qspi", env_hwconfig))
  798 + is_nor_flash_available = 0;
  799 + break;
  800 + }
  801 + return is_nor_flash_available;
  802 +}
  803 +#endif
  804 +
  805 +void *env_sf_get_env_addr(void)
  806 +{
  807 + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  808 +}
  809 +#endif
board/freescale/ls2080a/ls2080a.c
Diff comments   View file @ 77c07e7
... ... @@ -89,7 +89,8 @@
89 89 return;
90 90 }
91 91  
92   - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
  92 + if (get_mc_boot_status() == 0 &&
  93 + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
93 94 fdt_status_okay(fdt, offset);
94 95 else
95 96 fdt_status_fail(fdt, offset);
... ... @@ -140,6 +141,13 @@
140 141 #if defined(CONFIG_RESET_PHY_R)
141 142 void reset_phy(void)
142 143 {
  144 +}
  145 +#endif
  146 +
  147 +#ifdef CONFIG_TFABOOT
  148 +void *env_sf_get_env_addr(void)
  149 +{
  150 + return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
143 151 }
144 152 #endif
board/freescale/ls2080aqds/MAINTAINERS
Diff comments   View file @ 77c07e7
1 1 LS2080A BOARD
2 2 M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
  3 +M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
3 4 S: Maintained
4 5 F: board/freescale/ls2080aqds/
5 6 F: board/freescale/ls2080a/ls2080aqds.c
... ... @@ -8,6 +9,7 @@
8 9 F: configs/ls2080aqds_nand_defconfig
9 10 F: configs/ls2080aqds_qspi_defconfig
10 11 F: configs/ls2080aqds_sdcard_defconfig
  12 +F: configs/ls2088aqds_tfa_defconfig
11 13  
12 14 LS2080A_SECURE_BOOT BOARD
13 15 #M: Saksham Jain <saksham.jain@nxp.freescale.com>
board/freescale/ls2080aqds/ddr.c
Diff comments   View file @ 77c07e7
... ... @@ -155,8 +155,19 @@
155 155 }
156 156 }
157 157  
  158 +#ifdef CONFIG_TFABOOT
158 159 int fsl_initdram(void)
159 160 {
  161 + gd->ram_size = tfa_get_dram_size();
  162 +
  163 + if (!gd->ram_size)
  164 + gd->ram_size = fsl_ddr_sdram_size();
  165 +
  166 + return 0;
  167 +}
  168 +#else
  169 +int fsl_initdram(void)
  170 +{
160 171 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
161 172 gd->ram_size = fsl_ddr_sdram_size();
162 173 #else
... ... @@ -167,4 +178,5 @@
167 178  
168 179 return 0;
169 180 }
  181 +#endif /* CONFIG_TFABOOT */
board/freescale/ls2080aqds/ls2080aqds.c
Diff comments   View file @ 77c07e7
... ... @@ -294,7 +294,8 @@
294 294 return;
295 295 }
296 296  
297   - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
  297 + if (get_mc_boot_status() == 0 &&
  298 + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
298 299 fdt_status_okay(fdt, offset);
299 300 else
300 301 fdt_status_fail(fdt, offset);
board/freescale/ls2080ardb/MAINTAINERS
Diff comments   View file @ 77c07e7
... ... @@ -9,8 +9,11 @@
9 9  
10 10 LS2088A_QSPI-boot BOARD
11 11 M: Priyanka Jain <priyanka.jain@nxp.com>
  12 +M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
12 13 S: Maintained
13 14 F: configs/ls2088ardb_qspi_defconfig
  15 +F: configs/ls2088ardb_tfa_defconfig
  16 +F: configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
14 17  
15 18 LS2081ARDB BOARD
16 19 M: Priyanka Jain <priyanka.jain@nxp.com>
board/freescale/ls2080ardb/ddr.c
Diff comments   View file @ 77c07e7
... ... @@ -160,8 +160,19 @@
160 160 }
161 161 }
162 162  
  163 +#ifdef CONFIG_TFABOOT
163 164 int fsl_initdram(void)
164 165 {
  166 + gd->ram_size = tfa_get_dram_size();
  167 +
  168 + if (!gd->ram_size)
  169 + gd->ram_size = fsl_ddr_sdram_size();
  170 +
  171 + return 0;
  172 +}
  173 +#else
  174 +int fsl_initdram(void)
  175 +{
165 176 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
166 177 gd->ram_size = fsl_ddr_sdram_size();
167 178 #else
... ... @@ -172,4 +183,5 @@
172 183  
173 184 return 0;
174 185 }
  186 +#endif /* CONFIG_TFABOOT */
board/freescale/ls2080ardb/ls2080ardb.c
Diff comments   View file @ 77c07e7
... ... @@ -330,7 +330,8 @@
330 330 return;
331 331 }
332 332  
333   - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
  333 + if (get_mc_boot_status() == 0 &&
  334 + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
334 335 fdt_status_okay(fdt, offset);
335 336 else
336 337 fdt_status_fail(fdt, offset);
337 338  
... ... @@ -346,12 +347,47 @@
346 347 void fsl_fdt_fixup_flash(void *fdt)
347 348 {
348 349 int offset;
  350 +#ifdef CONFIG_TFABOOT
  351 + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  352 + u32 val;
  353 +#endif
349 354  
350 355 /*
351 356 * IFC and QSPI are muxed on board.
352 357 * So disable IFC node in dts if QSPI is enabled or
353 358 * disable QSPI node in dts in case QSPI is not enabled.
354 359 */
  360 +#ifdef CONFIG_TFABOOT
  361 + enum boot_src src = get_boot_src();
  362 + bool disable_ifc = false;
  363 +
  364 + switch (src) {
  365 + case BOOT_SOURCE_IFC_NOR:
  366 + disable_ifc = false;
  367 + break;
  368 + case BOOT_SOURCE_QSPI_NOR:
  369 + disable_ifc = true;
  370 + break;
  371 + default:
  372 + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  373 + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  374 + disable_ifc = true;
  375 + break;
  376 + }
  377 +
  378 + if (disable_ifc) {
  379 + offset = fdt_path_offset(fdt, "/soc/ifc");
  380 +
  381 + if (offset < 0)
  382 + offset = fdt_path_offset(fdt, "/ifc");
  383 + } else {
  384 + offset = fdt_path_offset(fdt, "/soc/quadspi");
  385 +
  386 + if (offset < 0)
  387 + offset = fdt_path_offset(fdt, "/quadspi");
  388 + }
  389 +
  390 +#else
355 391 #ifdef CONFIG_FSL_QSPI
356 392 offset = fdt_path_offset(fdt, "/soc/ifc");
357 393  
... ... @@ -363,6 +399,8 @@
363 399 if (offset < 0)
364 400 offset = fdt_path_offset(fdt, "/quadspi");
365 401 #endif
  402 +#endif
  403 +
366 404 if (offset < 0)
367 405 return;
368 406  
configs/ls1043aqds_tfa_defconfig
Diff comments   View file @ 77c07e7
... ... @@ -30,6 +30,7 @@
30 30 CONFIG_OF_CONTROL=y
31 31 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
32 32 CONFIG_ENV_IS_IN_FLASH=y
  33 +CONFIG_ENV_IS_IN_MMC=y
33 34 CONFIG_ENV_IS_IN_NAND=y
34 35 CONFIG_ENV_IS_IN_SPI_FLASH=y
35 36 CONFIG_DM=y
configs/ls1043ardb_tfa_defconfig
Diff comments   View file @ 77c07e7
... ... @@ -26,6 +26,7 @@
26 26 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
27 27 CONFIG_ENV_IS_IN_FLASH=y
28 28 CONFIG_ENV_IS_IN_NAND=y
  29 +CONFIG_ENV_IS_IN_MMC=y
29 30 CONFIG_DM=y
30 31 CONFIG_FSL_CAAM=y
31 32 CONFIG_DM_MMC=y
configs/ls1046aqds_tfa_defconfig
Diff comments   View file @ 77c07e7
... ... @@ -32,6 +32,7 @@
32 32 CONFIG_OF_CONTROL=y
33 33 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
34 34 CONFIG_ENV_IS_IN_FLASH=y
  35 +CONFIG_ENV_IS_IN_MMC=y
35 36 CONFIG_ENV_IS_IN_NAND=y
36 37 CONFIG_ENV_IS_IN_SPI_FLASH=y
37 38 CONFIG_DM=y
configs/ls1046ardb_tfa_defconfig
Diff comments   View file @ 77c07e7
... ... @@ -26,6 +26,7 @@
26 26 CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
27 27 CONFIG_OF_CONTROL=y
28 28 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
  29 +CONFIG_ENV_IS_IN_MMC=y
29 30 CONFIG_ENV_IS_IN_SPI_FLASH=y
30 31 CONFIG_DM=y
31 32 CONFIG_SATA_CEVA=y
configs/ls1088aqds_tfa_defconfig
Diff comments   View file @ 77c07e7
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1088AQDS=y
  3 +CONFIG_SYS_TEXT_BASE=0x82000000
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  6 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  7 +CONFIG_QSPI_AHB_INIT=y
  8 +CONFIG_DISTRO_DEFAULTS=y
  9 +CONFIG_NR_DRAM_BANKS=2
  10 +# CONFIG_SYS_MALLOC_F is not set
  11 +CONFIG_FIT_VERBOSE=y
  12 +CONFIG_OF_BOARD_SETUP=y
  13 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  14 +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
  15 +CONFIG_USE_BOOTARGS=y
  16 +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
  17 +# CONFIG_USE_BOOTCOMMAND is not set
  18 +# CONFIG_DISPLAY_BOARDINFO is not set
  19 +CONFIG_DISPLAY_BOARDINFO_LATE=y
  20 +CONFIG_HUSH_PARSER=y
  21 +CONFIG_CMD_GREPENV=y
  22 +CONFIG_CMD_MEMTEST=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_CMD_MMC=y
  25 +CONFIG_CMD_SF=y
  26 +CONFIG_CMD_USB=y
  27 +# CONFIG_CMD_SETEXPR is not set
  28 +CONFIG_CMD_DHCP=y
  29 +CONFIG_CMD_PING=y
  30 +CONFIG_MP=y
  31 +CONFIG_OF_CONTROL=y
  32 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
  33 +CONFIG_ENV_IS_IN_FLASH=y
  34 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  35 +CONFIG_ENV_IS_IN_NAND=y
  36 +CONFIG_ENV_IS_IN_MMC=y
  37 +CONFIG_NET_RANDOM_ETHADDR=y
  38 +CONFIG_DM=y
  39 +CONFIG_SCSI_AHCI=y
  40 +CONFIG_FSL_ESDHC=y
  41 +CONFIG_MTD_NOR_FLASH=y
  42 +CONFIG_FLASH_CFI_DRIVER=y
  43 +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  44 +CONFIG_SYS_FLASH_CFI=y
  45 +CONFIG_DM_SPI_FLASH=y
  46 +CONFIG_SPI_FLASH=y
  47 +CONFIG_SPI_FLASH_SPANSION=y
  48 +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
  49 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  50 +CONFIG_E1000=y
  51 +CONFIG_MII=y
  52 +CONFIG_PCI=y
  53 +CONFIG_DM_PCI=y
  54 +CONFIG_DM_PCI_COMPAT=y
  55 +CONFIG_PCIE_LAYERSCAPE=y
  56 +CONFIG_SYS_NS16550=y
  57 +CONFIG_SPI=y
  58 +CONFIG_DM_SPI=y
  59 +CONFIG_FSL_DSPI=y
  60 +CONFIG_FSL_QSPI=y
  61 +CONFIG_USB=y
  62 +CONFIG_DM_USB=y
  63 +CONFIG_USB_XHCI_HCD=y
  64 +CONFIG_USB_XHCI_DWC3=y
  65 +CONFIG_USB_DWC3=y
  66 +CONFIG_USB_STORAGE=y
  67 +CONFIG_USB_GADGET=y
  68 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  69 +CONFIG_BLK=y
  70 +CONFIG_DM_MMC=y
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
Diff comments   View file @ 77c07e7
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1088ARDB=y
  3 +CONFIG_SYS_TEXT_BASE=0x82000000
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_SECURE_BOOT=y
  6 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  7 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  8 +CONFIG_QSPI_AHB_INIT=y
  9 +CONFIG_DISTRO_DEFAULTS=y
  10 +CONFIG_NR_DRAM_BANKS=2
  11 +# CONFIG_SYS_MALLOC_F is not set
  12 +CONFIG_FIT_VERBOSE=y
  13 +CONFIG_OF_BOARD_SETUP=y
  14 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  15 +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
  16 +CONFIG_USE_BOOTARGS=y
  17 +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
  18 +# CONFIG_USE_BOOTCOMMAND is not set
  19 +CONFIG_MISC_INIT_R=y
  20 +# CONFIG_DISPLAY_BOARDINFO is not set
  21 +CONFIG_DISPLAY_BOARDINFO_LATE=y
  22 +CONFIG_CMD_GREPENV=y
  23 +CONFIG_CMD_MEMTEST=y
  24 +CONFIG_CMD_I2C=y
  25 +CONFIG_CMD_MMC=y
  26 +CONFIG_CMD_SF=y
  27 +CONFIG_CMD_USB=y
  28 +# CONFIG_CMD_SETEXPR is not set
  29 +CONFIG_MP=y
  30 +CONFIG_OF_CONTROL=y
  31 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
  32 +CONFIG_ENV_IS_NOWHERE=y
  33 +CONFIG_NET_RANDOM_ETHADDR=y
  34 +CONFIG_DM=y
  35 +CONFIG_SCSI_AHCI=y
  36 +CONFIG_FSL_ESDHC=y
  37 +CONFIG_DM_SPI_FLASH=y
  38 +CONFIG_SPI_FLASH=y
  39 +CONFIG_SPI_FLASH_SPANSION=y
  40 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  41 +CONFIG_E1000=y
  42 +CONFIG_MII=y
  43 +CONFIG_PCI=y
  44 +CONFIG_DM_PCI=y
  45 +CONFIG_DM_PCI_COMPAT=y
  46 +CONFIG_PCIE_LAYERSCAPE=y
  47 +CONFIG_SYS_NS16550=y
  48 +CONFIG_SPI=y
  49 +CONFIG_DM_SPI=y
  50 +CONFIG_FSL_DSPI=y
  51 +CONFIG_FSL_QSPI=y
  52 +CONFIG_USB=y
  53 +CONFIG_DM_USB=y
  54 +CONFIG_USB_XHCI_HCD=y
  55 +CONFIG_USB_XHCI_DWC3=y
  56 +CONFIG_USB_DWC3=y
  57 +CONFIG_USB_STORAGE=y
  58 +CONFIG_USB_GADGET=y
  59 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  60 +CONFIG_BLK=y
  61 +CONFIG_DM_MMC=y
  62 +CONFIG_RSA=y
  63 +CONFIG_SPL_RSA=y
  64 +CONFIG_RSA_SOFTWARE_EXP=y
configs/ls1088ardb_tfa_defconfig
Diff comments   View file @ 77c07e7
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1088ARDB=y
  3 +CONFIG_SYS_TEXT_BASE=0x82000000
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  6 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  7 +CONFIG_QSPI_AHB_INIT=y
  8 +CONFIG_DISTRO_DEFAULTS=y
  9 +CONFIG_NR_DRAM_BANKS=2
  10 +# CONFIG_SYS_MALLOC_F is not set
  11 +CONFIG_FIT_VERBOSE=y
  12 +CONFIG_OF_BOARD_SETUP=y
  13 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  14 +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
  15 +CONFIG_USE_BOOTARGS=y
  16 +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
  17 +# CONFIG_USE_BOOTCOMMAND is not set
  18 +CONFIG_MISC_INIT_R=y
  19 +# CONFIG_DISPLAY_BOARDINFO is not set
  20 +CONFIG_DISPLAY_BOARDINFO_LATE=y
  21 +CONFIG_CMD_GREPENV=y
  22 +CONFIG_CMD_MEMTEST=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_CMD_MMC=y
  25 +CONFIG_CMD_SF=y
  26 +CONFIG_CMD_USB=y
  27 +# CONFIG_CMD_SETEXPR is not set
  28 +CONFIG_MP=y
  29 +CONFIG_OF_CONTROL=y
  30 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
  31 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  32 +CONFIG_ENV_IS_IN_MMC=y
  33 +CONFIG_NET_RANDOM_ETHADDR=y
  34 +CONFIG_DM=y
  35 +CONFIG_SCSI_AHCI=y
  36 +CONFIG_FSL_ESDHC=y
  37 +CONFIG_DM_SPI_FLASH=y
  38 +CONFIG_SPI_FLASH=y
  39 +CONFIG_SPI_FLASH_SPANSION=y
  40 +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
  41 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  42 +CONFIG_E1000=y
  43 +CONFIG_MII=y
  44 +CONFIG_PCI=y
  45 +CONFIG_DM_PCI=y
  46 +CONFIG_DM_PCI_COMPAT=y
  47 +CONFIG_PCIE_LAYERSCAPE=y
  48 +CONFIG_SYS_NS16550=y
  49 +CONFIG_SPI=y
  50 +CONFIG_DM_SPI=y
  51 +CONFIG_FSL_DSPI=y
  52 +CONFIG_FSL_QSPI=y
  53 +CONFIG_USB=y
  54 +CONFIG_DM_USB=y
  55 +CONFIG_USB_XHCI_HCD=y
  56 +CONFIG_USB_XHCI_DWC3=y
  57 +CONFIG_USB_DWC3=y
  58 +CONFIG_USB_STORAGE=y
  59 +CONFIG_USB_GADGET=y
  60 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  61 +CONFIG_BLK=y
  62 +CONFIG_DM_MMC=y
configs/ls2088aqds_tfa_defconfig
Diff comments   View file @ 77c07e7
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS2080AQDS=y
  3 +CONFIG_SYS_TEXT_BASE=0x82000000
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  6 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  7 +CONFIG_NR_DRAM_BANKS=3
  8 +# CONFIG_SYS_MALLOC_F is not set
  9 +CONFIG_FIT_VERBOSE=y
  10 +CONFIG_OF_BOARD_SETUP=y
  11 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  12 +CONFIG_BOOTDELAY=10
  13 +CONFIG_USE_BOOTARGS=y
  14 +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
  15 +# CONFIG_USE_BOOTCOMMAND is not set
  16 +CONFIG_CMD_IMLS=y
  17 +CONFIG_CMD_GREPENV=y
  18 +CONFIG_CMD_EEPROM=y
  19 +CONFIG_CMD_GPT=y
  20 +CONFIG_CMD_I2C=y
  21 +CONFIG_CMD_MMC=y
  22 +CONFIG_CMD_NAND=y
  23 +CONFIG_CMD_PCI=y
  24 +CONFIG_CMD_SF=y
  25 +CONFIG_CMD_USB=y
  26 +# CONFIG_CMD_SETEXPR is not set
  27 +CONFIG_CMD_CACHE=y
  28 +CONFIG_CMD_DATE=y
  29 +CONFIG_MP=y
  30 +# CONFIG_ISO_PARTITION is not set
  31 +CONFIG_OF_CONTROL=y
  32 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
  33 +CONFIG_ENV_IS_IN_FLASH=y
  34 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  35 +CONFIG_ENV_IS_IN_MMC=y
  36 +CONFIG_NET_RANDOM_ETHADDR=y
  37 +CONFIG_DM=y
  38 +CONFIG_FSL_CAAM=y
  39 +CONFIG_FSL_ESDHC=y
  40 +CONFIG_MTD_NOR_FLASH=y
  41 +CONFIG_FLASH_CFI_DRIVER=y
  42 +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  43 +CONFIG_SYS_FLASH_CFI=y
  44 +CONFIG_DM_SPI_FLASH=y
  45 +CONFIG_PHYLIB=y
  46 +CONFIG_PHY_GIGE=y
  47 +CONFIG_E1000=y
  48 +CONFIG_MII=y
  49 +CONFIG_PCI=y
  50 +CONFIG_DM_PCI=y
  51 +CONFIG_DM_PCI_COMPAT=y
  52 +CONFIG_PCIE_LAYERSCAPE=y
  53 +CONFIG_SYS_NS16550=y
  54 +CONFIG_SPI=y
  55 +CONFIG_DM_SPI=y
  56 +CONFIG_FSL_DSPI=y
  57 +CONFIG_USB=y
  58 +CONFIG_DM_USB=y
  59 +CONFIG_USB_XHCI_HCD=y
  60 +CONFIG_USB_XHCI_DWC3=y
  61 +CONFIG_USB_STORAGE=y
  62 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  63 +CONFIG_BLK=y
  64 +CONFIG_DM_MMC=y
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
Diff comments   View file @ 77c07e7
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS2080ARDB=y
  3 +CONFIG_SYS_TEXT_BASE=0x82000000
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_SECURE_BOOT=y
  6 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  7 +CONFIG_QSPI_AHB_INIT=y
  8 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  9 +CONFIG_NR_DRAM_BANKS=3
  10 +# CONFIG_SYS_MALLOC_F is not set
  11 +CONFIG_FIT_VERBOSE=y
  12 +CONFIG_OF_BOARD_SETUP=y
  13 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  14 +CONFIG_BOOTDELAY=10
  15 +CONFIG_USE_BOOTARGS=y
  16 +CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
  17 +# CONFIG_USE_BOOTCOMMAND is not set
  18 +CONFIG_MISC_INIT_R=y
  19 +CONFIG_CMD_IMLS=y
  20 +CONFIG_CMD_GREPENV=y
  21 +CONFIG_CMD_EEPROM=y
  22 +CONFIG_CMD_GPT=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_CMD_MMC=y
  25 +CONFIG_CMD_NAND=y
  26 +CONFIG_CMD_PCI=y
  27 +CONFIG_CMD_SF=y
  28 +CONFIG_CMD_USB=y
  29 +# CONFIG_CMD_SETEXPR is not set
  30 +CONFIG_CMD_CACHE=y
  31 +CONFIG_CMD_DATE=y
  32 +CONFIG_MP=y
  33 +CONFIG_OF_CONTROL=y
  34 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
  35 +CONFIG_ENV_IS_NOWHERE=y
  36 +CONFIG_NET_RANDOM_ETHADDR=y
  37 +CONFIG_DM=y
  38 +CONFIG_FSL_CAAM=y
  39 +CONFIG_FSL_ESDHC=y
  40 +CONFIG_MTD_NOR_FLASH=y
  41 +CONFIG_FLASH_CFI_DRIVER=y
  42 +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  43 +CONFIG_SYS_FLASH_CFI=y
  44 +CONFIG_DM_SPI_FLASH=y
  45 +CONFIG_SPI_FLASH=y
  46 +CONFIG_SPI_FLASH_SPANSION=y
  47 +
  48 +CONFIG_PHYLIB=y
  49 +CONFIG_PHY_AQUANTIA=y
  50 +CONFIG_E1000=y
  51 +CONFIG_MII=y
  52 +CONFIG_PCI=y
  53 +CONFIG_DM_PCI=y
  54 +CONFIG_DM_PCI_COMPAT=y
  55 +CONFIG_PCIE_LAYERSCAPE=y
  56 +CONFIG_CONS_INDEX=2
  57 +CONFIG_SYS_NS16550=y
  58 +CONFIG_SPI=y
  59 +CONFIG_DM_SPI=y
  60 +CONFIG_FSL_DSPI=y
  61 +CONFIG_FSL_QSPI=y
  62 +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
  63 +
  64 +CONFIG_USB=y
  65 +CONFIG_DM_USB=y
  66 +CONFIG_USB_XHCI_HCD=y
  67 +CONFIG_USB_XHCI_DWC3=y
  68 +CONFIG_USB_STORAGE=y
  69 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  70 +CONFIG_BLK=y
  71 +CONFIG_DM_MMC=y
  72 +CONFIG_RSA=y
  73 +CONFIG_SPL_RSA=y
  74 +CONFIG_RSA_SOFTWARE_EXP=y
configs/ls2088ardb_tfa_defconfig
Diff comments   View file @ 77c07e7
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS2080ARDB=y
  3 +CONFIG_SYS_TEXT_BASE=0x82000000
  4 +CONFIG_TFABOOT=y
  5 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
  6 +CONFIG_QSPI_AHB_INIT=y
  7 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
  8 +CONFIG_NR_DRAM_BANKS=3
  9 +# CONFIG_SYS_MALLOC_F is not set
  10 +CONFIG_FIT_VERBOSE=y
  11 +CONFIG_OF_BOARD_SETUP=y
  12 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  13 +CONFIG_BOOTDELAY=10
  14 +CONFIG_USE_BOOTARGS=y
  15 +CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
  16 +# CONFIG_USE_BOOTCOMMAND is not set
  17 +CONFIG_MISC_INIT_R=y
  18 +CONFIG_CMD_IMLS=y
  19 +CONFIG_CMD_GREPENV=y
  20 +CONFIG_CMD_EEPROM=y
  21 +CONFIG_CMD_GPT=y
  22 +CONFIG_CMD_I2C=y
  23 +CONFIG_CMD_MMC=y
  24 +CONFIG_CMD_NAND=y
  25 +CONFIG_CMD_PCI=y
  26 +CONFIG_CMD_SF=y
  27 +CONFIG_CMD_USB=y
  28 +# CONFIG_CMD_SETEXPR is not set
  29 +CONFIG_CMD_CACHE=y
  30 +CONFIG_CMD_DATE=y
  31 +CONFIG_MP=y
  32 +CONFIG_OF_CONTROL=y
  33 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
  34 +CONFIG_ENV_IS_IN_FLASH=y
  35 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  36 +CONFIG_ENV_IS_IN_MMC=y
  37 +CONFIG_NET_RANDOM_ETHADDR=y
  38 +CONFIG_DM=y
  39 +CONFIG_FSL_CAAM=y
  40 +CONFIG_FSL_ESDHC=y
  41 +CONFIG_MTD_NOR_FLASH=y
  42 +CONFIG_FLASH_CFI_DRIVER=y
  43 +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
  44 +CONFIG_SYS_FLASH_CFI=y
  45 +CONFIG_DM_SPI_FLASH=y
  46 +CONFIG_SPI_FLASH=y
  47 +CONFIG_SPI_FLASH_SPANSION=y
  48 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  49 +
  50 +CONFIG_PHYLIB=y
  51 +CONFIG_PHY_AQUANTIA=y
  52 +CONFIG_E1000=y
  53 +CONFIG_MII=y
  54 +CONFIG_PCI=y
  55 +CONFIG_DM_PCI=y
  56 +CONFIG_DM_PCI_COMPAT=y
  57 +CONFIG_PCIE_LAYERSCAPE=y
  58 +CONFIG_CONS_INDEX=2
  59 +CONFIG_SYS_NS16550=y
  60 +CONFIG_SPI=y
  61 +CONFIG_DM_SPI=y
  62 +CONFIG_FSL_DSPI=y
  63 +CONFIG_FSL_QSPI=y
  64 +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
  65 +
  66 +CONFIG_USB=y
  67 +CONFIG_DM_USB=y
  68 +CONFIG_USB_XHCI_HCD=y
  69 +CONFIG_USB_XHCI_DWC3=y
  70 +CONFIG_USB_STORAGE=y
  71 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  72 +CONFIG_BLK=y
  73 +CONFIG_DM_MMC=y
drivers/misc/fsl_ifc.c
Diff comments   View file @ 77c07e7
... ... @@ -7,6 +7,7 @@
7 7 #include <common.h>
8 8 #include <fsl_ifc.h>
9 9  
  10 +#ifdef CONFIG_TFABOOT
10 11 struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
11 12 {
12 13 "cs0",
... ... @@ -340,6 +341,7 @@
340 341 regs_info->regs = ifc_cfg_default_boot;
341 342 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
342 343 }
  344 +#endif
343 345  
344 346 void print_ifc_regs(void)
345 347 {
... ... @@ -355,6 +357,7 @@
355 357 }
356 358 }
357 359  
  360 +#ifdef CONFIG_TFABOOT
358 361 void init_early_memctl_regs(void)
359 362 {
360 363 int i, j;
... ... @@ -405,4 +408,174 @@
405 408 regs[i].amask);
406 409 }
407 410 }
  411 +#else
  412 +void init_early_memctl_regs(void)
  413 +{
  414 +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
  415 + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
  416 + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
  417 + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
  418 + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
  419 +
  420 +#ifndef CONFIG_A003399_NOR_WORKAROUND
  421 +#ifdef CONFIG_SYS_CSPR0_EXT
  422 + set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
  423 +#endif
  424 +#ifdef CONFIG_SYS_CSOR0_EXT
  425 + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
  426 +#endif
  427 + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
  428 + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
  429 + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
  430 +#endif
  431 +#endif
  432 +
  433 +#ifdef CONFIG_SYS_CSPR1_EXT
  434 + set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
  435 +#endif
  436 +#ifdef CONFIG_SYS_CSOR1_EXT
  437 + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
  438 +#endif
  439 +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
  440 + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
  441 + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
  442 + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
  443 + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
  444 +
  445 + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
  446 + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
  447 + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
  448 +#endif
  449 +
  450 +#ifdef CONFIG_SYS_CSPR2_EXT
  451 + set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
  452 +#endif
  453 +#ifdef CONFIG_SYS_CSOR2_EXT
  454 + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
  455 +#endif
  456 +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
  457 + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
  458 + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
  459 + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
  460 + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
  461 +
  462 + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
  463 + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
  464 + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
  465 +#endif
  466 +
  467 +#ifdef CONFIG_SYS_CSPR3_EXT
  468 + set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
  469 +#endif
  470 +#ifdef CONFIG_SYS_CSOR3_EXT
  471 + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
  472 +#endif
  473 +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
  474 + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
  475 + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
  476 + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
  477 + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
  478 +
  479 + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
  480 + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
  481 + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
  482 +#endif
  483 +
  484 +#ifdef CONFIG_SYS_CSPR4_EXT
  485 + set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
  486 +#endif
  487 +#ifdef CONFIG_SYS_CSOR4_EXT
  488 + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
  489 +#endif
  490 +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
  491 + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
  492 + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
  493 + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
  494 + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
  495 +
  496 + set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
  497 + set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
  498 + set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
  499 +#endif
  500 +
  501 +#ifdef CONFIG_SYS_CSPR5_EXT
  502 + set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
  503 +#endif
  504 +#ifdef CONFIG_SYS_CSOR5_EXT
  505 + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
  506 +#endif
  507 +#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
  508 + set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
  509 + set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
  510 + set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
  511 + set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
  512 +
  513 + set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
  514 + set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
  515 + set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
  516 +#endif
  517 +
  518 +#ifdef CONFIG_SYS_CSPR6_EXT
  519 + set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
  520 +#endif
  521 +#ifdef CONFIG_SYS_CSOR6_EXT
  522 + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
  523 +#endif
  524 +#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
  525 + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
  526 + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
  527 + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
  528 + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
  529 +
  530 + set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
  531 + set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
  532 + set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
  533 +#endif
  534 +
  535 +#ifdef CONFIG_SYS_CSPR7_EXT
  536 + set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
  537 +#endif
  538 +#ifdef CONFIG_SYS_CSOR7_EXT
  539 + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
  540 +#endif
  541 +#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
  542 + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
  543 + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
  544 + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
  545 + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
  546 +
  547 + set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
  548 + set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
  549 + set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
  550 +#endif
  551 +}
  552 +
  553 +void init_final_memctl_regs(void)
  554 +{
  555 +#ifdef CONFIG_SYS_CSPR0_FINAL
  556 + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
  557 +#endif
  558 +#ifdef CONFIG_SYS_AMASK0_FINAL
  559 + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
  560 +#endif
  561 +#ifdef CONFIG_SYS_CSPR1_FINAL
  562 + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
  563 +#endif
  564 +#ifdef CONFIG_SYS_AMASK1_FINAL
  565 + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
  566 +#endif
  567 +#ifdef CONFIG_SYS_CSPR2_FINAL
  568 + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
  569 +#endif
  570 +#ifdef CONFIG_SYS_AMASK2_FINAL
  571 + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
  572 +#endif
  573 +#ifdef CONFIG_SYS_CSPR3_FINAL
  574 + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
  575 +#endif
  576 +#ifdef CONFIG_SYS_AMASK3_FINAL
  577 + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
  578 +#endif
  579 +}
  580 +#endif
drivers/mmc/fsl_esdhc.c
Diff comments   View file @ 77c07e7
... ... @@ -1545,7 +1545,6 @@
1545 1545 {
1546 1546 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1547 1547  
1548   - return true;
1549 1548 return esdhc_getcd_common(priv);
1550 1549 }
1551 1550  
drivers/net/fsl-mc/mc.c
Diff comments   View file @ 77c07e7
... ... @@ -834,6 +834,11 @@
834 834 return mc_dpl_applied;
835 835 }
836 836  
  837 +int is_lazy_dpl_addr_valid(void)
  838 +{
  839 + return !!mc_lazy_dpl_addr;
  840 +}
  841 +
837 842 /*
838 843 * Return the MC address of private DRAM block.
839 844 * As per MC design document, MC initial base address
drivers/pci/pcie_layerscape.c
Diff comments   View file @ 77c07e7
... ... @@ -225,6 +225,9 @@
225 225 {
226 226 struct udevice *bus = pcie->bus;
227 227  
  228 + if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
  229 + return -ENODEV;
  230 +
228 231 if (!pcie->enabled)
229 232 return -ENXIO;
230 233  
231 234  
... ... @@ -438,9 +441,7 @@
438 441 struct ls_pcie *pcie = dev_get_priv(dev);
439 442 const void *fdt = gd->fdt_blob;
440 443 int node = dev_of_offset(dev);
441   - u8 header_type;
442 444 u16 link_sta;
443   - bool ep_mode;
444 445 uint svr;
445 446 int ret;
446 447 fdt_size_t cfg_size;
447 448  
... ... @@ -524,15 +525,15 @@
524 525 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
525 526 pcie->big_endian);
526 527  
527   - header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
528   - ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
529   - printf("PCIe%u: %s %s", pcie->idx, dev->name,
530   - ep_mode ? "Endpoint" : "Root Complex");
  528 + pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
531 529  
532   - if (ep_mode)
533   - ls_pcie_setup_ep(pcie);
534   - else
535   - ls_pcie_setup_ctrl(pcie);
  530 + if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
  531 + printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
  532 + ls_pcie_setup_ep(pcie);
  533 + } else {
  534 + printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
  535 + ls_pcie_setup_ctrl(pcie);
  536 + }
536 537  
537 538 if (!ls_pcie_link_up(pcie)) {
538 539 /* Let the user know there's no PCIe link */
drivers/pci/pcie_layerscape.h
Diff comments   View file @ 77c07e7
... ... @@ -144,6 +144,7 @@
144 144 bool big_endian;
145 145 bool enabled;
146 146 int next_lut_index;
  147 + int mode;
147 148 };
148 149  
149 150 extern struct list_head ls_pcie_list;
drivers/pci/pcie_layerscape_fixup.c
Diff comments   View file @ 77c07e7
... ... @@ -218,7 +218,7 @@
218 218 }
219 219 #endif
220 220  
221   -static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
  221 +static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
222 222 {
223 223 int off;
224 224 uint svr;
225 225  
... ... @@ -243,10 +243,31 @@
243 243 return;
244 244 }
245 245  
246   - if (pcie->enabled)
  246 + if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
247 247 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
248 248 else
249 249 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  250 +}
  251 +
  252 +static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
  253 +{
  254 + int off;
  255 +
  256 + off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
  257 + pcie->dbi_res.start);
  258 + if (off < 0)
  259 + return;
  260 +
  261 + if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  262 + fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  263 + else
  264 + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  265 +}
  266 +
  267 +static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
  268 +{
  269 + ft_pcie_ep_fix(blob, pcie);
  270 + ft_pcie_rc_fix(blob, pcie);
250 271 }
251 272  
252 273 /* Fixup Kernel DT for PCIe */
include/configs/ls1043a_common.h
Diff comments   View file @ 77c07e7
... ... @@ -323,6 +323,8 @@
323 323 "env exists secureboot && esbc_halt;"
324 324 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
325 325 "env exists secureboot && esbc_halt;"
  326 +#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  327 + "env exists secureboot && esbc_halt;"
326 328 #else
327 329 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
328 330 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
include/configs/ls1088a_common.h
Diff comments   View file @ 77c07e7
... ... @@ -29,16 +29,23 @@
29 29  
30 30 #define LS1088ARDB_PB_BOARD 0x4A
31 31 /* Link Definitions */
  32 +#ifdef CONFIG_TFABOOT
  33 +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  34 +#else
32 35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  36 +#endif
33 37  
34 38 /* Link Definitions */
35   -
  39 +#ifdef CONFIG_TFABOOT
  40 +#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  41 +#else
36 42 #ifdef CONFIG_QSPI_BOOT
37 43 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
38 44 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
39 45 #define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
40 46 CONFIG_ENV_OFFSET)
41 47 #endif
  48 +#endif
42 49  
43 50 #define CONFIG_SKIP_LOWLEVEL_INIT
44 51  
... ... @@ -192,6 +199,7 @@
192 199 "mcinitcmd=fsl_mc start mc 0x580a00000" \
193 200 " 0x580e00000 \0"
194 201  
  202 +#ifndef CONFIG_TFABOOT
195 203 #if defined(CONFIG_QSPI_BOOT)
196 204 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
197 205 "sf read 0x80001000 0xd00000 0x100000;"\
... ... @@ -208,6 +216,7 @@
208 216 " cp.b $kernel_start $kernel_load" \
209 217 " $kernel_size && bootm $kernel_load"
210 218 #endif
  219 +#endif /* CONFIG_TFABOOT */
211 220 #endif
212 221  
213 222 /* Monitor Command Prompt */
include/configs/ls1088aqds.h
Diff comments   View file @ 77c07e7
... ... @@ -14,7 +14,15 @@
14 14 unsigned long get_board_ddr_clk(void);
15 15 #endif
16 16  
  17 +#ifdef CONFIG_TFABOOT
  18 +#define CONFIG_SYS_MMC_ENV_DEV 0
17 19  
  20 +#define CONFIG_ENV_SIZE 0x20000
  21 +#define CONFIG_ENV_OFFSET 0x500000
  22 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
  23 + CONFIG_ENV_OFFSET)
  24 +#define CONFIG_ENV_SECT_SIZE 0x40000
  25 +#else
18 26 #if defined(CONFIG_QSPI_BOOT)
19 27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
20 28 #define CONFIG_ENV_SECT_SIZE 0x40000
... ... @@ -27,6 +35,7 @@
27 35 #define CONFIG_ENV_SECT_SIZE 0x20000
28 36 #define CONFIG_ENV_SIZE 0x20000
29 37 #endif
  38 +#endif
30 39  
31 40 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
32 41 #define CONFIG_QIXIS_I2C_ACCESS
... ... @@ -209,6 +218,44 @@
209 218 FTIM2_GPCM_TWP(0x3E))
210 219 #define SYS_FPGA_CS_FTIM3 0x0
211 220  
  221 +#ifdef CONFIG_TFABOOT
  222 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  223 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  224 +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  225 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  226 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  227 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  228 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  229 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  230 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  231 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  232 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  233 +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  234 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  235 +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  236 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  237 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  238 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  239 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  240 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  241 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  242 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  243 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  244 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  245 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  246 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  247 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  248 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  249 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  250 +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  251 +#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
  252 +#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
  253 +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  254 +#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
  255 +#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
  256 +#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
  257 +#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
  258 +#else
212 259 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
213 260 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
214 261 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
... ... @@ -265,6 +312,7 @@
265 312 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
266 313 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
267 314 #endif
  315 +#endif
268 316  
269 317 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
270 318  
... ... @@ -323,7 +371,8 @@
323 371 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
324 372  
325 373 /* QSPI device */
326   -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  374 +#if defined(CONFIG_TFABOOT) || \
  375 + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
327 376 #define FSL_QSPI_FLASH_SIZE (1 << 26)
328 377 #define FSL_QSPI_FLASH_NUM 2
329 378  
... ... @@ -333,7 +382,8 @@
333 382 #define CONFIG_SPI_FLASH_STMICRO
334 383 #define CONFIG_SPI_FLASH_SST
335 384 #define CONFIG_SPI_FLASH_EON
336   -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  385 +#if !defined(CONFIG_TFABOOT) && \
  386 + !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
337 387 #define CONFIG_SF_DEFAULT_BUS 1
338 388 #define CONFIG_SF_DEFAULT_CS 0
339 389 #endif
... ... @@ -377,6 +427,50 @@
377 427 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
378 428 "mcmemsize=0x70000000 \0"
379 429 #else /* if !(CONFIG_SECURE_BOOT) */
  430 +#ifdef CONFIG_TFABOOT
  431 +#define QSPI_MC_INIT_CMD \
  432 + "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  433 + "sf read 0x80100000 0xE00000 0x100000;" \
  434 + "fsl_mc start mc 0x80000000 0x80100000\0"
  435 +#define SD_MC_INIT_CMD \
  436 + "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  437 + "mmc read 0x80100000 0x7000 0x800;" \
  438 + "fsl_mc start mc 0x80000000 0x80100000\0"
  439 +#define IFC_MC_INIT_CMD \
  440 + "fsl_mc start mc 0x580A00000 0x580E00000\0"
  441 +
  442 +#undef CONFIG_EXTRA_ENV_SETTINGS
  443 +#define CONFIG_EXTRA_ENV_SETTINGS \
  444 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  445 + "loadaddr=0x90100000\0" \
  446 + "kernel_addr=0x100000\0" \
  447 + "kernel_addr_sd=0x800\0" \
  448 + "ramdisk_addr=0x800000\0" \
  449 + "ramdisk_size=0x2000000\0" \
  450 + "fdt_high=0xa0000000\0" \
  451 + "initrd_high=0xffffffffffffffff\0" \
  452 + "kernel_start=0x1000000\0" \
  453 + "kernel_start_sd=0x8000\0" \
  454 + "kernel_load=0xa0000000\0" \
  455 + "kernel_size=0x2800000\0" \
  456 + "kernel_size_sd=0x14000\0" \
  457 + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  458 + "sf read 0x80100000 0xE00000 0x100000;" \
  459 + "fsl_mc start mc 0x80000000 0x80100000\0" \
  460 + "mcmemsize=0x70000000 \0"
  461 +#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \
  462 + "sf read 0x80001000 0xd00000 0x100000;"\
  463 + " fsl_mc lazyapply dpl 0x80001000 &&" \
  464 + " sf read $kernel_load $kernel_start" \
  465 + " $kernel_size && bootm $kernel_load"
  466 +#define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
  467 + " fsl_mc lazyapply dpl 0x80001000 &&" \
  468 + " mmc read $kernel_load $kernel_start_sd" \
  469 + " $kernel_size_sd && bootm $kernel_load"
  470 +#define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
  471 + " cp.b $kernel_start $kernel_load" \
  472 + " $kernel_size && bootm $kernel_load"
  473 +#else
380 474 #if defined(CONFIG_QSPI_BOOT)
381 475 #undef CONFIG_EXTRA_ENV_SETTINGS
382 476 #define CONFIG_EXTRA_ENV_SETTINGS \
... ... @@ -427,6 +521,7 @@
427 521 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
428 522 "mcmemsize=0x70000000 \0"
429 523 #endif
  524 +#endif /* CONFIG_TFABOOT */
430 525 #endif /* CONFIG_SECURE_BOOT */
431 526  
432 527 #ifdef CONFIG_FSL_MC_ENET
include/configs/ls1088ardb.h
Diff comments   View file @ 77c07e7
... ... @@ -8,6 +8,15 @@
8 8  
9 9 #include "ls1088a_common.h"
10 10  
  11 +#ifdef CONFIG_TFABOOT
  12 +#define CONFIG_SYS_MMC_ENV_DEV 0
  13 +
  14 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  15 +#define CONFIG_ENV_OFFSET 0x500000
  16 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
  17 + CONFIG_ENV_OFFSET)
  18 +#define CONFIG_ENV_SECT_SIZE 0x40000
  19 +#else
11 20 #if defined(CONFIG_QSPI_BOOT)
12 21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
13 22 #define CONFIG_ENV_SECT_SIZE 0x40000
14 23  
... ... @@ -21,8 +30,10 @@
21 30 #define CONFIG_ENV_SECT_SIZE 0x20000
22 31 #define CONFIG_ENV_SIZE 0x20000
23 32 #endif
  33 +#endif /* CONFIG_TFABOOT */
24 34  
25   -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  35 +#if defined(CONFIG_TFABOOT) || \
  36 + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
26 37 #ifndef CONFIG_SPL_BUILD
27 38 #define CONFIG_QIXIS_I2C_ACCESS
28 39 #endif
... ... @@ -185,7 +196,8 @@
185 196 FTIM2_GPCM_TWP(0x3E))
186 197 #define SYS_FPGA_CS_FTIM3 0x0
187 198  
188   -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  199 +#if defined(CONFIG_TFABOOT) || \
  200 + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
189 201 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
190 202 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
191 203 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
... ... @@ -215,7 +227,6 @@
215 227 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
216 228 #endif
217 229  
218   -
219 230 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
220 231  
221 232 #define I2C_MUX_CH_VOL_MONITOR 0xA
... ... @@ -274,7 +285,8 @@
274 285  
275 286 #ifndef SPL_NO_QSPI
276 287 /* QSPI device */
277   -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  288 +#if defined(CONFIG_TFABOOT) || \
  289 + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
278 290 #define FSL_QSPI_FLASH_SIZE (1 << 26)
279 291 #define FSL_QSPI_FLASH_NUM 2
280 292 #endif
... ... @@ -294,6 +306,26 @@
294 306  
295 307 #ifndef SPL_NO_ENV
296 308 /* Initial environment variables */
  309 +#ifdef CONFIG_TFABOOT
  310 +#define QSPI_MC_INIT_CMD \
  311 + "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  312 + "sf read 0x80100000 0xE00000 0x100000;" \
  313 + "env exists secureboot && " \
  314 + "sf read 0x80700000 0x700000 0x40000 && " \
  315 + "sf read 0x80740000 0x740000 0x40000 && " \
  316 + "esbc_validate 0x80700000 && " \
  317 + "esbc_validate 0x80740000 ;" \
  318 + "fsl_mc start mc 0x80000000 0x80100000\0"
  319 +#define SD_MC_INIT_CMD \
  320 + "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  321 + "mmc read 0x80100000 0x7000 0x800;" \
  322 + "env exists secureboot && " \
  323 + "mmc read 0x80700000 0x3800 0x10 && " \
  324 + "mmc read 0x80740000 0x3A00 0x10 && " \
  325 + "esbc_validate 0x80700000 && " \
  326 + "esbc_validate 0x80740000 ;" \
  327 + "fsl_mc start mc 0x80000000 0x80100000\0"
  328 +#else
297 329 #if defined(CONFIG_QSPI_BOOT)
298 330 #define MC_INIT_CMD \
299 331 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
300 332  
... ... @@ -317,8 +349,10 @@
317 349 "fsl_mc start mc 0x80000000 0x80100000\0" \
318 350 "mcmemsize=0x70000000\0"
319 351 #endif
  352 +#endif /* CONFIG_TFABOOT */
320 353  
321 354 #undef CONFIG_EXTRA_ENV_SETTINGS
  355 +#ifdef CONFIG_TFABOOT
322 356 #define CONFIG_EXTRA_ENV_SETTINGS \
323 357 "BOARD=ls1088ardb\0" \
324 358 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
... ... @@ -344,6 +378,80 @@
344 378 "kernel_size=0x2800000\0" \
345 379 "kernel_size_sd=0x14000\0" \
346 380 "kernelhdr_size_sd=0x10\0" \
  381 + QSPI_MC_INIT_CMD \
  382 + "mcmemsize=0x70000000\0" \
  383 + BOOTENV \
  384 + "boot_scripts=ls1088ardb_boot.scr\0" \
  385 + "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
  386 + "scan_dev_for_boot_part=" \
  387 + "part list ${devtype} ${devnum} devplist; " \
  388 + "env exists devplist || setenv devplist 1; " \
  389 + "for distro_bootpart in ${devplist}; do " \
  390 + "if fstype ${devtype} " \
  391 + "${devnum}:${distro_bootpart} " \
  392 + "bootfstype; then " \
  393 + "run scan_dev_for_boot; " \
  394 + "fi; " \
  395 + "done\0" \
  396 + "scan_dev_for_boot=" \
  397 + "echo Scanning ${devtype} " \
  398 + "${devnum}:${distro_bootpart}...; " \
  399 + "for prefix in ${boot_prefixes}; do " \
  400 + "run scan_dev_for_scripts; " \
  401 + "done;\0" \
  402 + "boot_a_script=" \
  403 + "load ${devtype} ${devnum}:${distro_bootpart} " \
  404 + "${scriptaddr} ${prefix}${script}; " \
  405 + "env exists secureboot && load ${devtype} " \
  406 + "${devnum}:${distro_bootpart} " \
  407 + "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  408 + "&& esbc_validate ${scripthdraddr};" \
  409 + "source ${scriptaddr}\0" \
  410 + "installer=load mmc 0:2 $load_addr " \
  411 + "/flex_installer_arm64.itb; " \
  412 + "env exists mcinitcmd && run mcinitcmd && " \
  413 + "mmc read 0x80001000 0x6800 0x800;" \
  414 + "fsl_mc lazyapply dpl 0x80001000;" \
  415 + "bootm $load_addr#ls1088ardb\0" \
  416 + "qspi_bootcmd=echo Trying load from qspi..;" \
  417 + "sf probe && sf read $load_addr " \
  418 + "$kernel_addr $kernel_size ; env exists secureboot " \
  419 + "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  420 + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  421 + "bootm $load_addr#$BOARD\0" \
  422 + "sd_bootcmd=echo Trying load from sd card..;" \
  423 + "mmcinfo; mmc read $load_addr " \
  424 + "$kernel_addr_sd $kernel_size_sd ;" \
  425 + "env exists secureboot && mmc read $kernelheader_addr_r "\
  426 + "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  427 + " && esbc_validate ${kernelheader_addr_r};" \
  428 + "bootm $load_addr#$BOARD\0"
  429 +#else
  430 +#define CONFIG_EXTRA_ENV_SETTINGS \
  431 + "BOARD=ls1088ardb\0" \
  432 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  433 + "ramdisk_addr=0x800000\0" \
  434 + "ramdisk_size=0x2000000\0" \
  435 + "fdt_high=0xa0000000\0" \
  436 + "initrd_high=0xffffffffffffffff\0" \
  437 + "fdt_addr=0x64f00000\0" \
  438 + "kernel_addr=0x1000000\0" \
  439 + "kernel_addr_sd=0x8000\0" \
  440 + "kernelhdr_addr_sd=0x4000\0" \
  441 + "kernel_start=0x580100000\0" \
  442 + "kernelheader_start=0x580800000\0" \
  443 + "scriptaddr=0x80000000\0" \
  444 + "scripthdraddr=0x80080000\0" \
  445 + "fdtheader_addr_r=0x80100000\0" \
  446 + "kernelheader_addr=0x800000\0" \
  447 + "kernelheader_addr_r=0x80200000\0" \
  448 + "kernel_addr_r=0x81000000\0" \
  449 + "kernelheader_size=0x40000\0" \
  450 + "fdt_addr_r=0x90000000\0" \
  451 + "load_addr=0xa0000000\0" \
  452 + "kernel_size=0x2800000\0" \
  453 + "kernel_size_sd=0x14000\0" \
  454 + "kernelhdr_size_sd=0x10\0" \
347 455 MC_INIT_CMD \
348 456 BOOTENV \
349 457 "boot_scripts=ls1088ardb_boot.scr\0" \
350 458  
... ... @@ -391,8 +499,28 @@
391 499 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
392 500 " && esbc_validate ${kernelheader_addr_r};" \
393 501 "bootm $load_addr#$BOARD\0"
  502 +#endif /* CONFIG_TFABOOT */
394 503  
395 504 #undef CONFIG_BOOTCOMMAND
  505 +#ifdef CONFIG_TFABOOT
  506 +#define QSPI_NOR_BOOTCOMMAND \
  507 + "sf read 0x80001000 0xd00000 0x100000;" \
  508 + "env exists mcinitcmd && env exists secureboot " \
  509 + " && sf read 0x80780000 0x780000 0x100000 " \
  510 + "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  511 + "&& fsl_mc lazyapply dpl 0x80001000;" \
  512 + "run distro_bootcmd;run qspi_bootcmd;" \
  513 + "env exists secureboot && esbc_halt;"
  514 +#define SD_BOOTCOMMAND \
  515 + "env exists mcinitcmd && mmcinfo; " \
  516 + "mmc read 0x80001000 0x6800 0x800; " \
  517 + "env exists mcinitcmd && env exists secureboot " \
  518 + " && mmc read 0x80780000 0x3C00 0x10 " \
  519 + "&& esbc_validate 0x80780000;env exists mcinitcmd " \
  520 + "&& fsl_mc lazyapply dpl 0x80001000;" \
  521 + "run distro_bootcmd;run sd_bootcmd;" \
  522 + "env exists secureboot && esbc_halt;"
  523 +#else
396 524 #if defined(CONFIG_QSPI_BOOT)
397 525 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
398 526 #define CONFIG_BOOTCOMMAND \
... ... @@ -416,6 +544,7 @@
416 544 "run distro_bootcmd;run sd_bootcmd;" \
417 545 "env exists secureboot && esbc_halt;"
418 546 #endif
  547 +#endif /* CONFIG_TFABOOT */
419 548  
420 549 /* MAC/PHY configuration */
421 550 #ifdef CONFIG_FSL_MC_ENET
include/configs/ls2080a_common.h
Diff comments   View file @ 77c07e7
... ... @@ -16,17 +16,23 @@
16 16 #include <asm/arch/config.h>
17 17  
18 18 /* Link Definitions */
  19 +#ifdef CONFIG_TFABOOT
  20 +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  21 +#else
19 22 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  23 +#endif
20 24  
21 25 /* We need architecture specific misc initializations */
22 26  
23 27 /* Link Definitions */
  28 +#ifndef CONFIG_TFABOOT
24 29 #ifndef CONFIG_QSPI_BOOT
25 30 #else
26 31 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
27 32 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
28 33 #define CONFIG_ENV_SECT_SIZE 0x40000
29 34 #endif
  35 +#endif
30 36  
31 37 #define CONFIG_SKIP_LOWLEVEL_INIT
32 38  
... ... @@ -185,6 +191,7 @@
185 191 "mcinitcmd=fsl_mc start mc 0x580a00000" \
186 192 " 0x580e00000 \0"
187 193  
  194 +#ifndef CONFIG_TFABOOT
188 195 #ifdef CONFIG_SD_BOOT
189 196 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
190 197 " fsl_mc apply dpl 0x80200000 &&" \
... ... @@ -194,6 +201,7 @@
194 201 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
195 202 " cp.b $kernel_start $kernel_load" \
196 203 " $kernel_size && bootm $kernel_load"
  204 +#endif
197 205 #endif
198 206  
199 207 /* Monitor Command Prompt */
include/configs/ls2080aqds.h
Diff comments   View file @ 77c07e7
... ... @@ -55,6 +55,15 @@
55 55 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
56 56 CONFIG_SYS_SCSI_MAX_LUN)
57 57  
  58 +#ifdef CONFIG_TFABOOT
  59 +#define CONFIG_SYS_MMC_ENV_DEV 0
  60 +#define CONFIG_ENV_SIZE 0x20000
  61 +#define CONFIG_ENV_OFFSET 0x500000
  62 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
  63 + CONFIG_ENV_OFFSET)
  64 +#define CONFIG_ENV_SECT_SIZE 0x20000
  65 +#endif
  66 +
58 67 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
59 68  
60 69 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
... ... @@ -261,7 +270,7 @@
261 270 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
262 271 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
263 272  
264   -#ifndef CONFIG_QSPI_BOOT
  273 +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT)
265 274 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
266 275 #define CONFIG_ENV_SECT_SIZE 0x20000
267 276 #define CONFIG_ENV_SIZE 0x2000
... ... @@ -361,6 +370,33 @@
361 370 "esbc_validate 0x580740000;" \
362 371 "fsl_mc start mc 0x580a00000" \
363 372 " 0x580e00000 \0"
  373 +#else
  374 +#ifdef CONFIG_TFABOOT
  375 +#define SD_MC_INIT_CMD \
  376 + "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  377 + "mmc read 0x80100000 0x7000 0x800;" \
  378 + "fsl_mc start mc 0x80000000 0x80100000\0"
  379 +#define IFC_MC_INIT_CMD \
  380 + "fsl_mc start mc 0x580a00000" \
  381 + " 0x580e00000 \0"
  382 +#define CONFIG_EXTRA_ENV_SETTINGS \
  383 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  384 + "loadaddr=0x80100000\0" \
  385 + "loadaddr_sd=0x90100000\0" \
  386 + "kernel_addr=0x100000\0" \
  387 + "kernel_addr_sd=0x800\0" \
  388 + "ramdisk_addr=0x800000\0" \
  389 + "ramdisk_size=0x2000000\0" \
  390 + "fdt_high=0xa0000000\0" \
  391 + "initrd_high=0xffffffffffffffff\0" \
  392 + "kernel_start=0x581000000\0" \
  393 + "kernel_start_sd=0x8000\0" \
  394 + "kernel_load=0xa0000000\0" \
  395 + "kernel_size=0x2800000\0" \
  396 + "kernel_size_sd=0x14000\0" \
  397 + "mcinitcmd=fsl_mc start mc 0x580a00000" \
  398 + " 0x580e00000 \0" \
  399 + "mcmemsize=0x70000000 \0"
364 400 #elif defined(CONFIG_SD_BOOT)
365 401 #define CONFIG_EXTRA_ENV_SETTINGS \
366 402 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
367 403  
... ... @@ -392,8 +428,8 @@
392 428 "mcmemsize=0x40000000\0" \
393 429 "mcinitcmd=fsl_mc start mc 0x580a00000" \
394 430 " 0x580e00000 \0"
  431 +#endif /* CONFIG_TFABOOT */
395 432 #endif /* CONFIG_SECURE_BOOT */
396   -
397 433  
398 434 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
399 435 #define CONFIG_FSL_MEMAC
include/configs/ls2080ardb.h
Diff comments   View file @ 77c07e7
... ... @@ -69,8 +69,17 @@
69 69 #define CONFIG_SYS_SCSI_MAX_LUN 1
70 70 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
71 71 CONFIG_SYS_SCSI_MAX_LUN)
  72 +#ifdef CONFIG_TFABOOT
  73 +#define CONFIG_SYS_MMC_ENV_DEV 0
72 74  
73   -#ifndef CONFIG_FSL_QSPI
  75 +#define CONFIG_ENV_SIZE 0x2000
  76 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
  77 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
  78 + CONFIG_ENV_OFFSET)
  79 +#define CONFIG_ENV_SECT_SIZE 0x40000
  80 +#endif
  81 +
  82 +#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
74 83 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
75 84  
76 85 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
77 86  
... ... @@ -212,9 +221,11 @@
212 221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
213 222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
214 223  
  224 +#ifndef CONFIG_TFABOOT
215 225 #define CONFIG_ENV_OFFSET (2048 * 1024)
216 226 #define CONFIG_ENV_SECT_SIZE 0x20000
217 227 #define CONFIG_ENV_SIZE 0x2000
  228 +#endif
218 229 #define CONFIG_SPL_PAD_TO 0x80000
219 230 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
220 231 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
221 232  
... ... @@ -237,10 +248,12 @@
237 248 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
238 249 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
239 250  
  251 +#ifndef CONFIG_TFABOOT
240 252 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
241 253 #define CONFIG_ENV_SECT_SIZE 0x20000
242 254 #define CONFIG_ENV_SIZE 0x2000
243 255 #endif
  256 +#endif
244 257  
245 258 /* Debug Server firmware */
246 259 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
... ... @@ -323,6 +336,27 @@
323 336 func(SCSI, scsi, 0)
324 337 #include <config_distro_bootcmd.h>
325 338  
  339 +#ifdef CONFIG_TFABOOT
  340 +#define QSPI_MC_INIT_CMD \
  341 + "env exists secureboot && " \
  342 + "esbc_validate 0x20700000 && " \
  343 + "esbc_validate 0x20740000;" \
  344 + "fsl_mc start mc 0x20a00000 0x20e00000 \0"
  345 +#define SD_MC_INIT_CMD \
  346 + "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
  347 + "mmc read 0x80100000 0x7000 0x800;" \
  348 + "env exists secureboot && " \
  349 + "mmc read 0x80700000 0x3800 0x10 && " \
  350 + "mmc read 0x80740000 0x3A00 0x10 && " \
  351 + "esbc_validate 0x80700000 && " \
  352 + "esbc_validate 0x80740000 ;" \
  353 + "fsl_mc start mc 0x80000000 0x80100000\0"
  354 +#define IFC_MC_INIT_CMD \
  355 + "env exists secureboot && " \
  356 + "esbc_validate 0x580700000 && " \
  357 + "esbc_validate 0x580740000; " \
  358 + "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  359 +#else
326 360 #ifdef CONFIG_QSPI_BOOT
327 361 #define MC_INIT_CMD \
328 362 "mcinitcmd=env exists secureboot && " \
329 363  
... ... @@ -347,9 +381,11 @@
347 381 "esbc_validate 0x580740000; " \
348 382 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
349 383 #endif
  384 +#endif
350 385  
351 386 /* Initial environment variables */
352 387 #undef CONFIG_EXTRA_ENV_SETTINGS
  388 +#ifdef CONFIG_TFABOOT
353 389 #define CONFIG_EXTRA_ENV_SETTINGS \
354 390 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
355 391 "ramdisk_addr=0x800000\0" \
... ... @@ -378,6 +414,75 @@
378 414 "mmcinfo; mmc read $load_addr " \
379 415 "$kernel_addr_sd $kernel_size_sd && " \
380 416 "bootm $load_addr#$board\0" \
  417 + QSPI_MC_INIT_CMD \
  418 + BOOTENV \
  419 + "boot_scripts=ls2088ardb_boot.scr\0" \
  420 + "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  421 + "scan_dev_for_boot_part=" \
  422 + "part list ${devtype} ${devnum} devplist; " \
  423 + "env exists devplist || setenv devplist 1; " \
  424 + "for distro_bootpart in ${devplist}; do " \
  425 + "if fstype ${devtype} " \
  426 + "${devnum}:${distro_bootpart} " \
  427 + "bootfstype; then " \
  428 + "run scan_dev_for_boot; " \
  429 + "fi; " \
  430 + "done\0" \
  431 + "scan_dev_for_boot=" \
  432 + "echo Scanning ${devtype} " \
  433 + "${devnum}:${distro_bootpart}...; " \
  434 + "for prefix in ${boot_prefixes}; do " \
  435 + "run scan_dev_for_scripts; " \
  436 + "done;\0" \
  437 + "boot_a_script=" \
  438 + "load ${devtype} ${devnum}:${distro_bootpart} " \
  439 + "${scriptaddr} ${prefix}${script}; " \
  440 + "env exists secureboot && load ${devtype} " \
  441 + "${devnum}:${distro_bootpart} " \
  442 + "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  443 + "&& esbc_validate ${scripthdraddr};" \
  444 + "source ${scriptaddr}\0" \
  445 + "qspi_bootcmd=echo Trying load from qspi..;" \
  446 + "sf probe && sf read $load_addr " \
  447 + "$kernel_start $kernel_size ; env exists secureboot &&" \
  448 + "sf read $kernelheader_addr_r $kernelheader_start " \
  449 + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  450 + " bootm $load_addr#$board\0" \
  451 + "nor_bootcmd=echo Trying load from nor..;" \
  452 + "cp.b $kernel_addr $load_addr " \
  453 + "$kernel_size ; env exists secureboot && " \
  454 + "cp.b $kernelheader_addr $kernelheader_addr_r " \
  455 + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  456 + "bootm $load_addr#$board\0"
  457 +#else
  458 +#define CONFIG_EXTRA_ENV_SETTINGS \
  459 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  460 + "ramdisk_addr=0x800000\0" \
  461 + "ramdisk_size=0x2000000\0" \
  462 + "fdt_high=0xa0000000\0" \
  463 + "initrd_high=0xffffffffffffffff\0" \
  464 + "fdt_addr=0x64f00000\0" \
  465 + "kernel_addr=0x581000000\0" \
  466 + "kernel_start=0x1000000\0" \
  467 + "kernelheader_start=0x800000\0" \
  468 + "scriptaddr=0x80000000\0" \
  469 + "scripthdraddr=0x80080000\0" \
  470 + "fdtheader_addr_r=0x80100000\0" \
  471 + "kernelheader_addr_r=0x80200000\0" \
  472 + "kernelheader_addr=0x580800000\0" \
  473 + "kernel_addr_r=0x81000000\0" \
  474 + "kernelheader_size=0x40000\0" \
  475 + "fdt_addr_r=0x90000000\0" \
  476 + "load_addr=0xa0000000\0" \
  477 + "kernel_size=0x2800000\0" \
  478 + "kernel_addr_sd=0x8000\0" \
  479 + "kernel_size_sd=0x14000\0" \
  480 + "console=ttyAMA0,38400n8\0" \
  481 + "mcmemsize=0x70000000\0" \
  482 + "sd_bootcmd=echo Trying load from SD ..;" \
  483 + "mmcinfo; mmc read $load_addr " \
  484 + "$kernel_addr_sd $kernel_size_sd && " \
  485 + "bootm $load_addr#$board\0" \
381 486 MC_INIT_CMD \
382 487 BOOTENV \
383 488 "boot_scripts=ls2088ardb_boot.scr\0" \
384 489  
... ... @@ -418,7 +523,36 @@
418 523 "cp.b $kernelheader_addr $kernelheader_addr_r " \
419 524 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
420 525 "bootm $load_addr#$board\0"
  526 +#endif
421 527  
  528 +#ifdef CONFIG_TFABOOT
  529 +#define QSPI_NOR_BOOTCOMMAND \
  530 + "env exists mcinitcmd && env exists secureboot "\
  531 + "&& esbc_validate 0x20780000; " \
  532 + "env exists mcinitcmd && " \
  533 + "fsl_mc lazyapply dpl 0x20d00000; " \
  534 + "run distro_bootcmd;run qspi_bootcmd; " \
  535 + "env exists secureboot && esbc_halt;"
  536 +
  537 +/* Try to boot an on-SD kernel first, then do normal distro boot */
  538 +#define SD_BOOTCOMMAND \
  539 + "env exists mcinitcmd && env exists secureboot "\
  540 + "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
  541 + "&& esbc_validate $load_addr; " \
  542 + "env exists mcinitcmd && run mcinitcmd " \
  543 + "&& mmc read 0x88000000 0x6800 0x800 " \
  544 + "&& fsl_mc lazyapply dpl 0x88000000; " \
  545 + "run distro_bootcmd;run sd_bootcmd; " \
  546 + "env exists secureboot && esbc_halt;"
  547 +
  548 +/* Try to boot an on-NOR kernel first, then do normal distro boot */
  549 +#define IFC_NOR_BOOTCOMMAND \
  550 + "env exists mcinitcmd && env exists secureboot "\
  551 + "&& esbc_validate 0x580780000; env exists mcinitcmd "\
  552 + "&& fsl_mc lazyapply dpl 0x580d00000;" \
  553 + "run distro_bootcmd;run nor_bootcmd; " \
  554 + "env exists secureboot && esbc_halt;"
  555 +#else
422 556 #undef CONFIG_BOOTCOMMAND
423 557 #ifdef CONFIG_QSPI_BOOT
424 558 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
... ... @@ -448,6 +582,7 @@
448 582 "&& fsl_mc lazyapply dpl 0x580d00000;" \
449 583 "run distro_bootcmd;run nor_bootcmd; " \
450 584 "env exists secureboot && esbc_halt;"
  585 +#endif
451 586 #endif
452 587  
453 588 /* MAC/PHY configuration */
include/environment.h
Diff comments   View file @ 77c07e7
... ... @@ -162,15 +162,6 @@
162 162 extern void env_reloc(void);
163 163 #endif
164 164  
165   -#ifdef CONFIG_ENV_IS_IN_MMC
166   -#include <mmc.h>
167   -
168   -extern int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
169   -# ifdef CONFIG_SYS_MMC_ENV_PART
170   -extern uint mmc_get_env_part(struct mmc *mmc);
171   -# endif
172   -#endif
173   -
174 165 #ifndef DO_DEPS_ONLY
175 166  
176 167 #include <env_attr.h>
include/fsl-mc/fsl_mc.h
Diff comments   View file @ 77c07e7
... ... @@ -54,6 +54,7 @@
54 54 void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
55 55 int get_mc_boot_status(void);
56 56 int get_dpl_apply_status(void);
  57 +int is_lazy_dpl_addr_valid(void);
57 58 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
58 59 int get_aiop_apply_status(void);
59 60 #endif
... ... @@ -828,6 +828,9 @@
828 828 int board_mmc_init(bd_t *bis);
829 829 int cpu_mmc_init(bd_t *bis);
830 830 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  831 +# ifdef CONFIG_SYS_MMC_ENV_PART
  832 +extern uint mmc_get_env_part(struct mmc *mmc);
  833 +# endif
831 834 int mmc_get_env_dev(void);
832 835  
833 836 /* Set block count limit because of 16 bit register limit on some hardware*/