zynq: Move zynq to clock framework

Move the zynq to clock framework and remove unused functions as well as the CONFIG_ZYNQ_PS_CLK_FREQ configuration. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

zynq: Move zynq to clock framework
Move the zynq to clock framework and remove unused functions as well as the CONFIG_ZYNQ_PS_CLK_FREQ configuration. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Stefan Herbrechtsmeier · Michal Simek
1 parent 3a64b25364
Showing 13 changed files with 59 additions and 651 deletions Side-by-side Diff
arch/arm/Kconfig
arch/arm/dts/zynq-7000.dtsi
arch/arm/mach-zynq/clk.c
arch/arm/mach-zynq/cpu.c
arch/arm/mach-zynq/include/mach/clk.h
arch/arm/mach-zynq/include/mach/sys_proto.h
arch/arm/mach-zynq/slcr.c
arch/arm/mach-zynq/timer.c
drivers/net/zynq_gem.c
drivers/serial/serial_zynq.c
include/configs/topic_miami.h
include/configs/zynq_zybo.h
scripts/config_whitelist.txt
@@ -714,6 +714,9 @@
 	select SPL_SEPARATE_BSS if SPL
 	select DM_USB if USB
 	select BLK
+	select CLK
+	select SPL_CLK
+	select CLK_ZYNQ
  
 config ARCH_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
@@ -248,12 +248,14 @@
 		};
  
 		slcr: slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 			reg = <0xF8000000 0x1000>;
 			ranges;
 			clkc: clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <1>;
 				compatible = "xlnx,ps7-clkc";
 				fclk-enable = <0>;
@@ -4,77 +4,13 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+#include <clk.h>
 #include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <dm.h>
 #include <asm/arch/clk.h>
  
-/* Board oscillator frequency */
-#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
-# define CONFIG_ZYNQ_PS_CLK_FREQ	33333333UL
-#endif
-
-/* Register bitfield defines */
-#define PLLCTRL_FBDIV_MASK	0x7f000
-#define PLLCTRL_FBDIV_SHIFT	12
-#define PLLCTRL_BPFORCE_MASK	(1 << 4)
-#define PLLCTRL_PWRDWN_MASK	2
-#define PLLCTRL_PWRDWN_SHIFT	1
-#define PLLCTRL_RESET_MASK	1
-#define PLLCTRL_RESET_SHIFT	0
-
-#define ZYNQ_CLK_MAXDIV		0x3f
-#define CLK_CTRL_DIV1_SHIFT	20
-#define CLK_CTRL_DIV1_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
-#define CLK_CTRL_DIV0_SHIFT	8
-#define CLK_CTRL_DIV0_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
-#define CLK_CTRL_SRCSEL_SHIFT	4
-#define CLK_CTRL_SRCSEL_MASK	(0x3 << CLK_CTRL_SRCSEL_SHIFT)
-
-#define CLK_CTRL_DIV2X_SHIFT	26
-#define CLK_CTRL_DIV2X_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
-#define CLK_CTRL_DIV3X_SHIFT	20
-#define CLK_CTRL_DIV3X_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
-
-#define ZYNQ_CLKMUX_SEL_0	0
-#define ZYNQ_CLKMUX_SEL_1	1
-#define ZYNQ_CLKMUX_SEL_2	2
-#define ZYNQ_CLKMUX_SEL_3	3
-
 DECLARE_GLOBAL_DATA_PTR;
  
-struct clk;
-
-/**
- * struct zynq_clk_ops:
- * @set_rate:	Function pointer to set_rate() implementation
- * @get_rate:	Function pointer to get_rate() implementation
- */
-struct zynq_clk_ops {
-	int (*set_rate)(struct clk *clk, unsigned long rate);
-	unsigned long (*get_rate)(struct clk *clk);
-};
-
-/**
- * struct clk:
- * @frequency:	Currenct frequency
- * @parent:	Parent clock
- * @flags:	Clock flags
- * @reg:	Clock control register
- * @ops:	Clock operations
- */
-struct clk {
-	unsigned long	frequency;
-	enum zynq_clk	parent;
-	unsigned int	flags;
-	u32		*reg;
-	struct zynq_clk_ops	ops;
-};
-#define ZYNQ_CLK_FLAGS_HAS_2_DIVS	1
-
-static struct clk clks[clk_max];
-
 static const char * const clk_names[clk_max] = {
 	"armpll", "ddrpll", "iopll",
 	"cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
  
  
  
  
  
  
  
  
  
@@ -90,548 +26,43 @@
 };
  
 /**
- * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
- * @srcsel:	Mux select value
- * Returns the clock identifier associated with the selected mux input.
- */
-static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
-{
-	unsigned int ret;
-
-	switch (srcsel) {
-	case ZYNQ_CLKMUX_SEL_0:
-	case ZYNQ_CLKMUX_SEL_1:
-		ret = armpll_clk;
-		break;
-	case ZYNQ_CLKMUX_SEL_2:
-		ret = ddrpll_clk;
-		break;
-	case ZYNQ_CLKMUX_SEL_3:
-		ret = iopll_clk;
-		break;
-	default:
-		ret = armpll_clk;
-		break;
-	}
-
-	return ret;
-}
-
-/**
- * ddr2x_get_rate() - Get clock rate of DDR2x clock
- * @clk:	Clock handle
- * Returns the current clock rate of @clk.
- */
-static unsigned long ddr2x_get_rate(struct clk *clk)
-{
-	u32 clk_ctrl = readl(clk->reg);
-	u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
-
-	return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
-}
-
-/**
- * ddr3x_get_rate() - Get clock rate of DDR3x clock
- * @clk:	Clock handle
- * Returns the current clock rate of @clk.
- */
-static unsigned long ddr3x_get_rate(struct clk *clk)
-{
-	u32 clk_ctrl = readl(clk->reg);
-	u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
-
-	return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
-}
-
-static void init_ddr_clocks(void)
-{
-	u32 div0, div1;
-	unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
-	u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
-
-	/* DDR2x */
-	clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
-	clks[ddr2x_clk].parent = ddrpll_clk;
-	clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
-	clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
-
-	/* DDR3x */
-	clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
-	clks[ddr3x_clk].parent = ddrpll_clk;
-	clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
-	clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
-
-	/* DCI */
-	clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
-	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
-	div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
-	clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
-	clks[dci_clk].parent = ddrpll_clk;
-	clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
-			DIV_ROUND_CLOSEST(prate, div0), div1);
-
-	gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
-}
-
-static void init_cpu_clocks(void)
-{
-	int clk_621;
-	u32 reg, div, srcsel;
-	enum zynq_clk parent;
-
-	reg = readl(&slcr_base->arm_clk_ctrl);
-	clk_621 = readl(&slcr_base->clk_621_true) & 1;
-	div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
-	srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
-	parent = __zynq_clk_cpu_get_parent(srcsel);
-
-	/* cpu clocks */
-	clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
-	clks[cpu_6or4x_clk].parent = parent;
-	clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
-			zynq_clk_get_rate(parent), div);
-
-	clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
-	clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
-	clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
-
-	clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
-	clks[cpu_2x_clk].parent = cpu_6or4x_clk;
-	clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
-			(2 + clk_621);
-
-	clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
-	clks[cpu_1x_clk].parent = cpu_6or4x_clk;
-	clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
-			(4 + 2 * clk_621);
-}
-
-/**
- * periph_calc_two_divs() - Calculate clock dividers
- * @cur_rate:	Current clock rate
- * @tgt_rate:	Target clock rate
- * @prate:	Parent clock rate
- * @div0:	First divider (output)
- * @div1:	Second divider (output)
- * Returns the actual clock rate possible.
+ * set_cpu_clk_info() - Setup clock information
  *
- * Calculates clock dividers for clocks with two 6-bit dividers.
+ * This function is called from common code after relocation and sets up the
+ * clock information.
  */
-static unsigned long periph_calc_two_divs(unsigned long cur_rate,
-		unsigned long tgt_rate, unsigned long prate, u32 *div0,
-		u32 *div1)
+int set_cpu_clk_info(void)
 {
-	long err, best_err = (long)(~0UL >> 1);
-	unsigned long rate, best_rate = 0;
-	u32 d0, d1;
+	struct clk clk;
+	struct udevice *dev;
+	ulong rate;
+	int i, ret;
  
-	for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
-		for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
-			rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
-					d1);
-			err = abs(rate - tgt_rate);
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+		DM_GET_DRIVER(zynq_clk), &dev);
+	if (ret)
+		return ret;
  
-			if (err < best_err) {
-				*div0 = d0;
-				*div1 = d1;
-				best_err = err;
-				best_rate = rate;
-			}
-		}
-	}
+	for (i = 0; i < 2; i++) {
+		clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
+		ret = clk_request(dev, &clk);
+		if (ret < 0)
+			return ret;
  
-	return best_rate;
-}
+		rate = clk_get_rate(&clk) / 1000000;
+		if (i)
+			gd->bd->bi_ddr_freq = rate;
+		else
+			gd->bd->bi_arm_freq = rate;
  
-/**
- * zynq_clk_periph_set_rate() - Set clock rate
- * @clk:	Handle of the peripheral clock
- * @rate:	New clock rate
- * Sets the clock frequency of @clk to @rate. Returns zero on success.
- */
-static int zynq_clk_periph_set_rate(struct clk *clk,
-		unsigned long rate)
-{
-	u32 ctrl, div0 = 0, div1 = 0;
-	unsigned long prate, new_rate, cur_rate = clk->frequency;
-
-	ctrl = readl(clk->reg);
-	prate = zynq_clk_get_rate(clk->parent);
-	ctrl &= ~CLK_CTRL_DIV0_MASK;
-
-	if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
-		ctrl &= ~CLK_CTRL_DIV1_MASK;
-		new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
-				&div1);
-		ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
-	} else {
-		div0 = DIV_ROUND_CLOSEST(prate, rate);
-		div0 &= ZYNQ_CLK_MAXDIV;
-		new_rate = DIV_ROUND_CLOSEST(rate, div0);
+		clk_free(&clk);
 	}
-
-	/* write new divs to hardware */
-	ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
-	writel(ctrl, clk->reg);
-
-	/* update frequency in clk framework */
-	clk->frequency = new_rate;
-
-	return 0;
-}
-
-/**
- * zynq_clk_periph_get_rate() - Get clock rate
- * @clk:	Handle of the peripheral clock
- * Returns the current clock rate of @clk.
- */
-static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
-{
-	u32 clk_ctrl = readl(clk->reg);
-	u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
-	u32 div1 = 1;
-
-	if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
-		div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
-
-	/* a register value of zero == division by 1 */
-	if (!div0)
-		div0 = 1;
-	if (!div1)
-		div1 = 1;
-
-	return
-		DIV_ROUND_CLOSEST(
-			DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
-			div1);
-}
-
-/**
- * __zynq_clk_periph_get_parent() - Decode clock multiplexer
- * @srcsel:	Mux select value
- * Returns the clock identifier associated with the selected mux input.
- */
-static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
-{
-	switch (srcsel) {
-	case ZYNQ_CLKMUX_SEL_0:
-	case ZYNQ_CLKMUX_SEL_1:
-		return iopll_clk;
-	case ZYNQ_CLKMUX_SEL_2:
-		return armpll_clk;
-	case ZYNQ_CLKMUX_SEL_3:
-		return ddrpll_clk;
-	default:
-		return 0;
-	}
-}
-
-/**
- * zynq_clk_periph_get_parent() - Decode clock multiplexer
- * @clk:	Clock handle
- * Returns the clock identifier associated with the selected mux input.
- */
-static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
-{
-	u32 clk_ctrl = readl(clk->reg);
-	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
-
-	return __zynq_clk_periph_get_parent(srcsel);
-}
-
-/**
- * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
- * @clk:	Pointer to struct clk for the clock
- * @ctrl:	Clock control register
- * @two_divs:	Indicates whether the clock features one or two dividers
- */
-static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl,
-		bool two_divs)
-{
-	clk->reg = ctrl;
-	if (two_divs)
-		clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
-	clk->parent = zynq_clk_periph_get_parent(clk);
-	clk->frequency = zynq_clk_periph_get_rate(clk);
-	clk->ops.get_rate = zynq_clk_periph_get_rate;
-	clk->ops.set_rate = zynq_clk_periph_set_rate;
-
-	return 0;
-}
-
-static void init_periph_clocks(void)
-{
-	zynq_clk_register_periph_clk(&clks[gem0_clk],
-				     &slcr_base->gem0_clk_ctrl, 1);
-	zynq_clk_register_periph_clk(&clks[gem1_clk],
-				     &slcr_base->gem1_clk_ctrl, 1);
-
-	zynq_clk_register_periph_clk(&clks[smc_clk],
-				     &slcr_base->smc_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[lqspi_clk],
-				     &slcr_base->lqspi_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[sdio0_clk],
-				     &slcr_base->sdio_clk_ctrl, 0);
-	zynq_clk_register_periph_clk(&clks[sdio1_clk],
-				     &slcr_base->sdio_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[spi0_clk],
-				     &slcr_base->spi_clk_ctrl, 0);
-	zynq_clk_register_periph_clk(&clks[spi1_clk],
-				     &slcr_base->spi_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[uart0_clk],
-				     &slcr_base->uart_clk_ctrl, 0);
-	zynq_clk_register_periph_clk(&clks[uart1_clk],
-				     &slcr_base->uart_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
-				     &slcr_base->dbg_clk_ctrl, 0);
-	zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
-				     &slcr_base->dbg_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[pcap_clk],
-				     &slcr_base->pcap_clk_ctrl, 0);
-
-	zynq_clk_register_periph_clk(&clks[fclk0_clk],
-				     &slcr_base->fpga0_clk_ctrl, 1);
-	zynq_clk_register_periph_clk(&clks[fclk1_clk],
-				     &slcr_base->fpga1_clk_ctrl, 1);
-	zynq_clk_register_periph_clk(&clks[fclk2_clk],
-				     &slcr_base->fpga2_clk_ctrl, 1);
-	zynq_clk_register_periph_clk(&clks[fclk3_clk],
-				     &slcr_base->fpga3_clk_ctrl, 1);
-}
-
-/**
- * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
- * @clk:	Pointer to struct clk for the clock
- * @ctrl:	Clock control register
- */
-static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl)
-{
-	clk->reg = ctrl;
-	clk->parent = cpu_1x_clk;
-	clk->frequency = zynq_clk_get_rate(clk->parent);
-}
-
-static void init_aper_clocks(void)
-{
-	zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[can0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[can1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-	zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-
-	zynq_clk_register_aper_clk(&clks[smc_aper_clk],
-				   &slcr_base->aper_clk_ctrl);
-}
-
-/**
- * __zynq_clk_pll_get_rate() - Get PLL rate
- * @addr:	Address of the PLL's control register
- * Returns the current PLL output rate.
- */
-static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
-{
-	u32 reg, mul, bypass;
-
-	reg = readl(addr);
-	bypass = reg & PLLCTRL_BPFORCE_MASK;
-	if (bypass)
-		mul = 1;
-	else
-		mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
-
-	return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
-}
-
-/**
- * zynq_clk_pll_get_rate() - Get PLL rate
- * @pll:	Handle of the PLL
- * Returns the current clock rate of @pll.
- */
-static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
-{
-	return __zynq_clk_pll_get_rate(pll->reg);
-}
-
-/**
- * zynq_clk_register_pll() - Set up a PLL with the framework
- * @clk:	Pointer to struct clk for the PLL
- * @ctrl:	PLL control register
- * @prate:	PLL input clock rate
- */
-static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl,
-		unsigned long prate)
-{
-	clk->reg = ctrl;
-	clk->frequency = zynq_clk_pll_get_rate(clk);
-	clk->ops.get_rate = zynq_clk_pll_get_rate;
-}
-
-/**
- * clkid_2_register() - Get clock control register
- * @id:	Clock identifier of one of the PLLs
- * Returns the address of the requested PLL's control register.
- */
-static u32 *clkid_2_register(enum zynq_clk id)
-{
-	switch (id) {
-	case armpll_clk:
-		return &slcr_base->arm_pll_ctrl;
-	case ddrpll_clk:
-		return &slcr_base->ddr_pll_ctrl;
-	case iopll_clk:
-		return &slcr_base->io_pll_ctrl;
-	default:
-		return &slcr_base->io_pll_ctrl;
-	}
-}
-
-/* API */
-/**
- * zynq_clk_early_init() - Early init for the clock framework
- *
- * This function is called from before relocation and sets up the CPU clock
- * frequency in the global data struct.
- */
-void zynq_clk_early_init(void)
-{
-	u32 reg = readl(&slcr_base->arm_clk_ctrl);
-	u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
-	u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
-	enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
-	u32 *pllreg = clkid_2_register(parent);
-	unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
-
-	if (!div)
-		div = 1;
-
-	gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
-}
-
-/**
- * get_uart_clk() - Get UART input frequency
- * @dev_index:	UART ID
- * Returns UART input clock frequency in Hz.
- *
- * Compared to zynq_clk_get_rate() this function is designed to work before
- * relocation and can be called when the serial UART is set up.
- */
-unsigned long get_uart_clk(int dev_index)
-{
-	u32 reg = readl(&slcr_base->uart_clk_ctrl);
-	u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
-	u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
-	enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
-	u32 *pllreg = clkid_2_register(parent);
-	unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
-
-	if (!div)
-		div = 1;
-
-	return DIV_ROUND_CLOSEST(prate, div);
-}
-
-/**
- * set_cpu_clk_info() - Initialize clock framework
- * Always returns zero.
- *
- * This function is called from common code after relocation and sets up the
- * clock framework. The framework must not be used before this function had been
- * called.
- */
-int set_cpu_clk_info(void)
-{
-	zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
-			      CONFIG_ZYNQ_PS_CLK_FREQ);
-	zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
-			      CONFIG_ZYNQ_PS_CLK_FREQ);
-	zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
-			      CONFIG_ZYNQ_PS_CLK_FREQ);
-
-	init_ddr_clocks();
-	init_cpu_clocks();
-	init_periph_clocks();
-	init_aper_clocks();
-
-	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
 	gd->bd->bi_dsp_freq = 0;
  
 	return 0;
 }
  
 /**
- * zynq_clk_get_rate() - Get clock rate
- * @clk:	Clock identifier
- * Returns the current clock rate of @clk on success or zero for an invalid
- * clock id.
- */
-unsigned long zynq_clk_get_rate(enum zynq_clk clk)
-{
-	if (clk < 0 || clk >= clk_max)
-		return 0;
-
-	return clks[clk].frequency;
-}
-
-/**
- * zynq_clk_set_rate() - Set clock rate
- * @clk:	Clock identifier
- * @rate:	Requested clock rate
- * Passes on the return value from the clock's set_rate() function or negative
- * errno.
- */
-int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
-{
-	if (clk < 0 || clk >= clk_max)
-		return -ENODEV;
-
-	if (clks[clk].ops.set_rate)
-		return clks[clk].ops.set_rate(&clks[clk], rate);
-
-	return -ENXIO;
-}
-
-/**
  * soc_clk_dump() - Print clock frequencies
  * Returns zero on success
  *
  
  
@@ -639,13 +70,35 @@
  */
 int soc_clk_dump(void)
 {
-	int i;
+	struct udevice *dev;
+	int i, ret;
  
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+		DM_GET_DRIVER(zynq_clk), &dev);
+	if (ret)
+		return ret;
+
 	printf("clk\t\tfrequency\n");
 	for (i = 0; i < clk_max; i++) {
 		const char *name = clk_names[i];
-		if (name)
-			printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
+		if (name) {
+			struct clk clk;
+			unsigned long rate;
+
+			clk.id = i;
+			ret = clk_request(dev, &clk);
+			if (ret < 0)
+				return ret;
+
+			rate = clk_get_rate(&clk);
+
+			clk_free(&clk);
+
+			if (rate == (unsigned long)-ENOSYS)
+				printf("%10s%20s\n", name, "unknown");
+			else
+				printf("%10s%20lu\n", name, rate);
+		}
 	}
  
 	return 0;
@@ -35,7 +35,6 @@
 	writel(0xC, &slcr_base->ddr_urgent);
 #endif
 #endif
-	zynq_clk_early_init();
 	zynq_slcr_lock();
  
 	return 0;
@@ -20,10 +20,5 @@
 	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
 	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
  
-void zynq_clk_early_init(void);
-int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
-unsigned long zynq_clk_get_rate(enum zynq_clk clk);
-unsigned long get_uart_clk(int dev_id);
-
 #endif
@@ -10,7 +10,6 @@
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
@@ -9,7 +9,6 @@
 #include <malloc.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
  
 #define SLCR_LOCK_MAGIC		0x767B
 #define SLCR_UNLOCK_MAGIC	0xDF0D
@@ -122,27 +121,6 @@
 	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
  
 	writel(1, &slcr_base->pss_rst_ctrl);
-}
-
-/* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
-{
-	int ret;
-
-	zynq_slcr_unlock();
-
-	if (gem_id > 1) {
-		printf("Non existing GEM id %d\n", gem_id);
-		goto out;
-	}
-
-	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
-	if (ret)
-		goto out;
-
-	udelay(100000);
-out:
-	zynq_slcr_lock();
 }
  
 void zynq_slcr_devcfg_disable(void)
@@ -61,7 +61,6 @@
 			(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
 			SCUTIMER_CONTROL_ENABLE_MASK;
  
-#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	struct udevice *dev;
 	struct clk clk;
 	int ret;
@@ -79,7 +78,6 @@
 	gd->cpu_clk = clk_get_rate(&clk);
  
 	clk_free(&clk);
-#endif
  
 	gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
  
@@ -181,9 +181,7 @@
 	struct phy_device *phydev;
 	int phy_of_handle;
 	struct mii_dev *bus;
-#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	struct clk clk;
-#endif
 };
  
 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -456,7 +454,6 @@
 		break;
 	}
  
-#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	ret = clk_set_rate(&priv->clk, clk_rate);
 	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
 		dev_err(dev, "failed to set tx clock rate\n");
@@ -468,10 +465,6 @@
 		dev_err(dev, "failed to enable tx clock\n");
 		return ret;
 	}
-#else
-	zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
-				ZYNQ_GEM_BASEADDR0, clk_rate);
-#endif
  
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);
  
@@ -644,13 +637,11 @@
 	priv->tx_bd = (struct emac_bd *)bd_space;
 	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
  
-#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to get clock\n");
 		return -EINVAL;
 	}
-#endif
  
 	priv->bus = mdio_alloc();
 	priv->bus->read = zynq_gem_miiphy_read;
@@ -15,7 +15,6 @@
 #include <asm/io.h>
 #include <linux/compiler.h>
 #include <serial.h>
-#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
  
 DECLARE_GLOBAL_DATA_PTR;
@@ -111,7 +110,6 @@
 	struct zynq_uart_priv *priv = dev_get_priv(dev);
 	unsigned long clock;
  
-#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
 	int ret;
 	struct clk clk;
  
@@ -133,9 +131,7 @@
 		dev_err(dev, "failed to enable clock\n");
 		return ret;
 	}
-#else
-	clock = get_uart_clk(0);
-#endif
+
 	_uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
  
 	return 0;
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_TOPIC_MIAMI_H
 #define __CONFIG_TOPIC_MIAMI_H
  
-#define CONFIG_ZYNQ_PS_CLK_FREQ		33333333UL
-
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
  
@@ -20,9 +20,6 @@
 #define CONFIG_DISPLAY
 #define CONFIG_I2C_EDID
  
-/* Define ZYBO PS Clock Frequency to 50MHz */
-#define CONFIG_ZYNQ_PS_CLK_FREQ	50000000UL
-
 #include <configs/zynq-common.h>
  
 #endif /* __CONFIG_ZYNQ_ZYBO_H */
@@ -6933,7 +6933,6 @@
 CONFIG_ZYNQ_HISPD_BROKEN
 CONFIG_ZYNQ_I2C0
 CONFIG_ZYNQ_I2C1
-CONFIG_ZYNQ_PS_CLK_FREQ
 CONFIG_ZYNQ_SDHCI0
 CONFIG_ZYNQ_SDHCI1
 CONFIG_ZYNQ_SDHCI_MAX_FREQ
...	...	@@ -714,6 +714,9 @@
714	714	select SPL_SEPARATE_BSS if SPL
715	715	select DM_USB if USB
716	716	select BLK
	717	+ select CLK
	718	+ select SPL_CLK
	719	+ select CLK_ZYNQ
717	720
718	721	config ARCH_ZYNQMP
719	722	bool "Support Xilinx ZynqMP Platform"
...	...	@@ -248,12 +248,14 @@
248	248	};
249	249
250	250	slcr: slcr@f8000000 {
	251	+ u-boot,dm-pre-reloc;
251	252	#address-cells = <1>;
252	253	#size-cells = <1>;
253	254	compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
254	255	reg = <0xF8000000 0x1000>;
255	256	ranges;
256	257	clkc: clkc@100 {
	258	+ u-boot,dm-pre-reloc;
257	259	#clock-cells = <1>;
258	260	compatible = "xlnx,ps7-clkc";
259	261	fclk-enable = <0>;
...	...	@@ -4,77 +4,13 @@
4	4	*
5	5	* SPDX-License-Identifier: GPL-2.0+
6	6	*/
	7	+#include <clk.h>
7	8	#include <common.h>
8		-#include <errno.h>
9		-#include <asm/io.h>
10		-#include <asm/arch/hardware.h>
	9	+#include <dm.h>
11	10	#include <asm/arch/clk.h>
12	11
13		-/* Board oscillator frequency */
14		-#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
15		-# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
16		-#endif
17		-
18		-/* Register bitfield defines */
19		-#define PLLCTRL_FBDIV_MASK 0x7f000
20		-#define PLLCTRL_FBDIV_SHIFT 12
21		-#define PLLCTRL_BPFORCE_MASK (1 << 4)
22		-#define PLLCTRL_PWRDWN_MASK 2
23		-#define PLLCTRL_PWRDWN_SHIFT 1
24		-#define PLLCTRL_RESET_MASK 1
25		-#define PLLCTRL_RESET_SHIFT 0
26		-
27		-#define ZYNQ_CLK_MAXDIV 0x3f
28		-#define CLK_CTRL_DIV1_SHIFT 20
29		-#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
30		-#define CLK_CTRL_DIV0_SHIFT 8
31		-#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
32		-#define CLK_CTRL_SRCSEL_SHIFT 4
33		-#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
34		-
35		-#define CLK_CTRL_DIV2X_SHIFT 26
36		-#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
37		-#define CLK_CTRL_DIV3X_SHIFT 20
38		-#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
39		-
40		-#define ZYNQ_CLKMUX_SEL_0 0
41		-#define ZYNQ_CLKMUX_SEL_1 1
42		-#define ZYNQ_CLKMUX_SEL_2 2
43		-#define ZYNQ_CLKMUX_SEL_3 3
44		-
45	12	DECLARE_GLOBAL_DATA_PTR;
46	13
47		-struct clk;
48		-
49		-/**
50		- * struct zynq_clk_ops:
51		- * @set_rate: Function pointer to set_rate() implementation
52		- * @get_rate: Function pointer to get_rate() implementation
53		- */
54		-struct zynq_clk_ops {
55		- int (set_rate)(struct clk clk, unsigned long rate);
56		- unsigned long (get_rate)(struct clk clk);
57		-};
58		-
59		-/**
60		- * struct clk:
61		- * @frequency: Currenct frequency
62		- * @parent: Parent clock
63		- * @flags: Clock flags
64		- * @reg: Clock control register
65		- * @ops: Clock operations
66		- */
67		-struct clk {
68		- unsigned long frequency;
69		- enum zynq_clk parent;
70		- unsigned int flags;
71		- u32 *reg;
72		- struct zynq_clk_ops ops;
73		-};
74		-#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
75		-
76		-static struct clk clks[clk_max];
77		-
78	14	static const char * const clk_names[clk_max] = {
79	15	"armpll", "ddrpll", "iopll",
80	16	"cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
81	17
82	18
83	19
84	20
85	21
86	22
87	23
88	24
89	25
...	...	@@ -90,548 +26,43 @@
90	26	};
91	27
92	28	/**
93		- * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
94		- * @srcsel: Mux select value
95		- * Returns the clock identifier associated with the selected mux input.
96		- */
97		-static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
98		-{
99		- unsigned int ret;
100		-
101		- switch (srcsel) {
102		- case ZYNQ_CLKMUX_SEL_0:
103		- case ZYNQ_CLKMUX_SEL_1:
104		- ret = armpll_clk;
105		- break;
106		- case ZYNQ_CLKMUX_SEL_2:
107		- ret = ddrpll_clk;
108		- break;
109		- case ZYNQ_CLKMUX_SEL_3:
110		- ret = iopll_clk;
111		- break;
112		- default:
113		- ret = armpll_clk;
114		- break;
115		- }
116		-
117		- return ret;
118		-}
119		-
120		-/**
121		- * ddr2x_get_rate() - Get clock rate of DDR2x clock
122		- * @clk: Clock handle
123		- * Returns the current clock rate of @clk.
124		- */
125		-static unsigned long ddr2x_get_rate(struct clk *clk)
126		-{
127		- u32 clk_ctrl = readl(clk->reg);
128		- u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
129		-
130		- return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
131		-}
132		-
133		-/**
134		- * ddr3x_get_rate() - Get clock rate of DDR3x clock
135		- * @clk: Clock handle
136		- * Returns the current clock rate of @clk.
137		- */
138		-static unsigned long ddr3x_get_rate(struct clk *clk)
139		-{
140		- u32 clk_ctrl = readl(clk->reg);
141		- u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
142		-
143		- return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
144		-}
145		-
146		-static void init_ddr_clocks(void)
147		-{
148		- u32 div0, div1;
149		- unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
150		- u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
151		-
152		- /* DDR2x */
153		- clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
154		- clks[ddr2x_clk].parent = ddrpll_clk;
155		- clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
156		- clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
157		-
158		- /* DDR3x */
159		- clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
160		- clks[ddr3x_clk].parent = ddrpll_clk;
161		- clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
162		- clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
163		-
164		- /* DCI */
165		- clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
166		- div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
167		- div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
168		- clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
169		- clks[dci_clk].parent = ddrpll_clk;
170		- clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
171		- DIV_ROUND_CLOSEST(prate, div0), div1);
172		-
173		- gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
174		-}
175		-
176		-static void init_cpu_clocks(void)
177		-{
178		- int clk_621;
179		- u32 reg, div, srcsel;
180		- enum zynq_clk parent;
181		-
182		- reg = readl(&slcr_base->arm_clk_ctrl);
183		- clk_621 = readl(&slcr_base->clk_621_true) & 1;
184		- div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
185		- srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
186		- parent = __zynq_clk_cpu_get_parent(srcsel);
187		-
188		- /* cpu clocks */
189		- clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
190		- clks[cpu_6or4x_clk].parent = parent;
191		- clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
192		- zynq_clk_get_rate(parent), div);
193		-
194		- clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
195		- clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
196		- clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
197		-
198		- clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
199		- clks[cpu_2x_clk].parent = cpu_6or4x_clk;
200		- clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
201		- (2 + clk_621);
202		-
203		- clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
204		- clks[cpu_1x_clk].parent = cpu_6or4x_clk;
205		- clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
206		- (4 + 2 * clk_621);
207		-}
208		-
209		-/**
210		- * periph_calc_two_divs() - Calculate clock dividers
211		- * @cur_rate: Current clock rate
212		- * @tgt_rate: Target clock rate
213		- * @prate: Parent clock rate
214		- * @div0: First divider (output)
215		- * @div1: Second divider (output)
216		- * Returns the actual clock rate possible.
	29	+ * set_cpu_clk_info() - Setup clock information
217	30	*
218		- * Calculates clock dividers for clocks with two 6-bit dividers.
	31	+ * This function is called from common code after relocation and sets up the
	32	+ * clock information.
219	33	*/
220		-static unsigned long periph_calc_two_divs(unsigned long cur_rate,
221		- unsigned long tgt_rate, unsigned long prate, u32 *div0,
222		- u32 *div1)
	34	+int set_cpu_clk_info(void)
223	35	{
224		- long err, best_err = (long)(~0UL >> 1);
225		- unsigned long rate, best_rate = 0;
226		- u32 d0, d1;
	36	+ struct clk clk;
	37	+ struct udevice *dev;
	38	+ ulong rate;
	39	+ int i, ret;
227	40
228		- for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
229		- for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
230		- rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
231		- d1);
232		- err = abs(rate - tgt_rate);
	41	+ ret = uclass_get_device_by_driver(UCLASS_CLK,
	42	+ DM_GET_DRIVER(zynq_clk), &dev);
	43	+ if (ret)
	44	+ return ret;
233	45
234		- if (err < best_err) {
235		- *div0 = d0;
236		- *div1 = d1;
237		- best_err = err;
238		- best_rate = rate;
239		- }
240		- }
241		- }
	46	+ for (i = 0; i < 2; i++) {
	47	+ clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
	48	+ ret = clk_request(dev, &clk);
	49	+ if (ret < 0)
	50	+ return ret;
242	51
243		- return best_rate;
244		-}
	52	+ rate = clk_get_rate(&clk) / 1000000;
	53	+ if (i)
	54	+ gd->bd->bi_ddr_freq = rate;
	55	+ else
	56	+ gd->bd->bi_arm_freq = rate;
245	57
246		-/**
247		- * zynq_clk_periph_set_rate() - Set clock rate
248		- * @clk: Handle of the peripheral clock
249		- * @rate: New clock rate
250		- * Sets the clock frequency of @clk to @rate. Returns zero on success.
251		- */
252		-static int zynq_clk_periph_set_rate(struct clk *clk,
253		- unsigned long rate)
254		-{
255		- u32 ctrl, div0 = 0, div1 = 0;
256		- unsigned long prate, new_rate, cur_rate = clk->frequency;
257		-
258		- ctrl = readl(clk->reg);
259		- prate = zynq_clk_get_rate(clk->parent);
260		- ctrl &= ~CLK_CTRL_DIV0_MASK;
261		-
262		- if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
263		- ctrl &= ~CLK_CTRL_DIV1_MASK;
264		- new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
265		- &div1);
266		- ctrl \|= div1 << CLK_CTRL_DIV1_SHIFT;
267		- } else {
268		- div0 = DIV_ROUND_CLOSEST(prate, rate);
269		- div0 &= ZYNQ_CLK_MAXDIV;
270		- new_rate = DIV_ROUND_CLOSEST(rate, div0);
	58	+ clk_free(&clk);
271	59	}
272		-
273		- /* write new divs to hardware */
274		- ctrl \|= div0 << CLK_CTRL_DIV0_SHIFT;
275		- writel(ctrl, clk->reg);
276		-
277		- /* update frequency in clk framework */
278		- clk->frequency = new_rate;
279		-
280		- return 0;
281		-}
282		-
283		-/**
284		- * zynq_clk_periph_get_rate() - Get clock rate
285		- * @clk: Handle of the peripheral clock
286		- * Returns the current clock rate of @clk.
287		- */
288		-static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
289		-{
290		- u32 clk_ctrl = readl(clk->reg);
291		- u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
292		- u32 div1 = 1;
293		-
294		- if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
295		- div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
296		-
297		- /* a register value of zero == division by 1 */
298		- if (!div0)
299		- div0 = 1;
300		- if (!div1)
301		- div1 = 1;
302		-
303		- return
304		- DIV_ROUND_CLOSEST(
305		- DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
306		- div1);
307		-}
308		-
309		-/**
310		- * __zynq_clk_periph_get_parent() - Decode clock multiplexer
311		- * @srcsel: Mux select value
312		- * Returns the clock identifier associated with the selected mux input.
313		- */
314		-static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
315		-{
316		- switch (srcsel) {
317		- case ZYNQ_CLKMUX_SEL_0:
318		- case ZYNQ_CLKMUX_SEL_1:
319		- return iopll_clk;
320		- case ZYNQ_CLKMUX_SEL_2:
321		- return armpll_clk;
322		- case ZYNQ_CLKMUX_SEL_3:
323		- return ddrpll_clk;
324		- default:
325		- return 0;
326		- }
327		-}
328		-
329		-/**
330		- * zynq_clk_periph_get_parent() - Decode clock multiplexer
331		- * @clk: Clock handle
332		- * Returns the clock identifier associated with the selected mux input.
333		- */
334		-static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
335		-{
336		- u32 clk_ctrl = readl(clk->reg);
337		- u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
338		-
339		- return __zynq_clk_periph_get_parent(srcsel);
340		-}
341		-
342		-/**
343		- * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
344		- * @clk: Pointer to struct clk for the clock
345		- * @ctrl: Clock control register
346		- * @two_divs: Indicates whether the clock features one or two dividers
347		- */
348		-static int zynq_clk_register_periph_clk(struct clk clk, u32 ctrl,
349		- bool two_divs)
350		-{
351		- clk->reg = ctrl;
352		- if (two_divs)
353		- clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
354		- clk->parent = zynq_clk_periph_get_parent(clk);
355		- clk->frequency = zynq_clk_periph_get_rate(clk);
356		- clk->ops.get_rate = zynq_clk_periph_get_rate;
357		- clk->ops.set_rate = zynq_clk_periph_set_rate;
358		-
359		- return 0;
360		-}
361		-
362		-static void init_periph_clocks(void)
363		-{
364		- zynq_clk_register_periph_clk(&clks[gem0_clk],
365		- &slcr_base->gem0_clk_ctrl, 1);
366		- zynq_clk_register_periph_clk(&clks[gem1_clk],
367		- &slcr_base->gem1_clk_ctrl, 1);
368		-
369		- zynq_clk_register_periph_clk(&clks[smc_clk],
370		- &slcr_base->smc_clk_ctrl, 0);
371		-
372		- zynq_clk_register_periph_clk(&clks[lqspi_clk],
373		- &slcr_base->lqspi_clk_ctrl, 0);
374		-
375		- zynq_clk_register_periph_clk(&clks[sdio0_clk],
376		- &slcr_base->sdio_clk_ctrl, 0);
377		- zynq_clk_register_periph_clk(&clks[sdio1_clk],
378		- &slcr_base->sdio_clk_ctrl, 0);
379		-
380		- zynq_clk_register_periph_clk(&clks[spi0_clk],
381		- &slcr_base->spi_clk_ctrl, 0);
382		- zynq_clk_register_periph_clk(&clks[spi1_clk],
383		- &slcr_base->spi_clk_ctrl, 0);
384		-
385		- zynq_clk_register_periph_clk(&clks[uart0_clk],
386		- &slcr_base->uart_clk_ctrl, 0);
387		- zynq_clk_register_periph_clk(&clks[uart1_clk],
388		- &slcr_base->uart_clk_ctrl, 0);
389		-
390		- zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
391		- &slcr_base->dbg_clk_ctrl, 0);
392		- zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
393		- &slcr_base->dbg_clk_ctrl, 0);
394		-
395		- zynq_clk_register_periph_clk(&clks[pcap_clk],
396		- &slcr_base->pcap_clk_ctrl, 0);
397		-
398		- zynq_clk_register_periph_clk(&clks[fclk0_clk],
399		- &slcr_base->fpga0_clk_ctrl, 1);
400		- zynq_clk_register_periph_clk(&clks[fclk1_clk],
401		- &slcr_base->fpga1_clk_ctrl, 1);
402		- zynq_clk_register_periph_clk(&clks[fclk2_clk],
403		- &slcr_base->fpga2_clk_ctrl, 1);
404		- zynq_clk_register_periph_clk(&clks[fclk3_clk],
405		- &slcr_base->fpga3_clk_ctrl, 1);
406		-}
407		-
408		-/**
409		- * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
410		- * @clk: Pointer to struct clk for the clock
411		- * @ctrl: Clock control register
412		- */
413		-static void zynq_clk_register_aper_clk(struct clk clk, u32 ctrl)
414		-{
415		- clk->reg = ctrl;
416		- clk->parent = cpu_1x_clk;
417		- clk->frequency = zynq_clk_get_rate(clk->parent);
418		-}
419		-
420		-static void init_aper_clocks(void)
421		-{
422		- zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
423		- &slcr_base->aper_clk_ctrl);
424		- zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
425		- &slcr_base->aper_clk_ctrl);
426		-
427		- zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
428		- &slcr_base->aper_clk_ctrl);
429		- zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
430		- &slcr_base->aper_clk_ctrl);
431		-
432		- zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
433		- &slcr_base->aper_clk_ctrl);
434		- zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
435		- &slcr_base->aper_clk_ctrl);
436		-
437		- zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
438		- &slcr_base->aper_clk_ctrl);
439		- zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
440		- &slcr_base->aper_clk_ctrl);
441		-
442		- zynq_clk_register_aper_clk(&clks[can0_aper_clk],
443		- &slcr_base->aper_clk_ctrl);
444		- zynq_clk_register_aper_clk(&clks[can1_aper_clk],
445		- &slcr_base->aper_clk_ctrl);
446		-
447		- zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
448		- &slcr_base->aper_clk_ctrl);
449		- zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
450		- &slcr_base->aper_clk_ctrl);
451		-
452		- zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
453		- &slcr_base->aper_clk_ctrl);
454		- zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
455		- &slcr_base->aper_clk_ctrl);
456		-
457		- zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
458		- &slcr_base->aper_clk_ctrl);
459		-
460		- zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
461		- &slcr_base->aper_clk_ctrl);
462		-
463		- zynq_clk_register_aper_clk(&clks[smc_aper_clk],
464		- &slcr_base->aper_clk_ctrl);
465		-}
466		-
467		-/**
468		- * __zynq_clk_pll_get_rate() - Get PLL rate
469		- * @addr: Address of the PLL's control register
470		- * Returns the current PLL output rate.
471		- */
472		-static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
473		-{
474		- u32 reg, mul, bypass;
475		-
476		- reg = readl(addr);
477		- bypass = reg & PLLCTRL_BPFORCE_MASK;
478		- if (bypass)
479		- mul = 1;
480		- else
481		- mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
482		-
483		- return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
484		-}
485		-
486		-/**
487		- * zynq_clk_pll_get_rate() - Get PLL rate
488		- * @pll: Handle of the PLL
489		- * Returns the current clock rate of @pll.
490		- */
491		-static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
492		-{
493		- return __zynq_clk_pll_get_rate(pll->reg);
494		-}
495		-
496		-/**
497		- * zynq_clk_register_pll() - Set up a PLL with the framework
498		- * @clk: Pointer to struct clk for the PLL
499		- * @ctrl: PLL control register
500		- * @prate: PLL input clock rate
501		- */
502		-static void zynq_clk_register_pll(struct clk clk, u32 ctrl,
503		- unsigned long prate)
504		-{
505		- clk->reg = ctrl;
506		- clk->frequency = zynq_clk_pll_get_rate(clk);
507		- clk->ops.get_rate = zynq_clk_pll_get_rate;
508		-}
509		-
510		-/**
511		- * clkid_2_register() - Get clock control register
512		- * @id: Clock identifier of one of the PLLs
513		- * Returns the address of the requested PLL's control register.
514		- */
515		-static u32 *clkid_2_register(enum zynq_clk id)
516		-{
517		- switch (id) {
518		- case armpll_clk:
519		- return &slcr_base->arm_pll_ctrl;
520		- case ddrpll_clk:
521		- return &slcr_base->ddr_pll_ctrl;
522		- case iopll_clk:
523		- return &slcr_base->io_pll_ctrl;
524		- default:
525		- return &slcr_base->io_pll_ctrl;
526		- }
527		-}
528		-
529		-/* API */
530		-/**
531		- * zynq_clk_early_init() - Early init for the clock framework
532		- *
533		- * This function is called from before relocation and sets up the CPU clock
534		- * frequency in the global data struct.
535		- */
536		-void zynq_clk_early_init(void)
537		-{
538		- u32 reg = readl(&slcr_base->arm_clk_ctrl);
539		- u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
540		- u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
541		- enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
542		- u32 *pllreg = clkid_2_register(parent);
543		- unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
544		-
545		- if (!div)
546		- div = 1;
547		-
548		- gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
549		-}
550		-
551		-/**
552		- * get_uart_clk() - Get UART input frequency
553		- * @dev_index: UART ID
554		- * Returns UART input clock frequency in Hz.
555		- *
556		- * Compared to zynq_clk_get_rate() this function is designed to work before
557		- * relocation and can be called when the serial UART is set up.
558		- */
559		-unsigned long get_uart_clk(int dev_index)
560		-{
561		- u32 reg = readl(&slcr_base->uart_clk_ctrl);
562		- u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
563		- u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
564		- enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
565		- u32 *pllreg = clkid_2_register(parent);
566		- unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
567		-
568		- if (!div)
569		- div = 1;
570		-
571		- return DIV_ROUND_CLOSEST(prate, div);
572		-}
573		-
574		-/**
575		- * set_cpu_clk_info() - Initialize clock framework
576		- * Always returns zero.
577		- *
578		- * This function is called from common code after relocation and sets up the
579		- * clock framework. The framework must not be used before this function had been
580		- * called.
581		- */
582		-int set_cpu_clk_info(void)
583		-{
584		- zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
585		- CONFIG_ZYNQ_PS_CLK_FREQ);
586		- zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
587		- CONFIG_ZYNQ_PS_CLK_FREQ);
588		- zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
589		- CONFIG_ZYNQ_PS_CLK_FREQ);
590		-
591		- init_ddr_clocks();
592		- init_cpu_clocks();
593		- init_periph_clocks();
594		- init_aper_clocks();
595		-
596		- gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
597	60	gd->bd->bi_dsp_freq = 0;
598	61
599	62	return 0;
600	63	}
601	64
602	65	/**
603		- * zynq_clk_get_rate() - Get clock rate
604		- * @clk: Clock identifier
605		- * Returns the current clock rate of @clk on success or zero for an invalid
606		- * clock id.
607		- */
608		-unsigned long zynq_clk_get_rate(enum zynq_clk clk)
609		-{
610		- if (clk < 0 \|\| clk >= clk_max)
611		- return 0;
612		-
613		- return clks[clk].frequency;
614		-}
615		-
616		-/**
617		- * zynq_clk_set_rate() - Set clock rate
618		- * @clk: Clock identifier
619		- * @rate: Requested clock rate
620		- * Passes on the return value from the clock's set_rate() function or negative
621		- * errno.
622		- */
623		-int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
624		-{
625		- if (clk < 0 \|\| clk >= clk_max)
626		- return -ENODEV;
627		-
628		- if (clks[clk].ops.set_rate)
629		- return clks[clk].ops.set_rate(&clks[clk], rate);
630		-
631		- return -ENXIO;
632		-}
633		-
634		-/**
635	66	* soc_clk_dump() - Print clock frequencies
636	67	* Returns zero on success
637	68	*
638	69
639	70
...	...	@@ -639,13 +70,35 @@
639	70	*/
640	71	int soc_clk_dump(void)
641	72	{
642		- int i;
	73	+ struct udevice *dev;
	74	+ int i, ret;
643	75
	76	+ ret = uclass_get_device_by_driver(UCLASS_CLK,
	77	+ DM_GET_DRIVER(zynq_clk), &dev);
	78	+ if (ret)
	79	+ return ret;
	80	+
644	81	printf("clk\t\tfrequency\n");
645	82	for (i = 0; i < clk_max; i++) {
646	83	const char *name = clk_names[i];
647		- if (name)
648		- printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
	84	+ if (name) {
	85	+ struct clk clk;
	86	+ unsigned long rate;
	87	+
	88	+ clk.id = i;
	89	+ ret = clk_request(dev, &clk);
	90	+ if (ret < 0)
	91	+ return ret;
	92	+
	93	+ rate = clk_get_rate(&clk);
	94	+
	95	+ clk_free(&clk);
	96	+
	97	+ if (rate == (unsigned long)-ENOSYS)
	98	+ printf("%10s%20s\n", name, "unknown");
	99	+ else
	100	+ printf("%10s%20lu\n", name, rate);
	101	+ }
649	102	}
650	103
651	104	return 0;
...	...	@@ -35,7 +35,6 @@
35	35	writel(0xC, &slcr_base->ddr_urgent);
36	36	#endif
37	37	#endif
38		- zynq_clk_early_init();
39	38	zynq_slcr_lock();
40	39
41	40	return 0;
...	...	@@ -20,10 +20,5 @@
20	20	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
21	21	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
22	22
23		-void zynq_clk_early_init(void);
24		-int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
25		-unsigned long zynq_clk_get_rate(enum zynq_clk clk);
26		-unsigned long get_uart_clk(int dev_id);
27		-
28	23	#endif
...	...	@@ -10,7 +10,6 @@
10	10	extern void zynq_slcr_lock(void);
11	11	extern void zynq_slcr_unlock(void);
12	12	extern void zynq_slcr_cpu_reset(void);
13		-extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
14	13	extern void zynq_slcr_devcfg_disable(void);
15	14	extern void zynq_slcr_devcfg_enable(void);
16	15	extern u32 zynq_slcr_get_boot_mode(void);
...	...	@@ -9,7 +9,6 @@
9	9	#include <malloc.h>
10	10	#include <asm/arch/hardware.h>
11	11	#include <asm/arch/sys_proto.h>
12		-#include <asm/arch/clk.h>
13	12
14	13	#define SLCR_LOCK_MAGIC 0x767B
15	14	#define SLCR_UNLOCK_MAGIC 0xDF0D
...	...	@@ -122,27 +121,6 @@
122	121	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
123	122
124	123	writel(1, &slcr_base->pss_rst_ctrl);
125		-}
126		-
127		-/* Setup clk for network */
128		-void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
129		-{
130		- int ret;
131		-
132		- zynq_slcr_unlock();
133		-
134		- if (gem_id > 1) {
135		- printf("Non existing GEM id %d\n", gem_id);
136		- goto out;
137		- }
138		-
139		- ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
140		- if (ret)
141		- goto out;
142		-
143		- udelay(100000);
144		-out:
145		- zynq_slcr_lock();
146	124	}
147	125
148	126	void zynq_slcr_devcfg_disable(void)
...	...	@@ -61,7 +61,6 @@
61	61	(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) \|
62	62	SCUTIMER_CONTROL_ENABLE_MASK;
63	63
64		-#if defined(CONFIG_CLK) \|\| defined(CONFIG_SPL_CLK)
65	64	struct udevice *dev;
66	65	struct clk clk;
67	66	int ret;
...	...	@@ -79,7 +78,6 @@
79	78	gd->cpu_clk = clk_get_rate(&clk);
80	79
81	80	clk_free(&clk);
82		-#endif
83	81
84	82	gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
85	83
...	...	@@ -181,9 +181,7 @@
181	181	struct phy_device *phydev;
182	182	int phy_of_handle;
183	183	struct mii_dev *bus;
184		-#if defined(CONFIG_CLK) \|\| defined(CONFIG_SPL_CLK)
185	184	struct clk clk;
186		-#endif
187	185	};
188	186
189	187	static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
...	...	@@ -456,7 +454,6 @@
456	454	break;
457	455	}
458	456
459		-#if defined(CONFIG_CLK) \|\| defined(CONFIG_SPL_CLK)
460	457	ret = clk_set_rate(&priv->clk, clk_rate);
461	458	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
462	459	dev_err(dev, "failed to set tx clock rate\n");
...	...	@@ -468,10 +465,6 @@
468	465	dev_err(dev, "failed to enable tx clock\n");
469	466	return ret;
470	467	}
471		-#else
472		- zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
473		- ZYNQ_GEM_BASEADDR0, clk_rate);
474		-#endif
475	468
476	469	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK \|
477	470	ZYNQ_GEM_NWCTRL_TXEN_MASK);
478	471
...	...	@@ -644,13 +637,11 @@
644	637	priv->tx_bd = (struct emac_bd *)bd_space;
645	638	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
646	639
647		-#if defined(CONFIG_CLK) \|\| defined(CONFIG_SPL_CLK)
648	640	ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
649	641	if (ret < 0) {
650	642	dev_err(dev, "failed to get clock\n");
651	643	return -EINVAL;
652	644	}
653		-#endif
654	645
655	646	priv->bus = mdio_alloc();
656	647	priv->bus->read = zynq_gem_miiphy_read;
...	...	@@ -15,7 +15,6 @@
15	15	#include <asm/io.h>
16	16	#include <linux/compiler.h>
17	17	#include <serial.h>
18		-#include <asm/arch/clk.h>
19	18	#include <asm/arch/hardware.h>
20	19
21	20	DECLARE_GLOBAL_DATA_PTR;
...	...	@@ -111,7 +110,6 @@
111	110	struct zynq_uart_priv *priv = dev_get_priv(dev);
112	111	unsigned long clock;
113	112
114		-#if defined(CONFIG_CLK) \|\| defined(CONFIG_SPL_CLK)
115	113	int ret;
116	114	struct clk clk;
117	115
...	...	@@ -133,9 +131,7 @@
133	131	dev_err(dev, "failed to enable clock\n");
134	132	return ret;
135	133	}
136		-#else
137		- clock = get_uart_clk(0);
138		-#endif
	134	+
139	135	_uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
140	136
141	137	return 0;