board: freescale: powerpc: add support for all RGMII modes

Make sure are RGMII internal delay modes are covered. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>

board: freescale: powerpc: add support for all RGMII modes
Make sure are RGMII internal delay modes are covered. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Madalin Bucur · Priyanka Jain
1 parent 919feb7911
Showing 11 changed files with 96 additions and 19 deletions Side-by-side Diff
board/freescale/corenet_ds/eth_hydra.c
board/freescale/corenet_ds/eth_p4080.c
board/freescale/corenet_ds/eth_superhydra.c
board/freescale/p2041rdb/eth.c
board/freescale/t102xqds/eth_t102xqds.c
board/freescale/t102xrdb/eth_t102xrdb.c
board/freescale/t1040qds/eth.c
board/freescale/t104xrdb/eth.c
board/freescale/t208xqds/eth_t208xqds.c
board/freescale/t208xrdb/eth_t208xrdb.c
board/freescale/t4qds/eth.c
@@ -349,6 +349,9 @@
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "emi1_rgmii");
 			break;
 		default:
@@ -448,6 +451,9 @@
 				miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * If DTSEC4 is RGMII, then it's routed via via EC1 to
 			 * the first on-board RGMII port.  If DTSEC5 is RGMII,
@@ -364,6 +364,9 @@
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fm_info_set_phy_address(i, 0);
 			mdio_mux[i] = EMI1_RGMII;
 			fm_info_set_mdio(i,
@@ -431,6 +434,9 @@
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fm_info_set_phy_address(i, 0);
 			mdio_mux[i] = EMI1_RGMII;
 			fm_info_set_mdio(i,
@@ -315,6 +315,9 @@
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "hydra_rg");
 			debug("Enabled MDIO node hydra_rg\n");
 			break;
@@ -351,6 +354,9 @@
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			fdt_status_okay_by_alias(fdt, "hydra_rg");
 			debug("Enabled MDIO node hydra_rg\n");
 			break;
@@ -555,6 +561,9 @@
 			miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * FM1 DTSEC5 is routed via EC1 to the first on-board
 			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -702,6 +711,9 @@
  
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * FM1 DTSEC5 is routed via EC1 to the first on-board
 			 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
@@ -80,17 +80,21 @@
 {
 	phy_interface_t intf = fm_info_get_enet_if(port);
 	char phy[16];
+	int lane;
+	u8 slot;
  
+	switch (intf) {
 	/* The RGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_RGMII) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
 		fdt_set_phy_handle(fdt, compat, addr, phy);
-	}
-
+		break;
 	/* The SGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_SGMII) {
-		int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
-		u8 slot;
+	case PHY_INTERFACE_MODE_SGMII:
+		lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
 		if (lane < 0)
 			return;
 		slot = lane_to_slot[lane];
  
  
@@ -105,16 +109,18 @@
 					+ (port - FM1_DTSEC1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
-	}
-
-	if (intf == PHY_INTERFACE_MODE_XGMII) {
+		break;
+	case PHY_INTERFACE_MODE_XGMII:
 		/* XAUI */
-		int lane = serdes_get_first_lane(XAUI_FM1);
+		lane = serdes_get_first_lane(XAUI_FM1);
 		if (lane >= 0) {
 			/* The XAUI PHY is identified by the slot */
 			sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
+		break;
+	default:
+		break;
 	}
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
@@ -168,6 +174,9 @@
 				fm_info_set_phy_address(i, riser_phy_addr[i]);
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
 			fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
 					CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
@@ -168,14 +168,19 @@
 {
 	struct fixed_link f_link;
  
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
+	switch (fm_info_get_enet_if(port)) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		if (port == FM1_DTSEC3) {
 			fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
 			fdt_setprop_string(fdt, offset, "phy-connection-type",
 					   "rgmii");
 			fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
 		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		break;
+	case PHY_INTERFACE_MODE_SGMII:
 		if (port == FM1_DTSEC1) {
 			fdt_set_phy_handle(fdt, compat, addr,
 					   "sgmii_vsc8234_phy_s5");
  
@@ -183,12 +188,14 @@
 			fdt_set_phy_handle(fdt, compat, addr,
 					   "sgmii_vsc8234_phy_s4");
 		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+		break;
+	case PHY_INTERFACE_MODE_SGMII_2500:
 		if (port == FM1_DTSEC3) {
 			fdt_set_phy_handle(fdt, compat, addr,
 					   "sgmii_aqr105_phy_s3");
 		}
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+		break;
+	case PHY_INTERFACE_MODE_QSGMII:
 		switch (port) {
 		case FM1_DTSEC1:
 			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
@@ -209,7 +216,8 @@
 		fdt_setprop_string(fdt, offset, "phy-connection-type",
 				   "qsgmii");
 		fdt_status_okay_by_alias(fdt, "emi1_slot2");
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+		break;
+	case PHY_INTERFACE_MODE_XGMII:
 		/* XFI interface */
 		f_link.phy_id = port;
 		f_link.duplex = 1;
@@ -220,6 +228,9 @@
 		fdt_delprop(fdt, offset, "phy-handle");
 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+		break;
+	default:
+		break;
 	}
 }
  
@@ -408,6 +419,9 @@
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII2;
 			else if (i == FM1_DTSEC4)
@@ -87,6 +87,9 @@
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
@@ -288,14 +288,17 @@
 	phy_interface_t intf = fm_info_get_enet_if(port);
 	char phy[16];
  
+	switch (intf) {
 	/* The RGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_RGMII) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
 		sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
 		fdt_set_phy_handle(fdt, compat, addr, phy);
-	}
-
+		break;
 	/* The SGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_SGMII) {
+	case PHY_INTERFACE_MODE_SGMII:
 		int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
 						 + port);
 		u8 slot;
@@ -309,6 +312,9 @@
 				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
 			fdt_set_phy_handle(fdt, compat, addr, phy);
 		}
+		break;
+	default:
+		break;
 	}
 }
  
@@ -341,6 +347,9 @@
 			}
 		break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (i == FM1_DTSEC4)
 				fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
  
@@ -491,6 +500,9 @@
 			break;
  
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
 			t1040_handle_phy_interface_rgmii(i);
 			break;
@@ -76,6 +76,9 @@
 			break;
 #endif
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (FM1_DTSEC4 == i)
 				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
 			if (FM1_DTSEC5 == i)
@@ -750,6 +750,9 @@
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII1;
 			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
@@ -74,6 +74,9 @@
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
@@ -638,6 +638,9 @@
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/* FM1 DTSEC5 routes to RGMII with EC2 */
 			debug("FM1@DTSEC%u is RGMII at address %u\n",
 				idx + 1, 2);
@@ -816,6 +819,9 @@
 			};
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
+		case PHY_INTERFACE_MODE_RGMII_RXID:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			/*
 			 * If DTSEC5 is RGMII, then it's routed via via EC1 to
 			 * the first on-board RGMII port.  If DTSEC6 is RGMII,
...	...	@@ -349,6 +349,9 @@
349	349	}
350	350	break;
351	351	case PHY_INTERFACE_MODE_RGMII:
	352	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	353	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	354	+ case PHY_INTERFACE_MODE_RGMII_ID:
352	355	fdt_status_okay_by_alias(fdt, "emi1_rgmii");
353	356	break;
354	357	default:
...	...	@@ -448,6 +451,9 @@
448	451	miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
449	452	break;
450	453	case PHY_INTERFACE_MODE_RGMII:
	454	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	455	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	456	+ case PHY_INTERFACE_MODE_RGMII_ID:
451	457	/*
452	458	* If DTSEC4 is RGMII, then it's routed via via EC1 to
453	459	* the first on-board RGMII port. If DTSEC5 is RGMII,
...	...	@@ -364,6 +364,9 @@
364	364	};
365	365	break;
366	366	case PHY_INTERFACE_MODE_RGMII:
	367	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	368	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	369	+ case PHY_INTERFACE_MODE_RGMII_ID:
367	370	fm_info_set_phy_address(i, 0);
368	371	mdio_mux[i] = EMI1_RGMII;
369	372	fm_info_set_mdio(i,
...	...	@@ -431,6 +434,9 @@
431	434	};
432	435	break;
433	436	case PHY_INTERFACE_MODE_RGMII:
	437	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	438	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	439	+ case PHY_INTERFACE_MODE_RGMII_ID:
434	440	fm_info_set_phy_address(i, 0);
435	441	mdio_mux[i] = EMI1_RGMII;
436	442	fm_info_set_mdio(i,
...	...	@@ -315,6 +315,9 @@
315	315	}
316	316	break;
317	317	case PHY_INTERFACE_MODE_RGMII:
	318	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	319	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	320	+ case PHY_INTERFACE_MODE_RGMII_ID:
318	321	fdt_status_okay_by_alias(fdt, "hydra_rg");
319	322	debug("Enabled MDIO node hydra_rg\n");
320	323	break;
...	...	@@ -351,6 +354,9 @@
351	354	}
352	355	break;
353	356	case PHY_INTERFACE_MODE_RGMII:
	357	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	358	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	359	+ case PHY_INTERFACE_MODE_RGMII_ID:
354	360	fdt_status_okay_by_alias(fdt, "hydra_rg");
355	361	debug("Enabled MDIO node hydra_rg\n");
356	362	break;
...	...	@@ -555,6 +561,9 @@
555	561	miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
556	562	break;
557	563	case PHY_INTERFACE_MODE_RGMII:
	564	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	565	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	566	+ case PHY_INTERFACE_MODE_RGMII_ID:
558	567	/*
559	568	* FM1 DTSEC5 is routed via EC1 to the first on-board
560	569	* RGMII port. FM2 DTSEC5 is routed via EC2 to the
...	...	@@ -702,6 +711,9 @@
702	711
703	712	break;
704	713	case PHY_INTERFACE_MODE_RGMII:
	714	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	715	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	716	+ case PHY_INTERFACE_MODE_RGMII_ID:
705	717	/*
706	718	* FM1 DTSEC5 is routed via EC1 to the first on-board
707	719	* RGMII port. FM2 DTSEC5 is routed via EC2 to the
...	...	@@ -80,17 +80,21 @@
80	80	{
81	81	phy_interface_t intf = fm_info_get_enet_if(port);
82	82	char phy[16];
	83	+ int lane;
	84	+ u8 slot;
83	85
	86	+ switch (intf) {
84	87	/* The RGMII PHY is identified by the MAC connected to it */
85		- if (intf == PHY_INTERFACE_MODE_RGMII) {
	88	+ case PHY_INTERFACE_MODE_RGMII:
	89	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	90	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	91	+ case PHY_INTERFACE_MODE_RGMII_ID:
86	92	sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
87	93	fdt_set_phy_handle(fdt, compat, addr, phy);
88		- }
89		-
	94	+ break;
90	95	/* The SGMII PHY is identified by the MAC connected to it */
91		- if (intf == PHY_INTERFACE_MODE_SGMII) {
92		- int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
93		- u8 slot;
	96	+ case PHY_INTERFACE_MODE_SGMII:
	97	+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
94	98	if (lane < 0)
95	99	return;
96	100	slot = lane_to_slot[lane];
97	101
98	102
...	...	@@ -105,16 +109,18 @@
105	109	+ (port - FM1_DTSEC1));
106	110	fdt_set_phy_handle(fdt, compat, addr, phy);
107	111	}
108		- }
109		-
110		- if (intf == PHY_INTERFACE_MODE_XGMII) {
	112	+ break;
	113	+ case PHY_INTERFACE_MODE_XGMII:
111	114	/* XAUI */
112		- int lane = serdes_get_first_lane(XAUI_FM1);
	115	+ lane = serdes_get_first_lane(XAUI_FM1);
113	116	if (lane >= 0) {
114	117	/* The XAUI PHY is identified by the slot */
115	118	sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
116	119	fdt_set_phy_handle(fdt, compat, addr, phy);
117	120	}
	121	+ break;
	122	+ default:
	123	+ break;
118	124	}
119	125	}
120	126	#endif /* #ifdef CONFIG_FMAN_ENET */
...	...	@@ -168,6 +174,9 @@
168	174	fm_info_set_phy_address(i, riser_phy_addr[i]);
169	175	break;
170	176	case PHY_INTERFACE_MODE_RGMII:
	177	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	178	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	179	+ case PHY_INTERFACE_MODE_RGMII_ID:
171	180	/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
172	181	fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
173	182	CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
...	...	@@ -168,14 +168,19 @@
168	168	{
169	169	struct fixed_link f_link;
170	170
171		- if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
	171	+ switch (fm_info_get_enet_if(port)) {
	172	+ case PHY_INTERFACE_MODE_RGMII:
	173	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	174	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	175	+ case PHY_INTERFACE_MODE_RGMII_ID:
172	176	if (port == FM1_DTSEC3) {
173	177	fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
174	178	fdt_setprop_string(fdt, offset, "phy-connection-type",
175	179	"rgmii");
176	180	fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
177	181	}
178		- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
	182	+ break;
	183	+ case PHY_INTERFACE_MODE_SGMII:
179	184	if (port == FM1_DTSEC1) {
180	185	fdt_set_phy_handle(fdt, compat, addr,
181	186	"sgmii_vsc8234_phy_s5");
182	187
...	...	@@ -183,12 +188,14 @@
183	188	fdt_set_phy_handle(fdt, compat, addr,
184	189	"sgmii_vsc8234_phy_s4");
185	190	}
186		- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
	191	+ break;
	192	+ case PHY_INTERFACE_MODE_SGMII_2500:
187	193	if (port == FM1_DTSEC3) {
188	194	fdt_set_phy_handle(fdt, compat, addr,
189	195	"sgmii_aqr105_phy_s3");
190	196	}
191		- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
	197	+ break;
	198	+ case PHY_INTERFACE_MODE_QSGMII:
192	199	switch (port) {
193	200	case FM1_DTSEC1:
194	201	fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
...	...	@@ -209,7 +216,8 @@
209	216	fdt_setprop_string(fdt, offset, "phy-connection-type",
210	217	"qsgmii");
211	218	fdt_status_okay_by_alias(fdt, "emi1_slot2");
212		- } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
	219	+ break;
	220	+ case PHY_INTERFACE_MODE_XGMII:
213	221	/* XFI interface */
214	222	f_link.phy_id = port;
215	223	f_link.duplex = 1;
...	...	@@ -220,6 +228,9 @@
220	228	fdt_delprop(fdt, offset, "phy-handle");
221	229	fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
222	230	fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
	231	+ break;
	232	+ default:
	233	+ break;
223	234	}
224	235	}
225	236
...	...	@@ -408,6 +419,9 @@
408	419	}
409	420	break;
410	421	case PHY_INTERFACE_MODE_RGMII:
	422	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	423	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	424	+ case PHY_INTERFACE_MODE_RGMII_ID:
411	425	if (i == FM1_DTSEC3)
412	426	mdio_mux[i] = EMI1_RGMII2;
413	427	else if (i == FM1_DTSEC4)
...	...	@@ -87,6 +87,9 @@
87	87	interface = fm_info_get_enet_if(i);
88	88	switch (interface) {
89	89	case PHY_INTERFACE_MODE_RGMII:
	90	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	91	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	92	+ case PHY_INTERFACE_MODE_RGMII_ID:
90	93	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
91	94	fm_info_set_mdio(i, dev);
92	95	break;
...	...	@@ -288,14 +288,17 @@
288	288	phy_interface_t intf = fm_info_get_enet_if(port);
289	289	char phy[16];
290	290
	291	+ switch (intf) {
291	292	/* The RGMII PHY is identified by the MAC connected to it */
292		- if (intf == PHY_INTERFACE_MODE_RGMII) {
	293	+ case PHY_INTERFACE_MODE_RGMII:
	294	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	295	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	296	+ case PHY_INTERFACE_MODE_RGMII_ID:
293	297	sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
294	298	fdt_set_phy_handle(fdt, compat, addr, phy);
295		- }
296		-
	299	+ break;
297	300	/* The SGMII PHY is identified by the MAC connected to it */
298		- if (intf == PHY_INTERFACE_MODE_SGMII) {
	301	+ case PHY_INTERFACE_MODE_SGMII:
299	302	int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
300	303	+ port);
301	304	u8 slot;
...	...	@@ -309,6 +312,9 @@
309	312	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
310	313	fdt_set_phy_handle(fdt, compat, addr, phy);
311	314	}
	315	+ break;
	316	+ default:
	317	+ break;
312	318	}
313	319	}
314	320
...	...	@@ -341,6 +347,9 @@
341	347	}
342	348	break;
343	349	case PHY_INTERFACE_MODE_RGMII:
	350	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	351	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	352	+ case PHY_INTERFACE_MODE_RGMII_ID:
344	353	if (i == FM1_DTSEC4)
345	354	fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
346	355
...	...	@@ -491,6 +500,9 @@
491	500	break;
492	501
493	502	case PHY_INTERFACE_MODE_RGMII:
	503	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	504	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	505	+ case PHY_INTERFACE_MODE_RGMII_ID:
494	506	/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
495	507	t1040_handle_phy_interface_rgmii(i);
496	508	break;
...	...	@@ -76,6 +76,9 @@
76	76	break;
77	77	#endif
78	78	case PHY_INTERFACE_MODE_RGMII:
	79	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	80	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	81	+ case PHY_INTERFACE_MODE_RGMII_ID:
79	82	if (FM1_DTSEC4 == i)
80	83	phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
81	84	if (FM1_DTSEC5 == i)
...	...	@@ -750,6 +750,9 @@
750	750	}
751	751	break;
752	752	case PHY_INTERFACE_MODE_RGMII:
	753	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	754	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	755	+ case PHY_INTERFACE_MODE_RGMII_ID:
753	756	if (i == FM1_DTSEC3)
754	757	mdio_mux[i] = EMI1_RGMII1;
755	758	else if (i == FM1_DTSEC4 \|\| FM1_DTSEC10)
...	...	@@ -74,6 +74,9 @@
74	74	interface = fm_info_get_enet_if(i);
75	75	switch (interface) {
76	76	case PHY_INTERFACE_MODE_RGMII:
	77	+ case PHY_INTERFACE_MODE_RGMII_TXID:
	78	+ case PHY_INTERFACE_MODE_RGMII_RXID:
	79	+ case PHY_INTERFACE_MODE_RGMII_ID:
77	80	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
78	81	fm_info_set_mdio(i, dev);
79	82	break;