Eric Lee / smarc-uboot

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Commit 784667d7f9452780966dd0b400ef516f14f14c26

Authored by Tom Rini
2 parents 2aaf7c4900 e625881ad7
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge tag 'xilinx-for-v2017.07' of git://www.denx.de/git/u-boot-microblaze 

Xilinx changes for v2017.07

ZynqMP:
- config cleanup
- SD LS mode support
- psu_init* cleanup
- unmap OCM
- Support for SMC

Zynq:
- add ddrc to Kconfig
- add topic-miamilite board support

Showing 23 changed files Side-by-side Diff

... ... @@ -2534,12 +2534,6 @@
2534 2534 Define this option to include a destructive SPI flash
2535 2535 test ('sf test').
2536 2536  
2537   - CONFIG_SF_DUAL_FLASH Dual flash memories
2538   -
2539   - Define this option to use dual flash support where two flash
2540   - memories can be connected with a given cs line.
2541   - Currently Xilinx Zynq qspi supports these type of connections.
2542   -
2543 2537 - SystemACE Support:
2544 2538 CONFIG_SYSTEMACE
2545 2539  
arch/arm/cpu/armv8/zynqmp/cpu.c
Diff comments   View file @ 784667d
... ... @@ -38,12 +38,6 @@
38 38 PTE_BLOCK_NON_SHARE |
39 39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 40 }, {
41   - .virt = 0xffe00000UL,
42   - .phys = 0xffe00000UL,
43   - .size = 0x00200000UL,
44   - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45   - PTE_BLOCK_INNER_SHARE
46   - }, {
47 41 .virt = 0x400000000UL,
48 42 .phys = 0x400000000UL,
49 43 .size = 0x200000000UL,
... ... @@ -104,4 +98,112 @@
104 98  
105 99 return ZYNQMP_CSU_VERSION_SILICON;
106 100 }
  101 +
  102 +#define ZYNQMP_MMIO_READ 0xC2000014
  103 +#define ZYNQMP_MMIO_WRITE 0xC2000013
  104 +
  105 +#ifndef CONFIG_SPL_BUILD
  106 +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
  107 + u32 *ret_payload)
  108 +{
  109 + /*
  110 + * Added SIP service call Function Identifier
  111 + * Make sure to stay in x0 register
  112 + */
  113 + struct pt_regs regs;
  114 +
  115 + regs.regs[0] = pm_api_id;
  116 + regs.regs[1] = ((u64)arg1 << 32) | arg0;
  117 + regs.regs[2] = ((u64)arg3 << 32) | arg2;
  118 +
  119 + smc_call(&regs);
  120 +
  121 + if (ret_payload != NULL) {
  122 + ret_payload[0] = (u32)regs.regs[0];
  123 + ret_payload[1] = upper_32_bits(regs.regs[0]);
  124 + ret_payload[2] = (u32)regs.regs[1];
  125 + ret_payload[3] = upper_32_bits(regs.regs[1]);
  126 + ret_payload[4] = (u32)regs.regs[2];
  127 + }
  128 +
  129 + return regs.regs[0];
  130 +}
  131 +
  132 +#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
  133 +
  134 +#define ZYNQMP_PM_VERSION_MAJOR 0
  135 +#define ZYNQMP_PM_VERSION_MINOR 3
  136 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
  137 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
  138 +
  139 +#define ZYNQMP_PM_VERSION \
  140 + ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
  141 + ZYNQMP_PM_VERSION_MINOR)
  142 +
  143 +#if defined(CONFIG_CLK_ZYNQMP)
  144 +void zynqmp_pmufw_version(void)
  145 +{
  146 + int ret;
  147 + u32 ret_payload[PAYLOAD_ARG_CNT];
  148 + u32 pm_api_version;
  149 +
  150 + ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
  151 + ret_payload);
  152 + pm_api_version = ret_payload[1];
  153 +
  154 + if (ret)
  155 + panic("PMUFW is not found - Please load it!\n");
  156 +
  157 + printf("PMUFW:\tv%d.%d\n",
  158 + pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
  159 + pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
  160 +
  161 + if (pm_api_version != ZYNQMP_PM_VERSION)
  162 + panic("PMUFW version error. Expected: v%d.%d\n",
  163 + ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
  164 +}
  165 +#endif
  166 +
  167 +int zynqmp_mmio_write(const u32 address,
  168 + const u32 mask,
  169 + const u32 value)
  170 +{
  171 + return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
  172 +}
  173 +
  174 +int zynqmp_mmio_read(const u32 address, u32 *value)
  175 +{
  176 + u32 ret_payload[PAYLOAD_ARG_CNT];
  177 + u32 ret;
  178 +
  179 + if (!value)
  180 + return -EINVAL;
  181 +
  182 + ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
  183 + *value = ret_payload[1];
  184 +
  185 + return ret;
  186 +}
  187 +#else
  188 +int zynqmp_mmio_write(const u32 address,
  189 + const u32 mask,
  190 + const u32 value)
  191 +{
  192 + u32 data;
  193 + u32 value_local = value;
  194 +
  195 + zynqmp_mmio_read(address, &data);
  196 + data &= ~mask;
  197 + value_local &= mask;
  198 + value_local |= data;
  199 + writel(value_local, (ulong)address);
  200 + return 0;
  201 +}
  202 +
  203 +int zynqmp_mmio_read(const u32 address, u32 *value)
  204 +{
  205 + *value = readl((ulong)address);
  206 + return 0;
  207 +}
  208 +#endif
arch/arm/cpu/armv8/zynqmp/spl.c
Diff comments   View file @ 784667d
... ... @@ -83,9 +83,15 @@
83 83 case JTAG_MODE:
84 84 return BOOT_DEVICE_RAM;
85 85 #ifdef CONFIG_SPL_MMC_SUPPORT
86   - case EMMC_MODE:
87   - case SD_MODE:
88 86 case SD_MODE1:
  87 + case SD1_LSHFT_MODE: /* not working on silicon v1 */
  88 +/* if both controllers enabled, then these two are the second controller */
  89 +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
  90 + return BOOT_DEVICE_MMC2;
  91 +/* else, fall through, the one SDHCI controller that is enabled is number 1 */
  92 +#endif
  93 + case SD_MODE:
  94 + case EMMC_MODE:
89 95 return BOOT_DEVICE_MMC1;
90 96 #endif
91 97 #ifdef CONFIG_SPL_DFU_SUPPORT
92 98  
... ... @@ -106,10 +112,11 @@
106 112  
107 113 u32 spl_boot_mode(const u32 boot_device)
108 114 {
109   - switch (spl_boot_device()) {
  115 + switch (boot_device) {
110 116 case BOOT_DEVICE_RAM:
111 117 return 0;
112 118 case BOOT_DEVICE_MMC1:
  119 + case BOOT_DEVICE_MMC2:
113 120 return MMCSD_MODE_FS;
114 121 default:
115 122 puts("spl: error: unsupported device\n");
arch/arm/dts/Makefile
Diff comments   View file @ 784667d
... ... @@ -127,6 +127,7 @@
127 127 zynq-microzed.dtb \
128 128 zynq-picozed.dtb \
129 129 zynq-topic-miami.dtb \
  130 + zynq-topic-miamilite.dtb \
130 131 zynq-topic-miamiplus.dtb \
131 132 zynq-zc770-xm010.dtb \
132 133 zynq-zc770-xm011.dtb \
arch/arm/dts/zynq-topic-miamilite.dts
Diff comments   View file @ 784667d
  1 +/*
  2 + * Topic Miami Lite board DTS
  3 + *
  4 + * Copyright (C) 2017 Topic Embedded Products
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +#include "zynq-topic-miami.dts"
  9 +
  10 +/ {
  11 + model = "Topic Miami Lite Zynq Board";
  12 + compatible = "topic,miamilite", "xlnx,zynq-7000";
  13 +};
  14 +
  15 +&qspi {
  16 + is-dual = <1>;
  17 +};
arch/arm/include/asm/arch-zynqmp/sys_proto.h
Diff comments   View file @ 784667d
... ... @@ -8,6 +8,8 @@
8 8 #ifndef _ASM_ARCH_SYS_PROTO_H
9 9 #define _ASM_ARCH_SYS_PROTO_H
10 10  
  11 +#define PAYLOAD_ARG_CNT 5
  12 +
11 13 int zynq_slcr_get_mio_pin_status(const char *periph);
12 14  
13 15 unsigned int zynqmp_get_silicon_version(void);
... ... @@ -15,6 +17,12 @@
15 17 void psu_init(void);
16 18  
17 19 void handoff_setup(void);
  20 +
  21 +void zynqmp_pmufw_version(void);
  22 +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
  23 +int zynqmp_mmio_read(const u32 address, u32 *value);
  24 +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
  25 + u32 *ret_payload);
18 26  
19 27 #endif /* _ASM_ARCH_SYS_PROTO_H */
arch/arm/mach-zynq/Kconfig
Diff comments   View file @ 784667d
... ... @@ -24,6 +24,14 @@
24 24 config SPL_SPI_SUPPORT
25 25 default y if ZYNQ_QSPI
26 26  
  27 +config ZYNQ_DDRC_INIT
  28 + bool "Zynq DDRC initialization"
  29 + default y
  30 + help
  31 + This option used to perform DDR specific initialization
  32 + if required. There might be cases like ddr less where we
  33 + want to skip ddr init and this option is useful for it.
  34 +
27 35 config SYS_BOARD
28 36 default "zynq"
29 37  
arch/arm/mach-zynq/ddrc.c
Diff comments   View file @ 784667d
... ... @@ -12,6 +12,9 @@
12 12  
13 13 DECLARE_GLOBAL_DATA_PTR;
14 14  
  15 +#ifndef CONFIG_ZYNQ_DDRC_INIT
  16 +void zynq_ddrc_init(void) {}
  17 +#else
15 18 /* Control regsiter bitfield definitions */
16 19 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC
17 20 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2
... ... @@ -46,4 +49,5 @@
46 49 puts("ECC disabled ");
47 50 }
48 51 }
  52 +#endif
arch/microblaze/dts/Makefile
Diff comments   View file @ 784667d
... ... @@ -2,7 +2,7 @@
2 2 # SPDX-License-Identifier: GPL-2.0+
3 3 #
4 4  
5   -dtb-y += microblaze-generic.dtb
  5 +dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb
6 6  
7 7 targets += $(dtb-y)
8 8  
board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
Diff comments   View file @ 784667d
  1 +/*
  2 + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
  3 + * (c) Copyright 2016 Topic Embedded Products.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include "../ps7_init_gpl.h"
  9 +
  10 +static unsigned long ps7_pll_init_data_3_0[] = {
  11 + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
  12 + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
  13 + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
  14 + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
  15 + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
  16 + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
  17 + EMIT_MASKPOLL(0xF800010C, 0x00000001U),
  18 + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
  19 + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
  20 + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
  21 + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
  22 + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
  23 + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
  24 + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
  25 + EMIT_MASKPOLL(0xF800010C, 0x00000002U),
  26 + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
  27 + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
  28 + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U),
  29 + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U),
  30 + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
  31 + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
  32 + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
  33 + EMIT_MASKPOLL(0xF800010C, 0x00000004U),
  34 + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
  35 + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
  36 + EMIT_EXIT(),
  37 +};
  38 +
  39 +static unsigned long ps7_clock_init_data_3_0[] = {
  40 + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
  41 + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U),
  42 + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U),
  43 + EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U),
  44 + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U),
  45 + EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U),
  46 + EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U),
  47 + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U),
  48 + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U),
  49 + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U),
  50 + EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
  51 + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U),
  52 + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U),
  53 + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U),
  54 + EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U),
  55 + EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U),
  56 + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
  57 + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
  58 + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
  59 + EMIT_EXIT(),
  60 +};
  61 +
  62 +static unsigned long ps7_ddr_init_data_3_0[] = {
  63 + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
  64 + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
  65 + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
  66 + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
  67 + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
  68 + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
  69 + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
  70 + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
  71 + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
  72 + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
  73 + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
  74 + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
  75 + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
  76 + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
  77 + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
  78 + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
  79 + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
  80 + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
  81 + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
  82 + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
  83 + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
  84 + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
  85 + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
  86 + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
  87 + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
  88 + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
  89 + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
  90 + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
  91 + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
  92 + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
  93 + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
  94 + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
  95 + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
  96 + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
  97 + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
  98 + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
  99 + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
  100 + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
  101 + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
  102 + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
  103 + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
  104 + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
  105 + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
  106 + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
  107 + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
  108 + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU),
  109 + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U),
  110 + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU),
  111 + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU),
  112 + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
  113 + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
  114 + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
  115 + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
  116 + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU),
  117 + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U),
  118 + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU),
  119 + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU),
  120 + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U),
  121 + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U),
  122 + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU),
  123 + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U),
  124 + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU),
  125 + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U),
  126 + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU),
  127 + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU),
  128 + EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U),
  129 + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
  130 + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
  131 + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
  132 + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
  133 + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
  134 + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
  135 + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
  136 + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
  137 + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
  138 + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
  139 + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
  140 + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
  141 + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
  142 + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
  143 + EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
  144 + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
  145 + EMIT_MASKPOLL(0xF8006054, 0x00000007U),
  146 + EMIT_EXIT(),
  147 +};
  148 +
  149 +static unsigned long ps7_mio_init_data_3_0[] = {
  150 + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
  151 + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
  152 + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
  153 + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
  154 + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
  155 + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
  156 + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
  157 + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
  158 + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
  159 + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
  160 + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
  161 + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
  162 + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U),
  163 + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
  164 + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
  165 + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
  166 + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
  167 + EMIT_EXIT(),
  168 +};
  169 +
  170 +static unsigned long ps7_peripherals_init_data_3_0[] = {
  171 + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
  172 + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
  173 + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
  174 + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
  175 + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
  176 + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
  177 + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
  178 + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
  179 + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
  180 + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
  181 + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
  182 + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
  183 + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
  184 + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
  185 + EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
  186 + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
  187 + EMIT_MASKDELAY(0xF8F00200, 1),
  188 + EMIT_MASKDELAY(0xF8F00200, 1),
  189 + EMIT_MASKDELAY(0xF8F00200, 1),
  190 + EMIT_EXIT(),
  191 +};
  192 +
  193 +static unsigned long ps7_post_config_3_0[] = {
  194 + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
  195 + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
  196 + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
  197 + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
  198 + EMIT_EXIT(),
  199 +};
  200 +
  201 +int ps7_init(void)
  202 +{
  203 + int ret;
  204 +
  205 + ret = ps7_config(ps7_mio_init_data_3_0);
  206 + if (ret != PS7_INIT_SUCCESS)
  207 + return ret;
  208 + ret = ps7_config(ps7_pll_init_data_3_0);
  209 + if (ret != PS7_INIT_SUCCESS)
  210 + return ret;
  211 + ret = ps7_config(ps7_clock_init_data_3_0);
  212 + if (ret != PS7_INIT_SUCCESS)
  213 + return ret;
  214 + ret = ps7_config(ps7_ddr_init_data_3_0);
  215 + if (ret != PS7_INIT_SUCCESS)
  216 + return ret;
  217 + ret = ps7_config(ps7_peripherals_init_data_3_0);
  218 + if (ret != PS7_INIT_SUCCESS)
  219 + return ret;
  220 +
  221 + return PS7_INIT_SUCCESS;
  222 +}
  223 +
  224 +int ps7_post_config(void)
  225 +{
  226 + return ps7_config(ps7_post_config_3_0);
  227 +}
board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt
Diff comments   View file @ 784667d
  1 +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
  2 +0xf8000700 0x202
  3 +0xf8000704 0x202
  4 +0xf8000708 0x202
  5 +0xf800070c 0x202
  6 +0xf8000710 0x202
  7 +0xf8000714 0x202
  8 +0xf8000718 0x202
  9 +0xf800071c 0x200
  10 +0xf8000720 0x202
  11 +0xf8000724 0x202
  12 +0xf8000728 0x202
  13 +0xf800072c 0x202
  14 +0xf8000730 0x202
  15 +0xf8000734 0x202
  16 +0xf8000738 0x12e1
  17 +0xf800073c 0x12e0
  18 +0xf8000740 0x1200
  19 +0xf8000744 0x1200
  20 +0xf8000748 0x1200
  21 +0xf800074c 0x1200
  22 +0xf8000750 0x1200
  23 +0xf8000754 0x1200
  24 +0xf8000758 0x1200
  25 +0xf800075c 0x1200
  26 +0xf8000760 0x1200
  27 +0xf8000764 0x200
  28 +0xf8000768 0x1200
  29 +0xf800076c 0x200
  30 +0xf8000770 0x304
  31 +0xf8000774 0x305
  32 +0xf8000778 0x304
  33 +0xf800077c 0x305
  34 +0xf8000780 0x304
  35 +0xf8000784 0x304
  36 +0xf8000788 0x304
  37 +0xf800078c 0x304
  38 +0xf8000790 0x305
  39 +0xf8000794 0x304
  40 +0xf8000798 0x304
  41 +0xf800079c 0x304
  42 +0xf80007a0 0x380
  43 +0xf80007a4 0x380
  44 +0xf80007a8 0x380
  45 +0xf80007ac 0x380
  46 +0xf80007b0 0x380
  47 +0xf80007b4 0x380
  48 +0xf80007b8 0x1200
  49 +0xf80007bc 0x1200
  50 +0xf80007c0 0x1240
  51 +0xf80007c4 0x1240
  52 +0xf80007c8 0x1240
  53 +0xf80007cc 0x1240
  54 +0xf80007d0 0x1200
  55 +0xf80007d4 0x1200
  56 +0xf8000830 0x380037
  57 +0xf8000834 0x3a0039
  58 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
  59 +0xE000D000 0x800238C1 // QSPI config - divide-by-2
  60 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
  61 +0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
board/xilinx/zynqmp/sleep.h
Diff comments   View file @ 784667d
  1 +/* Intentionally empty file for psu_init* */
board/xilinx/zynqmp/xil_io.h
Diff comments   View file @ 784667d
... ... @@ -33,13 +33,10 @@
33 33 return readl(addr);
34 34 }
35 35  
36   -void mask_delay(u32 delay);
37 36 void usleep(u32 sleep)
38 37 {
39 38 udelay(sleep);
40 39 }
41   -int mask_poll(u32 add, u32 mask);
42   -int mask_pollOnValue(u32 add, u32 mask, u32 value);
43 40  
44 41 #endif /* XIL_IO_H */
board/xilinx/zynqmp/zynqmp.c
Diff comments   View file @ 784667d
... ... @@ -113,6 +113,14 @@
113 113 }
114 114 #endif
115 115  
  116 +int board_early_init_f(void)
  117 +{
  118 +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
  119 + zynqmp_pmufw_version();
  120 +#endif
  121 + return 0;
  122 +}
  123 +
116 124 #define ZYNQMP_VERSION_SIZE 9
117 125  
118 126 int board_init(void)
configs/topic_miamilite_defconfig
Diff comments   View file @ 784667d
  1 +CONFIG_ARM=y
  2 +CONFIG_SYS_VENDOR="topic"
  3 +CONFIG_SYS_CONFIG_NAME="topic_miami"
  4 +CONFIG_ARCH_ZYNQ=y
  5 +CONFIG_SYS_TEXT_BASE=0x4000000
  6 +CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
  7 +CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
  8 +CONFIG_BOOTDELAY=0
  9 +# CONFIG_DISPLAY_CPUINFO is not set
  10 +CONFIG_SPL=y
  11 +CONFIG_HUSH_PARSER=y
  12 +CONFIG_SYS_PROMPT="zynq-uboot> "
  13 +# CONFIG_CMD_IMLS is not set
  14 +# CONFIG_CMD_FLASH is not set
  15 +CONFIG_CMD_MMC=y
  16 +CONFIG_CMD_SF=y
  17 +CONFIG_CMD_I2C=y
  18 +CONFIG_CMD_USB=y
  19 +CONFIG_CMD_DFU=y
  20 +CONFIG_CMD_GPIO=y
  21 +# CONFIG_CMD_SETEXPR is not set
  22 +# CONFIG_CMD_NET is not set
  23 +# CONFIG_CMD_NFS is not set
  24 +CONFIG_CMD_CACHE=y
  25 +CONFIG_CMD_EXT4=y
  26 +CONFIG_CMD_FAT=y
  27 +CONFIG_CMD_FS_GENERIC=y
  28 +CONFIG_OF_EMBED=y
  29 +CONFIG_SPL_DM_SEQ_ALIAS=y
  30 +CONFIG_DFU_RAM=y
  31 +CONFIG_MMC_SDHCI=y
  32 +CONFIG_MMC_SDHCI_ZYNQ=y
  33 +CONFIG_SF_DUAL_FLASH=y
  34 +CONFIG_SPI_FLASH=y
  35 +CONFIG_SPI_FLASH_BAR=y
  36 +CONFIG_SPI_FLASH_STMICRO=y
  37 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  38 +CONFIG_DEBUG_UART=y
  39 +CONFIG_DEBUG_UART_ZYNQ=y
  40 +CONFIG_DEBUG_UART_BASE=0xe0000000
  41 +CONFIG_DEBUG_UART_CLOCK=100000000
  42 +CONFIG_ZYNQ_QSPI=y
  43 +CONFIG_USB=y
  44 +CONFIG_USB_EHCI_HCD=y
  45 +CONFIG_USB_ULPI_VIEWPORT=y
  46 +CONFIG_USB_ULPI=y
  47 +CONFIG_USB_STORAGE=y
  48 +CONFIG_USB_GADGET=y
  49 +CONFIG_CI_UDC=y
  50 +CONFIG_USB_GADGET_DOWNLOAD=y
  51 +CONFIG_G_DNL_MANUFACTURER="Xilinx"
  52 +CONFIG_G_DNL_VENDOR_NUM=0x03fd
  53 +CONFIG_G_DNL_PRODUCT_NUM=0x0300
configs/topic_miamiplus_defconfig
Diff comments   View file @ 784667d
1 1 CONFIG_ARM=y
2 2 CONFIG_SYS_VENDOR="topic"
3   -CONFIG_SYS_CONFIG_NAME="topic_miamiplus"
  3 +CONFIG_SYS_CONFIG_NAME="topic_miami"
4 4 CONFIG_ARCH_ZYNQ=y
5 5 CONFIG_SYS_TEXT_BASE=0x4000000
6 6 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
... ... @@ -29,6 +29,7 @@
29 29 CONFIG_DFU_RAM=y
30 30 CONFIG_MMC_SDHCI=y
31 31 CONFIG_MMC_SDHCI_ZYNQ=y
  32 +CONFIG_SF_DUAL_FLASH=y
32 33 CONFIG_SPI_FLASH=y
33 34 CONFIG_SPI_FLASH_BAR=y
34 35 CONFIG_SPI_FLASH_STMICRO=y
drivers/block/sata_ceva.c
Diff comments   View file @ 784667d
... ... @@ -6,7 +6,6 @@
6 6 */
7 7 #include <common.h>
8 8 #include <dm.h>
9   -#include <netdev.h>
10 9 #include <ahci.h>
11 10 #include <scsi.h>
12 11 #include <asm/arch/hardware.h>
drivers/fpga/zynqmppl.c
Diff comments   View file @ 784667d
... ... @@ -10,6 +10,7 @@
10 10 #include <common.h>
11 11 #include <zynqmppl.h>
12 12 #include <linux/sizes.h>
  13 +#include <asm/arch/sys_proto.h>
13 14  
14 15 #define DUMMY_WORD 0xffffffff
15 16  
16 17  
17 18  
... ... @@ -191,25 +192,14 @@
191 192 return 0;
192 193 }
193 194  
194   -static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
195   -{
196   - struct pt_regs regs;
197   - regs.regs[0] = id;
198   - regs.regs[1] = reg0;
199   - regs.regs[2] = reg1;
200   - regs.regs[3] = reg2;
201   -
202   - smc_call(&regs);
203   -
204   - return regs.regs[0];
205   -}
206   -
207 195 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
208 196 bitstream_type bstype)
209 197 {
210 198 u32 swap;
211   - ulong bin_buf, flags;
  199 + ulong bin_buf;
212 200 int ret;
  201 + u32 buf_lo, buf_hi;
  202 + u32 ret_payload[PAYLOAD_ARG_CNT];
213 203  
214 204 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
215 205 return FPGA_FAIL;
... ... @@ -224,9 +214,10 @@
224 214 else
225 215 bsize = bsize / 4;
226 216  
227   - flags = (u32)bsize | ((u64)bstype << 32);
228   -
229   - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
  217 + buf_lo = (u32)bin_buf;
  218 + buf_hi = upper_32_bits(bin_buf);
  219 + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
  220 + bstype, ret_payload);
230 221 if (ret)
231 222 debug("PL FPGA LOAD fail\n");
232 223  
drivers/mtd/spi/Kconfig
Diff comments   View file @ 784667d
... ... @@ -42,6 +42,13 @@
42 42 Bank/Extended address registers are used to access the flash
43 43 which has size > 16MiB in 3-byte addressing.
44 44  
  45 +config SF_DUAL_FLASH
  46 + bool "SPI DUAL flash memory support"
  47 + depends on SPI_FLASH
  48 + help
  49 + Enable this option to support two flash memories connected to a single
  50 + controller. Currently Xilinx Zynq qspi supports this.
  51 +
45 52 if SPI_FLASH
46 53  
47 54 config SPI_FLASH_ATMEL
include/configs/topic_miami.h
Diff comments   View file @ 784667d
... ... @@ -56,7 +56,6 @@
56 56 #undef CONFIG_SF_DEFAULT_SPEED
57 57 #define CONFIG_SF_DEFAULT_SPEED 108000000
58 58 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
59   -#undef CONFIG_SF_DUAL_FLASH
60 59 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
61 60 #undef CONFIG_SPI_FLASH_WINBOND
62 61 #undef CONFIG_SPI_FLASH_ISSI
include/configs/topic_miamiplus.h
View file @ 784667d
1   -#include "topic_miami.h"
2   -#define CONFIG_SF_DUAL_FLASH
include/configs/xilinx_zynqmp.h
Diff comments   View file @ 784667d
... ... @@ -29,9 +29,6 @@
29 29 #define CONFIG_SYS_MEMTEST_START 0
30 30 #define CONFIG_SYS_MEMTEST_END 1000
31 31  
32   -/* Have release address at the end of 256MB for now */
33   -#define CPU_RELEASE_ADDR 0xFFFFFF0
34   -
35 32 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
36 33  
37 34 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
38 35  
... ... @@ -292,12 +289,14 @@
292 289 # define CONFIG_ENV_MAX_ENTRIES 10
293 290  
294 291 # define CONFIG_SYS_SPL_MALLOC_START 0x20000000
295   -# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000
  292 +# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
296 293  
297 294 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
298 295 # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
299 296 #endif
300 297 #endif
  298 +
  299 +#define CONFIG_BOARD_EARLY_INIT_F
301 300  
302 301 #endif /* __XILINX_ZYNQMP_H */
scripts/config_whitelist.txt
Diff comments   View file @ 784667d
... ... @@ -2284,7 +2284,6 @@
2284 2284 CONFIG_SF_DEFAULT_CS
2285 2285 CONFIG_SF_DEFAULT_MODE
2286 2286 CONFIG_SF_DEFAULT_SPEED
2287   -CONFIG_SF_DUAL_FLASH
2288 2287 CONFIG_SGI_IP28
2289 2288 CONFIG_SH4_PCI
2290 2289 CONFIG_SH73A0