Eric Lee / smarc-uboot

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Commit 78506c2f8618732b59eba68cd56d20a55c087006

Authored by vpeter4
Committed by Stefano Babic
1 parent b893c9898c
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

udoo: Switch to SPL support 

Currently we need to build one U-boot image for each of the udoo
variants: quad and dual-lite.

By switching to SPL we can support all two variants with a single binary.

Based on the SPL for wandboard.

Tested with OpenELEC (Open Embedded Linux Entertainment Center)
on both boards.

Signed-off-by: Peter Vicman <peter.vicman@gmail.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Peter Vicman <peter.vicman@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>

Showing 12 changed files with 351 additions and 253 deletions Side-by-side Diff

... ... @@ -514,6 +514,7 @@
514 514 config TARGET_UDOO
515 515 bool "Support udoo"
516 516 select CPU_V7
  517 + select SUPPORT_SPL
517 518  
518 519 config TARGET_WANDBOARD
519 520 bool "Support wandboard"
board/udoo/1066mhz_4x256mx16.cfg
View file @ 78506c2
1   -/*
2   - * Copyright (C) 2013 Boundary Devices
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
8   -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
9   -
10   -DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
11   -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
12   -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
13   -
14   -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
15   -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
16   -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
17   -
18   -DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
19   -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
20   -DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
21   -
22   -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
23   -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
24   -
25   -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
26   -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
27   -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
28   -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
29   -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
30   -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
31   -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
32   -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
33   -
34   -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
35   -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
36   -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
37   -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
38   -
39   -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
40   -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
41   -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
42   -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
43   -
44   -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
45   -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
46   -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
47   -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
48   -
49   -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
50   -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
51   -
52   -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
53   -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
54   -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
board/udoo/MAINTAINERS
Diff comments   View file @ 78506c2
... ... @@ -3,5 +3,5 @@
3 3 S: Maintained
4 4 F: board/udoo/
5 5 F: include/configs/udoo.h
6   -F: configs/udoo_quad_defconfig
  6 +F: configs/udoo_defconfig
... ... @@ -4,5 +4,5 @@
4 4 # SPDX-License-Identifier: GPL-2.0+
5 5 #
6 6  
7   -obj-y := udoo.o
  7 +obj-y := udoo.o udoo_spl.o
board/udoo/clocks.cfg
View file @ 78506c2
1   -/*
2   - * Copyright (C) 2013 Boundary Devices
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - *
6   - * Device Configuration Data (DCD)
7   - *
8   - * Each entry must have the format:
9   - * Addr-type Address Value
10   - *
11   - * where:
12   - * Addr-type register length (1,2 or 4 bytes)
13   - * Address absolute address of the register
14   - * value value to be stored in the register
15   - */
16   -
17   -/* set the default clock gate to save power */
18   -DATA 4, CCM_CCGR0, 0x00C03F3F
19   -DATA 4, CCM_CCGR1, 0x0030FC03
20   -DATA 4, CCM_CCGR2, 0x0FFFC000
21   -DATA 4, CCM_CCGR3, 0x3FF00000
22   -DATA 4, CCM_CCGR4, 0x00FFF300
23   -DATA 4, CCM_CCGR5, 0x0F0000C3
24   -DATA 4, CCM_CCGR6, 0x000003FF
25   -
26   -/* enable AXI cache for VDOA/VPU/IPU */
27   -DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
28   -
29   -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
30   -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
31   -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
board/udoo/ddr-setup.cfg
View file @ 78506c2
1   -/*
2   - * Copyright (C) 2013 Boundary Devices
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - *
6   - * Device Configuration Data (DCD)
7   - *
8   - * Each entry must have the format:
9   - * Addr-type Address Value
10   - *
11   - * where:
12   - * Addr-type register length (1,2 or 4 bytes)
13   - * Address absolute address of the register
14   - * value value to be stored in the register
15   - */
16   -
17   -/*
18   - * DDR3 settings
19   - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
20   - * memory bus width: 64 bits x16/x32/x64
21   - * MX6DL ddr is limited to 800 MHz(400 MHz clock)
22   - * memory bus width: 64 bits x16/x32/x64
23   - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
24   - * memory bus width: 32 bits x16/x32
25   - */
26   -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
27   -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
28   -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
29   -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
30   -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
31   -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
32   -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
33   -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
34   -
35   -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
36   -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
37   -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
38   -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
39   -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
40   -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
41   -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
42   -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
43   -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
44   -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
45   -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
46   -
47   -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
48   -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
49   -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
50   -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
51   -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
52   -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
53   -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
54   -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
55   -
56   -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
57   -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
58   -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
59   -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
60   -
61   -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
62   -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
63   -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
64   -
65   -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
66   -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
67   -
68   -/* (differential input) */
69   -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
70   -/* (differential input) */
71   -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
72   -/* disable ddr pullups */
73   -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
74   -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
75   -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
76   -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
77   -
78   -/* Read data DQ Byte0-3 delay */
79   -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
80   -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
81   -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
82   -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
83   -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
84   -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
85   -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
86   -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
... ... @@ -42,28 +42,28 @@
42 42  
43 43 int dram_init(void)
44 44 {
45   - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
  45 + gd->ram_size = imx_ddr_size();
46 46  
47 47 return 0;
48 48 }
49 49  
50 50 static iomux_v3_cfg_t const uart2_pads[] = {
51   - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
52   - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  51 + IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  52 + IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
53 53 };
54 54  
55 55 static iomux_v3_cfg_t const usdhc3_pads[] = {
56   - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57   - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58   - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59   - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60   - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61   - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56 + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  57 + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  58 + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59 + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60 + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61 + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 62 };
63 63  
64 64 static iomux_v3_cfg_t const wdog_pads[] = {
65   - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
66   - MX6_PAD_EIM_D19__GPIO3_IO19,
  65 + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  66 + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
67 67 };
68 68  
69 69 int mx6_rgmii_rework(struct phy_device *phydev)
70 70  
71 71  
72 72  
73 73  
74 74  
75 75  
76 76  
77 77  
78 78  
... ... @@ -96,43 +96,43 @@
96 96 }
97 97  
98 98 static iomux_v3_cfg_t const enet_pads1[] = {
99   - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
100   - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
101   - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
102   - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
103   - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
104   - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
105   - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
106   - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
107   - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
108   - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99 + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  100 + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  101 + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  102 + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  103 + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  104 + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  105 + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  106 + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  107 + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  108 + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 109 /* RGMII reset */
110   - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  110 + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
111 111 /* Ethernet power supply */
112   - MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
  112 + IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 113 /* pin 32 - 1 - (MODE0) all */
114   - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114 + IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
115 115 /* pin 31 - 1 - (MODE1) all */
116   - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  116 + IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
117 117 /* pin 28 - 1 - (MODE2) all */
118   - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  118 + IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
119 119 /* pin 27 - 1 - (MODE3) all */
120   - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  120 + IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
121 121 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
122   - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  122 + IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
123 123 };
124 124  
125 125 static iomux_v3_cfg_t const enet_pads2[] = {
126   - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
127   - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
128   - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
129   - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
130   - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  126 + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  127 + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  128 + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  129 + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  130 + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
131 131 };
132 132  
133 133 static void setup_iomux_enet(void)
134 134 {
135   - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  135 + SETUP_IOMUX_PADS(enet_pads1);
136 136 udelay(20);
137 137 gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
138 138  
139 139  
140 140  
... ... @@ -156,17 +156,17 @@
156 156 gpio_free(IMX_GPIO_NR(6, 28));
157 157 gpio_free(IMX_GPIO_NR(6, 29));
158 158  
159   - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  159 + SETUP_IOMUX_PADS(enet_pads2);
160 160 }
161 161  
162 162 static void setup_iomux_uart(void)
163 163 {
164   - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  164 + SETUP_IOMUX_PADS(uart2_pads);
165 165 }
166 166  
167 167 static void setup_iomux_wdog(void)
168 168 {
169   - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  169 + SETUP_IOMUX_PADS(wdog_pads);
170 170 gpio_direction_output(WDT_TRG, 0);
171 171 gpio_direction_output(WDT_EN, 1);
172 172 gpio_direction_input(WDT_TRG);
... ... @@ -212,7 +212,7 @@
212 212  
213 213 int board_mmc_init(bd_t *bis)
214 214 {
215   - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  215 + SETUP_IOMUX_PADS(usdhc3_pads);
216 216 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
217 217 usdhc_cfg.max_bus_width = 4;
218 218  
219 219  
220 220  
... ... @@ -242,14 +242,29 @@
242 242 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
243 243  
244 244 #ifdef CONFIG_CMD_SATA
245   - setup_sata();
  245 + if (is_cpu_type(MXC_CPU_MX6Q))
  246 + setup_sata();
246 247 #endif
247 248 return 0;
248 249 }
249 250  
  251 +int board_late_init(void)
  252 +{
  253 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  254 + if (is_cpu_type(MXC_CPU_MX6Q))
  255 + setenv("board_rev", "MX6Q");
  256 + else
  257 + setenv("board_rev", "MX6DL");
  258 +#endif
  259 + return 0;
  260 +}
  261 +
250 262 int checkboard(void)
251 263 {
252   - puts("Board: Udoo\n");
  264 + if (is_cpu_type(MXC_CPU_MX6Q))
  265 + puts("Board: Udoo Quad\n");
  266 + else
  267 + puts("Board: Udoo DualLite\n");
253 268  
254 269 return 0;
255 270 }
board/udoo/udoo.cfg
View file @ 78506c2
1   -/*
2   - * Copyright (C) 2013 Boundary Devices
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - *
6   - * Refer doc/README.imximage for more details about how-to configure
7   - * and create imximage boot image
8   - *
9   - * The syntax is taken as close as possible with the kwbimage
10   - */
11   -
12   -/* image version */
13   -IMAGE_VERSION 2
14   -
15   -/*
16   - * Boot Device : one of
17   - * spi, sd (the board has no nand neither onenand)
18   - */
19   -BOOT_FROM sd
20   -
21   -#define __ASSEMBLY__
22   -#include <config.h>
23   -#include "asm/arch/mx6-ddr.h"
24   -#include "asm/arch/iomux.h"
25   -#include "asm/arch/crm_regs.h"
26   -
27   -#include "ddr-setup.cfg"
28   -#include "1066mhz_4x256mx16.cfg"
29   -#include "clocks.cfg"
board/udoo/udoo_spl.c
Diff comments   View file @ 78506c2
  1 +/*
  2 + * Copyright (C) 2015 Udoo
  3 + * Author: Tungyi Lin <tungyilin1127@gmail.com>
  4 + * Richard Hu <hakahu@gmail.com>
  5 + * Based on board/wandboard/spl.c
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <asm/arch/clock.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +#include <asm/arch/iomux.h>
  12 +#include <asm/arch/mx6-pins.h>
  13 +#include <asm/errno.h>
  14 +#include <asm/gpio.h>
  15 +#include <asm/imx-common/iomux-v3.h>
  16 +#include <asm/imx-common/video.h>
  17 +#include <mmc.h>
  18 +#include <fsl_esdhc.h>
  19 +#include <asm/arch/crm_regs.h>
  20 +#include <asm/io.h>
  21 +#include <asm/arch/sys_proto.h>
  22 +#include <spl.h>
  23 +
  24 +DECLARE_GLOBAL_DATA_PTR;
  25 +
  26 +#if defined(CONFIG_SPL_BUILD)
  27 +#include <asm/arch/mx6-ddr.h>
  28 +
  29 +/*
  30 + * Driving strength:
  31 + * 0x30 == 40 Ohm
  32 + * 0x28 == 48 Ohm
  33 + */
  34 +#define IMX6DQ_DRIVE_STRENGTH 0x30
  35 +#define IMX6SDL_DRIVE_STRENGTH 0x28
  36 +
  37 +/* configure MX6Q/DUAL mmdc DDR io registers */
  38 +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  39 + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  40 + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  41 + .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  42 + .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  43 + .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  44 + .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  45 + .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  46 + .dram_sdba2 = 0x00000000,
  47 + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  48 + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  49 + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  50 + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  51 + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  52 + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  53 + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  54 + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  55 + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  56 + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  57 + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  58 + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  59 + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  60 + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  61 + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  62 + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  63 + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  64 + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  65 +};
  66 +
  67 +/* configure MX6Q/DUAL mmdc GRP io registers */
  68 +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  69 + .grp_ddr_type = 0x000c0000,
  70 + .grp_ddrmode_ctl = 0x00020000,
  71 + .grp_ddrpke = 0x00000000,
  72 + .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  73 + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  74 + .grp_ddrmode = 0x00020000,
  75 + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  76 + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  77 + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  78 + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  79 + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  80 + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  81 + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  82 + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  83 +};
  84 +
  85 +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  86 +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  87 + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  88 + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  89 + .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  90 + .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  91 + .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  92 + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  93 + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  94 + .dram_sdba2 = 0x00000000,
  95 + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  96 + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  97 + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  98 + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  99 + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  100 + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  101 + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  102 + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  103 + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  104 + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  105 + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  106 + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  107 + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  108 + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  109 + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  110 + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  111 + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  112 + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  113 +};
  114 +
  115 +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  116 +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  117 + .grp_ddr_type = 0x000c0000,
  118 + .grp_ddrmode_ctl = 0x00020000,
  119 + .grp_ddrpke = 0x00000000,
  120 + .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  121 + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  122 + .grp_ddrmode = 0x00020000,
  123 + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  124 + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  125 + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  126 + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  127 + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  128 + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  129 + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  130 + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  131 +};
  132 +
  133 +/* MT41K128M16JT-125 */
  134 +static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  135 + /* quad = 1066, duallite = 800 */
  136 + .mem_speed = 1066,
  137 + .density = 2,
  138 + .width = 16,
  139 + .banks = 8,
  140 + .rowaddr = 14,
  141 + .coladdr = 10,
  142 + .pagesz = 2,
  143 + .trcd = 1375,
  144 + .trcmin = 4875,
  145 + .trasmin = 3500,
  146 + .SRT = 0,
  147 +};
  148 +
  149 +static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
  150 + .p0_mpwldectrl0 = 0x00350035,
  151 + .p0_mpwldectrl1 = 0x001F001F,
  152 + .p1_mpwldectrl0 = 0x00010001,
  153 + .p1_mpwldectrl1 = 0x00010001,
  154 + .p0_mpdgctrl0 = 0x43510360,
  155 + .p0_mpdgctrl1 = 0x0342033F,
  156 + .p1_mpdgctrl0 = 0x033F033F,
  157 + .p1_mpdgctrl1 = 0x03290266,
  158 + .p0_mprddlctl = 0x4B3E4141,
  159 + .p1_mprddlctl = 0x47413B4A,
  160 + .p0_mpwrdlctl = 0x42404843,
  161 + .p1_mpwrdlctl = 0x4C3F4C45,
  162 +};
  163 +
  164 +static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  165 + .p0_mpwldectrl0 = 0x002F0038,
  166 + .p0_mpwldectrl1 = 0x001F001F,
  167 + .p1_mpwldectrl0 = 0x001F001F,
  168 + .p1_mpwldectrl1 = 0x001F001F,
  169 + .p0_mpdgctrl0 = 0x425C0251,
  170 + .p0_mpdgctrl1 = 0x021B021E,
  171 + .p1_mpdgctrl0 = 0x021B021E,
  172 + .p1_mpdgctrl1 = 0x01730200,
  173 + .p0_mprddlctl = 0x45474C45,
  174 + .p1_mprddlctl = 0x44464744,
  175 + .p0_mpwrdlctl = 0x3F3F3336,
  176 + .p1_mpwrdlctl = 0x32383630,
  177 +};
  178 +
  179 +/* DDR 64bit 1GB */
  180 +static struct mx6_ddr_sysinfo mem_qdl = {
  181 + .dsize = 2,
  182 + .cs1_mirror = 0,
  183 + /* config for full 4GB range so that get_mem_size() works */
  184 + .cs_density = 32,
  185 + .ncs = 1,
  186 + .bi_on = 1,
  187 + /* quad = 2, duallite = 1 */
  188 + .rtt_nom = 2,
  189 + /* quad = 2, duallite = 1 */
  190 + .rtt_wr = 2,
  191 + .ralat = 5,
  192 + .walat = 0,
  193 + .mif3_mode = 3,
  194 + .rst_to_cke = 0x23,
  195 + .sde_to_rst = 0x10,
  196 +};
  197 +
  198 +static void ccgr_init(void)
  199 +{
  200 + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  201 +
  202 + /* set the default clock gate to save power */
  203 + writel(0x00C03F3F, &ccm->CCGR0);
  204 + writel(0x0030FC03, &ccm->CCGR1);
  205 + writel(0x0FFFC000, &ccm->CCGR2);
  206 + writel(0x3FF00000, &ccm->CCGR3);
  207 + writel(0x00FFF300, &ccm->CCGR4);
  208 + writel(0x0F0000C3, &ccm->CCGR5);
  209 + writel(0x000003FF, &ccm->CCGR6);
  210 +}
  211 +
  212 +static void gpr_init(void)
  213 +{
  214 + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  215 +
  216 + /* enable AXI cache for VDOA/VPU/IPU */
  217 + writel(0xF00000FF, &iomux->gpr[4]);
  218 + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  219 + writel(0x007F007F, &iomux->gpr[6]);
  220 + writel(0x007F007F, &iomux->gpr[7]);
  221 +}
  222 +
  223 +static void spl_dram_init(void)
  224 +{
  225 + if (is_cpu_type(MXC_CPU_MX6DL)) {
  226 + mt41k128m16jt_125.mem_speed = 800;
  227 + mem_qdl.rtt_nom = 1;
  228 + mem_qdl.rtt_wr = 1;
  229 +
  230 + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  231 + mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
  232 + } else if (is_cpu_type(MXC_CPU_MX6Q)) {
  233 + mt41k128m16jt_125.mem_speed = 1066;
  234 + mem_qdl.rtt_nom = 2;
  235 + mem_qdl.rtt_wr = 2;
  236 +
  237 + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  238 + mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
  239 + }
  240 +
  241 + udelay(100);
  242 +}
  243 +
  244 +void board_init_f(ulong dummy)
  245 +{
  246 + ccgr_init();
  247 +
  248 + /* setup AIPS and disable watchdog */
  249 + arch_cpu_init();
  250 +
  251 + gpr_init();
  252 +
  253 + /* iomux */
  254 + board_early_init_f();
  255 +
  256 + /* setup GP timer */
  257 + timer_init();
  258 +
  259 + /* UART clocks enabled and gd valid - init serial console */
  260 + preloader_console_init();
  261 +
  262 + /* DDR initialization */
  263 + spl_dram_init();
  264 +
  265 + /* Clear the BSS. */
  266 + memset(__bss_start, 0, __bss_end - __bss_start);
  267 +
  268 + /* load/boot image from boot device */
  269 + board_init_r(NULL, 0);
  270 +}
  271 +#endif
configs/udoo_defconfig
Diff comments   View file @ 78506c2
  1 +CONFIG_SPL=y
  2 +CONFIG_ARM=y
  3 +CONFIG_DM=y
  4 +CONFIG_DM_THERMAL=y
  5 +CONFIG_TARGET_UDOO=y
  6 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
configs/udoo_quad_defconfig
View file @ 78506c2
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_UDOO=y
3   -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024"
4   -# CONFIG_CMD_IMLS is not set
5   -# CONFIG_CMD_FLASH is not set
include/configs/udoo.h
Diff comments   View file @ 78506c2
... ... @@ -11,6 +11,10 @@
11 11  
12 12 #include "mx6_common.h"
13 13  
  14 +#define CONFIG_SPL_MMC_SUPPORT
  15 +#define CONFIG_SPL_FAT_SUPPORT
  16 +#include "imx6_spl.h"
  17 +
14 18 #define MACH_TYPE_UDOO 4800
15 19 #define CONFIG_MACH_TYPE MACH_TYPE_UDOO
16 20  
... ... @@ -18,6 +22,7 @@
18 22 #define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
19 23  
20 24 #define CONFIG_BOARD_EARLY_INIT_F
  25 +#define CONFIG_BOARD_LATE_INIT
21 26  
22 27 #define CONFIG_MXC_UART
23 28 #define CONFIG_MXC_UART_BASE UART2_BASE
... ... @@ -58,7 +63,7 @@
58 63 /* MMC Configuration */
59 64 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
60 65  
61   -#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb"
  66 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
62 67  
63 68 #define CONFIG_EXTRA_ENV_SETTINGS \
64 69 "script=boot.scr\0" \
... ... @@ -67,7 +72,7 @@
67 72 "splashpos=m,m\0" \
68 73 "fdt_high=0xffffffff\0" \
69 74 "initrd_high=0xffffffff\0" \
70   - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \" \
  75 + "fdt_file=undefined\0" \" \
71 76 "fdt_addr=0x18000000\0" \
72 77 "boot_fdt=try\0" \
73 78 "ip_dyn=yes\0" \
74 79  
... ... @@ -134,9 +139,17 @@
134 139 "fi; " \
135 140 "else " \
136 141 "bootz; " \
137   - "fi;\0"
  142 + "fi;\0" \
  143 + "findfdt=" \
  144 + "if test $board_rev = MX6Q ; then " \
  145 + "setenv fdt_file imx6q-udoo.dtb; fi; " \
  146 + "if test $board_rev = MX6DL ; then " \
  147 + "setenv fdt_file imx6dl-udoo.dtb; fi; " \
  148 + "if test $fdt_file = undefined; then " \
  149 + "echo WARNING: Could not determine dtb to use; fi; \0"
138 150  
139 151 #define CONFIG_BOOTCOMMAND \
  152 + "run findfdt; " \
140 153 "mmc dev ${mmcdev}; if mmc rescan; then " \
141 154 "if run loadbootscript; then " \
142 155 "run bootscript; " \