Eric Lee / smarc-uboot

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Commit 786a08e0dd3d0505e10cc93622ce5db696c627e9

Authored by Bin Meng
Committed by Simon Glass
1 parent df07d91956
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: Move VGA option rom macros to Kconfig 

Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Showing 9 changed files with 30 additions and 11 deletions Side-by-side Diff

... ... @@ -1035,8 +1035,8 @@
1035 1035 IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
1036 1036 endif
1037 1037  
1038   -ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
1039   -IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
  1038 +ifneq ($(CONFIG_HAVE_VGA_BIOS),)
  1039 +IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
1040 1040 endif
1041 1041  
1042 1042 quiet_cmd_ifdtool = IFDTOOL $@
... ... @@ -287,6 +287,28 @@
287 287 help
288 288 The running frequency in MHz of Time-Stamp Counter (TSC).
289 289  
  290 +config HAVE_VGA_BIOS
  291 + bool "Add a VGA BIOS image"
  292 + help
  293 + Select this option if you have a VGA BIOS image that you would
  294 + like to add to your ROM.
  295 +
  296 +config VGA_BIOS_FILE
  297 + string "VGA BIOS image filename"
  298 + depends on HAVE_VGA_BIOS
  299 + default "vga.bin"
  300 + help
  301 + The filename of the VGA BIOS image in the board directory.
  302 +
  303 +config VGA_BIOS_ADDR
  304 + hex "VGA BIOS image location"
  305 + depends on HAVE_VGA_BIOS
  306 + default 0xfff90000
  307 + help
  308 + The location of VGA BIOS image in the SPI flash. For example, base
  309 + address of 0xfff90000 indicates that the image will be put at offset
  310 + 0x90000 from the beginning of a 1MB flash device.
  311 +
290 312 menu "System tables"
291 313  
292 314 config GENERATE_PIRQ_TABLE
configs/chromebook_link_defconfig
Diff comments   View file @ 786a08e
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
4 4 CONFIG_TARGET_CHROMEBOOK_LINK=y
5 5 CONFIG_HAVE_MRC=y
  6 +CONFIG_HAVE_VGA_BIOS=y
6 7 # CONFIG_CMD_IMLS is not set
7 8 # CONFIG_CMD_FLASH is not set
8 9 # CONFIG_CMD_SETEXPR is not set
configs/chromebox_panther_defconfig
Diff comments   View file @ 786a08e
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
4 4 CONFIG_TARGET_CHROMEBOX_PANTHER=y
5 5 CONFIG_HAVE_MRC=y
  6 +CONFIG_HAVE_VGA_BIOS=y
6 7 # CONFIG_CMD_IMLS is not set
7 8 # CONFIG_CMD_FLASH is not set
8 9 # CONFIG_CMD_SETEXPR is not set
configs/minnowmax_defconfig
Diff comments   View file @ 786a08e
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
4 4 CONFIG_TARGET_MINNOWMAX=y
5 5 CONFIG_HAVE_INTEL_ME=y
  6 +CONFIG_HAVE_VGA_BIOS=y
6 7 CONFIG_SMP=y
7 8 CONFIG_GENERATE_SFI_TABLE=y
8 9 CONFIG_CMD_CPU=y
... ... @@ -79,7 +79,7 @@
79 79 * ./northbridge/intel/sandybridge/systemagent-r6.bin
80 80  
81 81 The 3rd one should be renamed to mrc.bin.
82   -As for the video ROM, you can get it here [3].
  82 +As for the video ROM, you can get it here [3] and rename it to vga.bin.
83 83 Make sure all these binary blobs are put in the board directory.
84 84  
85 85 Now you can build U-Boot and obtain u-boot.rom:
drivers/pci/pci_rom.c
Diff comments   View file @ 786a08e
... ... @@ -79,8 +79,8 @@
79 79 if (vendev != mapped_vendev)
80 80 debug("Device ID mapped to %#08x\n", mapped_vendev);
81 81  
82   -#ifdef CONFIG_X86_OPTION_ROM_ADDR
83   - rom_address = CONFIG_X86_OPTION_ROM_ADDR;
  82 +#ifdef CONFIG_VGA_BIOS_ADDR
  83 + rom_address = CONFIG_VGA_BIOS_ADDR;
84 84 #else
85 85  
86 86 if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) {
include/configs/minnowmax.h
Diff comments   View file @ 786a08e
... ... @@ -52,9 +52,6 @@
52 52 #undef CONFIG_USB_MAX_CONTROLLER_COUNT
53 53 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
54 54  
55   -#define CONFIG_X86_OPTION_ROM_FILE vga.bin
56   -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
57   -
58 55 #define VIDEO_IO_OFFSET 0
59 56 #define CONFIG_X86EMU_RAW_IO
60 57 #define CONFIG_VGA_AS_SINGLE_DEVICE
include/configs/x86-chromebook.h
Diff comments   View file @ 786a08e
... ... @@ -26,9 +26,6 @@
26 26 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
27 27 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
28 28  
29   -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
30   -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
31   -
32 29 #define CONFIG_PCI_MEM_BUS 0xe0000000
33 30 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
34 31 #define CONFIG_PCI_MEM_SIZE 0x10000000