Eric Lee / smarc-uboot

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Commit 78ad457b2dbd0fe6cdc7ea42a69774a72ed007b9

Authored by Andre Przywara
Committed by Tom Rini
1 parent 8993056fb3
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: shrink exception table code 

In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions there. Right now we just put an unconditional branch
there, then use a macro to place the 34 instructions *per entry* after
that. That effectivly doubles the size of our exception table, which
is quite a waste, given that we use it mostly for debugging purposes.

Since the register saving part is actually identical, let's just convert
that macro into a function, and "bl" into it directly from the exception
slot, of course after having saved at least the original LR.
This saves us about 950 bytes of code, which is quite a relief for some
tight SPLs, in particular the 64-bit Allwinner ones.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Showing 1 changed file with 56 additions and 73 deletions Side-by-side Diff

arch/arm/cpu/armv8/exceptions.S
Diff comments   View file @ 78ad457
... ... @@ -12,12 +12,65 @@
12 12 #include <linux/linkage.h>
13 13  
14 14 /*
  15 + * Exception vectors.
  16 + */
  17 + .align 11
  18 + .globl vectors
  19 +vectors:
  20 + .align 7 /* Current EL Synchronous Thread */
  21 + stp x29, x30, [sp, #-16]!
  22 + bl _exception_entry
  23 + bl do_bad_sync
  24 + b exception_exit
  25 +
  26 + .align 7 /* Current EL IRQ Thread */
  27 + stp x29, x30, [sp, #-16]!
  28 + bl _exception_entry
  29 + bl do_bad_irq
  30 + b exception_exit
  31 +
  32 + .align 7 /* Current EL FIQ Thread */
  33 + stp x29, x30, [sp, #-16]!
  34 + bl _exception_entry
  35 + bl do_bad_fiq
  36 + b exception_exit
  37 +
  38 + .align 7 /* Current EL Error Thread */
  39 + stp x29, x30, [sp, #-16]!
  40 + bl _exception_entry
  41 + bl do_bad_error
  42 + b exception_exit
  43 +
  44 + .align 7 /* Current EL Synchronous Handler */
  45 + stp x29, x30, [sp, #-16]!
  46 + bl _exception_entry
  47 + bl do_sync
  48 + b exception_exit
  49 +
  50 + .align 7 /* Current EL IRQ Handler */
  51 + stp x29, x30, [sp, #-16]!
  52 + bl _exception_entry
  53 + bl do_irq
  54 + b exception_exit
  55 +
  56 + .align 7 /* Current EL FIQ Handler */
  57 + stp x29, x30, [sp, #-16]!
  58 + bl _exception_entry
  59 + bl do_fiq
  60 + b exception_exit
  61 +
  62 + .align 7 /* Current EL Error Handler */
  63 + stp x29, x30, [sp, #-16]!
  64 + bl _exception_entry
  65 + bl do_error
  66 + b exception_exit
  67 +
  68 +/*
15 69 * Enter Exception.
16 70 * This will save the processor state that is ELR/X0~X30
17 71 * to the stack frame.
18 72 */
19   -.macro exception_entry
20   - stp x29, x30, [sp, #-16]!
  73 +_exception_entry:
21 74 stp x27, x28, [sp, #-16]!
22 75 stp x25, x26, [sp, #-16]!
23 76 stp x23, x24, [sp, #-16]!
24 77  
... ... @@ -46,78 +99,8 @@
46 99 0:
47 100 stp x2, x0, [sp, #-16]!
48 101 mov x0, sp
49   -.endm
  102 + ret
50 103  
51   -/*
52   - * Exception vectors.
53   - */
54   - .align 11
55   - .globl vectors
56   -vectors:
57   - .align 7
58   - b _do_bad_sync /* Current EL Synchronous Thread */
59   -
60   - .align 7
61   - b _do_bad_irq /* Current EL IRQ Thread */
62   -
63   - .align 7
64   - b _do_bad_fiq /* Current EL FIQ Thread */
65   -
66   - .align 7
67   - b _do_bad_error /* Current EL Error Thread */
68   -
69   - .align 7
70   - b _do_sync /* Current EL Synchronous Handler */
71   -
72   - .align 7
73   - b _do_irq /* Current EL IRQ Handler */
74   -
75   - .align 7
76   - b _do_fiq /* Current EL FIQ Handler */
77   -
78   - .align 7
79   - b _do_error /* Current EL Error Handler */
80   -
81   -
82   -_do_bad_sync:
83   - exception_entry
84   - bl do_bad_sync
85   - b exception_exit
86   -
87   -_do_bad_irq:
88   - exception_entry
89   - bl do_bad_irq
90   - b exception_exit
91   -
92   -_do_bad_fiq:
93   - exception_entry
94   - bl do_bad_fiq
95   - b exception_exit
96   -
97   -_do_bad_error:
98   - exception_entry
99   - bl do_bad_error
100   - b exception_exit
101   -
102   -_do_sync:
103   - exception_entry
104   - bl do_sync
105   - b exception_exit
106   -
107   -_do_irq:
108   - exception_entry
109   - bl do_irq
110   - b exception_exit
111   -
112   -_do_fiq:
113   - exception_entry
114   - bl do_fiq
115   - b exception_exit
116   -
117   -_do_error:
118   - exception_entry
119   - bl do_error
120   - b exception_exit
121 104  
122 105 exception_exit:
123 106 ldp x2, x0, [sp],#16