Eric Lee / smarc-uboot

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Commit 78bbc5ce151c5a484bb51bf1866b4a993ffc16ec

Authored by Peter Tyser
Committed by Andrew Fleming-AFLEMING
1 parent 487dcb4fb8
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

XPedite5200 board support 

Initial support for Extreme Engineering Solutions XPedite5200 -
a MPC8548-based PMC single board computer.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Showing 5 changed files with 106 additions and 5 deletions Side-by-side Diff

... ... @@ -413,6 +413,7 @@
413 413  
414 414 Peter Tyser <ptyser@xes-inc.com>
415 415  
  416 + XPEDITE5200 MPC8548
416 417 XPEDITE5370 MPC8572
417 418  
418 419 David Updegraff <dave@cray.com>
... ... @@ -385,6 +385,7 @@
385 385 TQM8548 \
386 386 TQM8555 \
387 387 TQM8560 \
  388 + XPEDITE5200 \
388 389 XPEDITE5370 \
389 390 "
390 391  
... ... @@ -2463,6 +2463,9 @@
2463 2463 echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
2464 2464 @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
2465 2465  
  2466 +XPEDITE5200_config: unconfig
  2467 + @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
  2468 +
2466 2469 XPEDITE5370_config: unconfig
2467 2470 @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
2468 2471  
board/xes/common/Makefile
Diff comments   View file @ 78bbc5c
... ... @@ -29,9 +29,10 @@
29 29  
30 30 LIB = $(obj)lib$(VENDOR).a
31 31  
  32 +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
32 33 COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
33 34 COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
34   -COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
  35 +COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
35 36  
36 37 SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
37 38 OBJS := $(addprefix $(obj),$(COBJS-y))
board/xes/common/fsl_85xx_pci.c
Diff comments   View file @ 78bbc5c
... ... @@ -34,6 +34,9 @@
34 34  
35 35 int first_free_busno = 0;
36 36  
  37 +#ifdef CONFIG_PCI1
  38 +static struct pci_controller pci1_hose;
  39 +#endif
37 40 #ifdef CONFIG_PCIE1
38 41 static struct pci_controller pcie1_hose;
39 42 #endif
... ... @@ -44,6 +47,7 @@
44 47 static struct pci_controller pcie3_hose;
45 48 #endif
46 49  
  50 +#ifdef CONFIG_MPC8572
47 51 /* Correlate host/agent POR bits to usable info. Table 4-14 */
48 52 struct host_agent_cfg_t {
49 53 uchar pcie_root[3];
50 54  
... ... @@ -81,7 +85,39 @@
81 85 {{0, 0, 0}, 4},
82 86 {{8, 0, 0}, 0},
83 87 };
  88 +#elif defined CONFIG_MPC8548
  89 +/* Correlate host/agent POR bits to usable info. Table 4-12 */
  90 +struct host_agent_cfg_t {
  91 + uchar pci_host[2];
  92 + uchar pcie_root[1];
  93 + uchar rio_host;
  94 +} host_agent_cfg[8] = {
  95 + {{1, 1}, {0}, 0},
  96 + {{1, 1}, {1}, 0},
  97 + {{1, 1}, {0}, 1},
  98 + {{0, 0}, {0}, 0}, /* reserved */
  99 + {{0, 1}, {1}, 0},
  100 + {{1, 1}, {1}, 0},
  101 + {{0, 1}, {1}, 1},
  102 + {{1, 1}, {1}, 1}
  103 +};
84 104  
  105 +/* Correlate port width POR bits to usable info. Table 4-13 */
  106 +struct io_port_cfg_t {
  107 + uchar pcie_width[1];
  108 + uchar rio_width;
  109 +} io_port_cfg[8] = {
  110 + {{0}, 0},
  111 + {{0}, 0},
  112 + {{0}, 0},
  113 + {{4}, 4},
  114 + {{4}, 4},
  115 + {{0}, 4},
  116 + {{0}, 4},
  117 + {{8}, 0},
  118 +};
  119 +#endif
  120 +
85 121 void pci_init_board(void)
86 122 {
87 123 struct pci_controller *hose;
88 124  
... ... @@ -94,9 +130,65 @@
94 130 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
95 131 struct pci_region *r;
96 132  
97   - debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
98   - devdisr, io_sel, host_agent);
  133 +#ifdef CONFIG_PCI1
  134 + uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
  135 + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
  136 + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  137 + uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
  138 + uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
99 139  
  140 + width = 0; /* Silence compiler warning... */
  141 + io_sel &= 0xf; /* Silence compiler warning... */
  142 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
  143 + hose = &pci1_hose;
  144 + host = host_agent_cfg[host_agent].pci_host[0];
  145 + r = hose->regions;
  146 +
  147 +
  148 + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  149 + printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
  150 + pci_32 ? 32 : 64,
  151 + pcix ? "PCIX" : "PCI",
  152 + pci_spd_norm ? ">=" : "<=",
  153 + pcix ? freq * 2 : freq,
  154 + host ? "host" : "agent",
  155 + pci_arb ? "arbiter" : "external-arbiter");
  156 +
  157 + /* inbound */
  158 + r += fsl_pci_setup_inbound_windows(r);
  159 +
  160 + /* outbound memory */
  161 + pci_set_region(r++,
  162 + CONFIG_SYS_PCI1_MEM_BASE,
  163 + CONFIG_SYS_PCI1_MEM_PHYS,
  164 + CONFIG_SYS_PCI1_MEM_SIZE,
  165 + PCI_REGION_MEM);
  166 +
  167 + /* outbound io */
  168 + pci_set_region(r++,
  169 + CONFIG_SYS_PCI1_IO_BASE,
  170 + CONFIG_SYS_PCI1_IO_PHYS,
  171 + CONFIG_SYS_PCI1_IO_SIZE,
  172 + PCI_REGION_IO);
  173 +
  174 + hose->region_count = r - hose->regions;
  175 +
  176 + hose->first_busno = first_free_busno;
  177 + pci_setup_indirect(hose, (int)&pci->cfg_addr,
  178 + (int)&pci->cfg_data);
  179 +
  180 + fsl_pci_init(hose);
  181 +
  182 + first_free_busno = hose->last_busno+1;
  183 + printf(" PCI1 on bus %02x - %02x\n",
  184 + hose->first_busno, hose->last_busno);
  185 + } else {
  186 + printf(" PCI1: disabled\n");
  187 + }
  188 +#elif defined CONFIG_MPC8548
  189 + /* PCI1 not present on MPC8572 */
  190 + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
  191 +#endif
100 192 #ifdef CONFIG_PCIE1
101 193 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
102 194 hose = &pcie1_hose;
... ... @@ -143,7 +235,7 @@
143 235 if (!host)
144 236 fsl_pci_config_unlock(hose);
145 237  
146   - first_free_busno = hose->last_busno+1;
  238 + first_free_busno = hose->last_busno + 1;
147 239 printf(" PCIE1 on bus %02x - %02x\n",
148 240 hose->first_busno, hose->last_busno);
149 241 }
... ... @@ -200,7 +292,6 @@
200 292 first_free_busno = hose->last_busno+1;
201 293 printf(" PCIE2 on bus %02x - %02x\n",
202 294 hose->first_busno, hose->last_busno);
203   -
204 295 }
205 296 #else
206 297 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
... ... @@ -267,6 +358,10 @@
267 358  
268 359 void ft_board_pci_setup(void *blob, bd_t *bd)
269 360 {
  361 + /* TODO - make node name (eg pci0) dynamic */
  362 +#ifdef CONFIG_PCI1
  363 + ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
  364 +#endif
270 365 #ifdef CONFIG_PCIE1
271 366 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
272 367 #endif