net: gmac_rockchip: Add support for the RK3368 GMAC

The GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

net: gmac_rockchip: Add support for the RK3368 GMAC
The GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Philipp Tomsich
1 parent cf8aceb1c9
Showing 2 changed files with 79 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-rockchip/grf_rk3368.h
drivers/net/gmac_rockchip.c
@@ -129,5 +129,6 @@
 	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
 	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
 };
+
 #endif
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
@@ -83,6 +84,38 @@
 	return 0;
 }
  
+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3368_grf *grf;
+	int clk;
+	enum {
+		RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
+		RK3368_GMAC_CLK_SEL_25M = 3 << 4,
+		RK3368_GMAC_CLK_SEL_125M = 0 << 4,
+		RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
+	};
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3368_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3368_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3368_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3399_grf_regs *grf;
@@ -129,6 +162,44 @@
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
  
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3368_grf *grf;
+	enum {
+		RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
+		RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+		RK3368_RMII_MODE_MASK  = BIT(6),
+		RK3368_RMII_MODE       = BIT(6),
+	};
+	enum {
+		RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
+		RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
+		RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
+		RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
+		RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+		RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
+		RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+		RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15,
+		     RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+		     RK3368_GMAC_PHY_INTF_SEL_RGMII);
+
+	rk_clrsetreg(&grf->soc_con16,
+		     RK3368_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3368_TXCLK_DLY_ENA_GMAC_MASK |
+		     RK3368_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3368_CLK_TX_DL_CFG_GMAC_MASK,
+		     RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
+		     RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3399_grf_regs *grf;
@@ -208,6 +279,11 @@
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
  
+const struct rk_gmac_ops rk3368_gmac_ops = {
+	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3399_gmac_ops = {
 	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
@@ -216,6 +292,8 @@
 static const struct udevice_id rockchip_gmac_ids[] = {
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3368-gmac",
+	  .data = (ulong)&rk3368_gmac_ops },
 	{ .compatible = "rockchip,rk3399-gmac",
 	  .data = (ulong)&rk3399_gmac_ops },
 	{ }
...	...	@@ -129,5 +129,6 @@
129	129	MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
130	130	MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
131	131	};
	132	+
132	133	#endif
...	...	@@ -16,6 +16,7 @@
16	16	#include <asm/arch/clock.h>
17	17	#include <asm/arch/hardware.h>
18	18	#include <asm/arch/grf_rk3288.h>
	19	+#include <asm/arch/grf_rk3368.h>
19	20	#include <asm/arch/grf_rk3399.h>
20	21	#include <dm/pinctrl.h>
21	22	#include <dt-bindings/clock/rk3288-cru.h>
...	...	@@ -83,6 +84,38 @@
83	84	return 0;
84	85	}
85	86
	87	+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
	88	+{
	89	+ struct rk3368_grf *grf;
	90	+ int clk;
	91	+ enum {
	92	+ RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
	93	+ RK3368_GMAC_CLK_SEL_25M = 3 << 4,
	94	+ RK3368_GMAC_CLK_SEL_125M = 0 << 4,
	95	+ RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
	96	+ };
	97	+
	98	+ switch (priv->phydev->speed) {
	99	+ case 10:
	100	+ clk = RK3368_GMAC_CLK_SEL_2_5M;
	101	+ break;
	102	+ case 100:
	103	+ clk = RK3368_GMAC_CLK_SEL_25M;
	104	+ break;
	105	+ case 1000:
	106	+ clk = RK3368_GMAC_CLK_SEL_125M;
	107	+ break;
	108	+ default:
	109	+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
	110	+ return -EINVAL;
	111	+ }
	112	+
	113	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	114	+ rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
	115	+
	116	+ return 0;
	117	+}
	118	+
86	119	static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
87	120	{
88	121	struct rk3399_grf_regs *grf;
...	...	@@ -129,6 +162,44 @@
129	162	pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
130	163	}
131	164
	165	+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	166	+{
	167	+ struct rk3368_grf *grf;
	168	+ enum {
	169	+ RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
	170	+ RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
	171	+ RK3368_RMII_MODE_MASK = BIT(6),
	172	+ RK3368_RMII_MODE = BIT(6),
	173	+ };
	174	+ enum {
	175	+ RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
	176	+ RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
	177	+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
	178	+ RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
	179	+ RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
	180	+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
	181	+ RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
	182	+ RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
	183	+ RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
	184	+ RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
	185	+ };
	186	+
	187	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	188	+ rk_clrsetreg(&grf->soc_con15,
	189	+ RK3368_RMII_MODE_MASK \| RK3368_GMAC_PHY_INTF_SEL_MASK,
	190	+ RK3368_GMAC_PHY_INTF_SEL_RGMII);
	191	+
	192	+ rk_clrsetreg(&grf->soc_con16,
	193	+ RK3368_RXCLK_DLY_ENA_GMAC_MASK \|
	194	+ RK3368_TXCLK_DLY_ENA_GMAC_MASK \|
	195	+ RK3368_CLK_RX_DL_CFG_GMAC_MASK \|
	196	+ RK3368_CLK_TX_DL_CFG_GMAC_MASK,
	197	+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE \|
	198	+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE \|
	199	+ pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT \|
	200	+ pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
	201	+}
	202	+
132	203	static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
133	204	{
134	205	struct rk3399_grf_regs *grf;
...	...	@@ -208,6 +279,11 @@
208	279	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
209	280	};
210	281
	282	+const struct rk_gmac_ops rk3368_gmac_ops = {
	283	+ .fix_mac_speed = rk3368_gmac_fix_mac_speed,
	284	+ .set_to_rgmii = rk3368_gmac_set_to_rgmii,
	285	+};
	286	+
211	287	const struct rk_gmac_ops rk3399_gmac_ops = {
212	288	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
213	289	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
...	...	@@ -216,6 +292,8 @@
216	292	static const struct udevice_id rockchip_gmac_ids[] = {
217	293	{ .compatible = "rockchip,rk3288-gmac",
218	294	.data = (ulong)&rk3288_gmac_ops },
	295	+ { .compatible = "rockchip,rk3368-gmac",
	296	+ .data = (ulong)&rk3368_gmac_ops },
219	297	{ .compatible = "rockchip,rk3399-gmac",
220	298	.data = (ulong)&rk3399_gmac_ops },
221	299	{ }