Eric Lee / smarc-uboot

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Commit 7961b9f6db19d039b4e6e9c21a9715b6d5b92393

Authored by Tom Rini
2 parents fee626c449 fef4a545b6
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge git://git.denx.de/u-boot-socfpga

Showing 17 changed files Side-by-side Diff

... ... @@ -698,16 +698,17 @@
698 698 select OF_CONTROL
699 699 select SPL_OF_CONTROL
700 700 select DM
701   - select DM_SPI_FLASH
702   - select DM_SPI
703 701 select ENABLE_ARM_SOC_BOOT0_HOOK
704 702 select ARCH_EARLY_INIT_R
705 703 select ARCH_MISC_INIT
706   - select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
707 704 select SYS_THUMB_BUILD
708 705 imply CMD_MTDPARTS
709 706 imply CRC32_VERIFY
  707 + imply DM_SPI
  708 + imply DM_SPI_FLASH
710 709 imply FAT_WRITE
  710 + imply HW_WATCHDOG
  711 + imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
711 712  
712 713 config ARCH_SUNXI
713 714 bool "Support sunxi (Allwinner) SoCs"
arch/arm/dts/socfpga_arria5_socdk.dts
Diff comments   View file @ 7961b9f
... ... @@ -88,7 +88,7 @@
88 88 u-boot,dm-pre-reloc;
89 89 #address-cells = <1>;
90 90 #size-cells = <1>;
91   - compatible = "n25q00";
  91 + compatible = "n25q00", "spi-flash";
92 92 reg = <0>; /* chip select */
93 93 spi-max-frequency = <50000000>;
94 94 m25p,fast-read;
arch/arm/dts/socfpga_cyclone5_is1.dts
Diff comments   View file @ 7961b9f
... ... @@ -87,7 +87,7 @@
87 87 u-boot,dm-pre-reloc;
88 88 #address-cells = <1>;
89 89 #size-cells = <1>;
90   - compatible = "n25q00";
  90 + compatible = "n25q00", "spi-flash";
91 91 reg = <0>; /* chip select */
92 92 spi-max-frequency = <100000000>;
93 93 m25p,fast-read;
arch/arm/dts/socfpga_cyclone5_socdk.dts
Diff comments   View file @ 7961b9f
... ... @@ -98,7 +98,7 @@
98 98 u-boot,dm-pre-reloc;
99 99 #address-cells = <1>;
100 100 #size-cells = <1>;
101   - compatible = "n25q00";
  101 + compatible = "n25q00", "spi-flash";
102 102 reg = <0>; /* chip select */
103 103 spi-max-frequency = <100000000>;
104 104 m25p,fast-read;
arch/arm/dts/socfpga_cyclone5_socrates.dts
Diff comments   View file @ 7961b9f
... ... @@ -68,7 +68,7 @@
68 68 flash0: n25q00@0 {
69 69 #address-cells = <1>;
70 70 #size-cells = <1>;
71   - compatible = "n25q00";
  71 + compatible = "n25q00", "spi-flash";
72 72 reg = <0>; /* chip select */
73 73 spi-max-frequency = <50000000>;
74 74 m25p,fast-read;
include/configs/socfpga_arria10_socdk.h
Diff comments   View file @ 7961b9f
... ... @@ -9,8 +9,6 @@
9 9  
10 10 #include <asm/arch/base_addr_a10.h>
11 11  
12   -#define CONFIG_HW_WATCHDOG
13   -
14 12 /* Booting Linux */
15 13 #define CONFIG_LOADADDR 0x01000000
16 14 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
include/configs/socfpga_arria5_socdk.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
15 13  
include/configs/socfpga_cyclone5_socdk.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
15 13  
include/configs/socfpga_de0_nano_soc.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
15 13  
include/configs/socfpga_de10_nano.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
15 13  
include/configs/socfpga_de1_soc.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
15 13  
include/configs/socfpga_is1.h
Diff comments   View file @ 7961b9f
... ... @@ -9,8 +9,6 @@
9 9  
10 10 #include <asm/arch/base_addr_ac5.h>
11 11  
12   -#define CONFIG_HW_WATCHDOG
13   -
14 12 /* Memory configurations */
15 13 #define PHYS_SDRAM_1_SIZE 0x10000000
16 14  
include/configs/socfpga_mcvevk.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
15 13  
include/configs/socfpga_sockit.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
15 13  
include/configs/socfpga_socrates.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
15 13  
include/configs/socfpga_sr1500.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
15 13  
include/configs/socfpga_vining_fpga.h
Diff comments   View file @ 7961b9f
... ... @@ -8,8 +8,6 @@
8 8  
9 9 #include <asm/arch/base_addr_ac5.h>
10 10  
11   -#define CONFIG_HW_WATCHDOG
12   -
13 11 /* Memory configurations */
14 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
15 13