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Commit 799e125cca9f75a6e3bc87676266f8da4ebefcfd

Authored by Jiandong Zheng
Committed by Tom Rini
1 parent 2d66a0fd58
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: bcm281xx: net: Add Ethernet Driver 

The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom
SoC(s) and:
- supports multiple MAC blocks,
- provides support for the Broadcom GMAC.
This driver requires MII and PHYLIB.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

Showing 6 changed files with 1536 additions and 0 deletions Side-by-side Diff

drivers/net/Makefile
Diff comments   View file @ 799e125
... ... @@ -10,6 +10,8 @@
10 10 obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
11 11 obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
12 12 obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
  13 +obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
  14 +obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
13 15 obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
14 16 obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
15 17 obj-$(CONFIG_CS8900) += cs8900.o
drivers/net/bcm-sf2-eth-gmac.c
Diff comments   View file @ 799e125
  1 +/*
  2 + * Copyright 2014 Broadcom Corporation.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifdef BCM_GMAC_DEBUG
  8 +#ifndef DEBUG
  9 +#define DEBUG
  10 +#endif
  11 +#endif
  12 +
  13 +#include <config.h>
  14 +#include <common.h>
  15 +#include <malloc.h>
  16 +#include <net.h>
  17 +#include <asm/io.h>
  18 +#include <phy.h>
  19 +
  20 +#include "bcm-sf2-eth.h"
  21 +#include "bcm-sf2-eth-gmac.h"
  22 +
  23 +#define SPINWAIT(exp, us) { \
  24 + uint countdown = (us) + 9; \
  25 + while ((exp) && (countdown >= 10)) {\
  26 + udelay(10); \
  27 + countdown -= 10; \
  28 + } \
  29 +}
  30 +
  31 +static int gmac_disable_dma(struct eth_dma *dma, int dir);
  32 +static int gmac_enable_dma(struct eth_dma *dma, int dir);
  33 +
  34 +/* DMA Descriptor */
  35 +typedef struct {
  36 + /* misc control bits */
  37 + uint32_t ctrl1;
  38 + /* buffer count and address extension */
  39 + uint32_t ctrl2;
  40 + /* memory address of the date buffer, bits 31:0 */
  41 + uint32_t addrlow;
  42 + /* memory address of the date buffer, bits 63:32 */
  43 + uint32_t addrhigh;
  44 +} dma64dd_t;
  45 +
  46 +uint32_t g_dmactrlflags;
  47 +
  48 +static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags)
  49 +{
  50 + debug("%s enter\n", __func__);
  51 +
  52 + g_dmactrlflags &= ~mask;
  53 + g_dmactrlflags |= flags;
  54 +
  55 + /* If trying to enable parity, check if parity is actually supported */
  56 + if (g_dmactrlflags & DMA_CTRL_PEN) {
  57 + uint32_t control;
  58 +
  59 + control = readl(GMAC0_DMA_TX_CTRL_ADDR);
  60 + writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR);
  61 + if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) {
  62 + /*
  63 + * We *can* disable it, therefore it is supported;
  64 + * restore control register
  65 + */
  66 + writel(control, GMAC0_DMA_TX_CTRL_ADDR);
  67 + } else {
  68 + /* Not supported, don't allow it to be enabled */
  69 + g_dmactrlflags &= ~DMA_CTRL_PEN;
  70 + }
  71 + }
  72 +
  73 + return g_dmactrlflags;
  74 +}
  75 +
  76 +static inline void reg32_clear_bits(uint32_t reg, uint32_t value)
  77 +{
  78 + uint32_t v = readl(reg);
  79 + v &= ~(value);
  80 + writel(v, reg);
  81 +}
  82 +
  83 +static inline void reg32_set_bits(uint32_t reg, uint32_t value)
  84 +{
  85 + uint32_t v = readl(reg);
  86 + v |= value;
  87 + writel(v, reg);
  88 +}
  89 +
  90 +#ifdef BCM_GMAC_DEBUG
  91 +static void dma_tx_dump(struct eth_dma *dma)
  92 +{
  93 + dma64dd_t *descp = NULL;
  94 + uint8_t *bufp;
  95 + int i;
  96 +
  97 + printf("TX DMA Register:\n");
  98 + printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
  99 + readl(GMAC0_DMA_TX_CTRL_ADDR),
  100 + readl(GMAC0_DMA_TX_PTR_ADDR),
  101 + readl(GMAC0_DMA_TX_ADDR_LOW_ADDR),
  102 + readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR),
  103 + readl(GMAC0_DMA_TX_STATUS0_ADDR),
  104 + readl(GMAC0_DMA_TX_STATUS1_ADDR));
  105 +
  106 + printf("TX Descriptors:\n");
  107 + for (i = 0; i < TX_BUF_NUM; i++) {
  108 + descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
  109 + printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
  110 + descp->ctrl1, descp->ctrl2,
  111 + descp->addrhigh, descp->addrlow);
  112 + }
  113 +
  114 + printf("TX Buffers:\n");
  115 + /* Initialize TX DMA descriptor table */
  116 + for (i = 0; i < TX_BUF_NUM; i++) {
  117 + bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE);
  118 + printf("buf%d:0x%x; ", i, (uint32_t)bufp);
  119 + }
  120 + printf("\n");
  121 +}
  122 +
  123 +static void dma_rx_dump(struct eth_dma *dma)
  124 +{
  125 + dma64dd_t *descp = NULL;
  126 + uint8_t *bufp;
  127 + int i;
  128 +
  129 + printf("RX DMA Register:\n");
  130 + printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
  131 + readl(GMAC0_DMA_RX_CTRL_ADDR),
  132 + readl(GMAC0_DMA_RX_PTR_ADDR),
  133 + readl(GMAC0_DMA_RX_ADDR_LOW_ADDR),
  134 + readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR),
  135 + readl(GMAC0_DMA_RX_STATUS0_ADDR),
  136 + readl(GMAC0_DMA_RX_STATUS1_ADDR));
  137 +
  138 + printf("RX Descriptors:\n");
  139 + for (i = 0; i < RX_BUF_NUM; i++) {
  140 + descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
  141 + printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
  142 + descp->ctrl1, descp->ctrl2,
  143 + descp->addrhigh, descp->addrlow);
  144 + }
  145 +
  146 + printf("RX Buffers:\n");
  147 + for (i = 0; i < RX_BUF_NUM; i++) {
  148 + bufp = dma->rx_buf + i * RX_BUF_SIZE;
  149 + printf("buf%d:0x%x; ", i, (uint32_t)bufp);
  150 + }
  151 + printf("\n");
  152 +}
  153 +#endif
  154 +
  155 +static int dma_tx_init(struct eth_dma *dma)
  156 +{
  157 + dma64dd_t *descp = NULL;
  158 + uint8_t *bufp;
  159 + int i;
  160 + uint32_t ctrl;
  161 +
  162 + debug("%s enter\n", __func__);
  163 +
  164 + /* clear descriptor memory */
  165 + memset((void *)(dma->tx_desc_aligned), 0,
  166 + TX_BUF_NUM * sizeof(dma64dd_t));
  167 + memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE);
  168 +
  169 + /* Initialize TX DMA descriptor table */
  170 + for (i = 0; i < TX_BUF_NUM; i++) {
  171 + descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
  172 + bufp = dma->tx_buf + i * TX_BUF_SIZE;
  173 + /* clear buffer memory */
  174 + memset((void *)bufp, 0, TX_BUF_SIZE);
  175 +
  176 + ctrl = 0;
  177 + /* if last descr set endOfTable */
  178 + if (i == (TX_BUF_NUM-1))
  179 + ctrl = D64_CTRL1_EOT;
  180 + descp->ctrl1 = ctrl;
  181 + descp->ctrl2 = 0;
  182 + descp->addrlow = (uint32_t)bufp;
  183 + descp->addrhigh = 0;
  184 + }
  185 +
  186 + /* flush descriptor and buffer */
  187 + descp = dma->tx_desc_aligned;
  188 + bufp = dma->tx_buf;
  189 + flush_dcache_range((unsigned long)descp,
  190 + (unsigned long)(descp +
  191 + sizeof(dma64dd_t) * TX_BUF_NUM));
  192 + flush_dcache_range((unsigned long)(bufp),
  193 + (unsigned long)(bufp + TX_BUF_SIZE * TX_BUF_NUM));
  194 +
  195 + /* initialize the DMA channel */
  196 + writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);
  197 + writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
  198 +
  199 + /* now update the dma last descriptor */
  200 + writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK,
  201 + GMAC0_DMA_TX_PTR_ADDR);
  202 +
  203 + return 0;
  204 +}
  205 +
  206 +static int dma_rx_init(struct eth_dma *dma)
  207 +{
  208 + uint32_t last_desc;
  209 + dma64dd_t *descp = NULL;
  210 + uint8_t *bufp;
  211 + uint32_t ctrl;
  212 + int i;
  213 +
  214 + debug("%s enter\n", __func__);
  215 +
  216 + /* clear descriptor memory */
  217 + memset((void *)(dma->rx_desc_aligned), 0,
  218 + RX_BUF_NUM * sizeof(dma64dd_t));
  219 + /* clear buffer memory */
  220 + memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE);
  221 +
  222 + /* Initialize RX DMA descriptor table */
  223 + for (i = 0; i < RX_BUF_NUM; i++) {
  224 + descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
  225 + bufp = dma->rx_buf + i * RX_BUF_SIZE;
  226 + ctrl = 0;
  227 + /* if last descr set endOfTable */
  228 + if (i == (RX_BUF_NUM - 1))
  229 + ctrl = D64_CTRL1_EOT;
  230 + descp->ctrl1 = ctrl;
  231 + descp->ctrl2 = RX_BUF_SIZE;
  232 + descp->addrlow = (uint32_t)bufp;
  233 + descp->addrhigh = 0;
  234 +
  235 + last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK)
  236 + + sizeof(dma64dd_t);
  237 + }
  238 +
  239 + descp = dma->rx_desc_aligned;
  240 + bufp = dma->rx_buf;
  241 + /* flush descriptor and buffer */
  242 + flush_dcache_range((unsigned long)descp,
  243 + (unsigned long)(descp +
  244 + sizeof(dma64dd_t) * RX_BUF_NUM));
  245 + flush_dcache_range((unsigned long)(bufp),
  246 + (unsigned long)(bufp + RX_BUF_SIZE * RX_BUF_NUM));
  247 +
  248 + /* initailize the DMA channel */
  249 + writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);
  250 + writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR);
  251 +
  252 + /* now update the dma last descriptor */
  253 + writel(last_desc, GMAC0_DMA_RX_PTR_ADDR);
  254 +
  255 + return 0;
  256 +}
  257 +
  258 +static int dma_init(struct eth_dma *dma)
  259 +{
  260 + debug(" %s enter\n", __func__);
  261 +
  262 + /*
  263 + * Default flags: For backwards compatibility both
  264 + * Rx Overflow Continue and Parity are DISABLED.
  265 + */
  266 + dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0);
  267 +
  268 + debug("rx burst len 0x%x\n",
  269 + (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK)
  270 + >> D64_RC_BL_SHIFT);
  271 + debug("tx burst len 0x%x\n",
  272 + (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK)
  273 + >> D64_XC_BL_SHIFT);
  274 +
  275 + dma_tx_init(dma);
  276 + dma_rx_init(dma);
  277 +
  278 + /* From end of chip_init() */
  279 + /* enable the overflow continue feature and disable parity */
  280 + dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */,
  281 + DMA_CTRL_ROC /* value */);
  282 +
  283 + return 0;
  284 +}
  285 +
  286 +static int dma_deinit(struct eth_dma *dma)
  287 +{
  288 + debug(" %s enter\n", __func__);
  289 +
  290 + gmac_disable_dma(dma, MAC_DMA_RX);
  291 + gmac_disable_dma(dma, MAC_DMA_TX);
  292 +
  293 + free(dma->tx_buf);
  294 + dma->tx_buf = NULL;
  295 + free(dma->tx_desc);
  296 + dma->tx_desc = NULL;
  297 + dma->tx_desc_aligned = NULL;
  298 +
  299 + free(dma->rx_buf);
  300 + dma->rx_buf = NULL;
  301 + free(dma->rx_desc);
  302 + dma->rx_desc = NULL;
  303 + dma->rx_desc_aligned = NULL;
  304 +
  305 + return 0;
  306 +}
  307 +
  308 +int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
  309 +{
  310 + uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE;
  311 +
  312 + /* kick off the dma */
  313 + size_t len = length;
  314 + int txout = dma->cur_tx_index;
  315 + uint32_t flags;
  316 + dma64dd_t *descp = NULL;
  317 + uint32_t ctrl;
  318 + uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) +
  319 + sizeof(dma64dd_t)) & D64_XP_LD_MASK;
  320 + size_t buflen;
  321 +
  322 + debug("%s enter\n", __func__);
  323 +
  324 + /* load the buffer */
  325 + memcpy(bufp, packet, len);
  326 +
  327 + /* Add 4 bytes for Ethernet FCS/CRC */
  328 + buflen = len + 4;
  329 +
  330 + ctrl = (buflen & D64_CTRL2_BC_MASK);
  331 +
  332 + /* the transmit will only be one frame or set SOF, EOF */
  333 + /* also set int on completion */
  334 + flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF;
  335 +
  336 + /* txout points to the descriptor to uset */
  337 + /* if last descriptor then set EOT */
  338 + if (txout == (TX_BUF_NUM - 1)) {
  339 + flags |= D64_CTRL1_EOT;
  340 + last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK;
  341 + }
  342 +
  343 + /* write the descriptor */
  344 + descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout;
  345 + descp->addrlow = (uint32_t)bufp;
  346 + descp->addrhigh = 0;
  347 + descp->ctrl1 = flags;
  348 + descp->ctrl2 = ctrl;
  349 +
  350 + /* flush descriptor and buffer */
  351 + flush_dcache_range((unsigned long)descp,
  352 + (unsigned long)(descp + sizeof(dma64dd_t)));
  353 + flush_dcache_range((unsigned long)bufp,
  354 + (unsigned long)(bufp + TX_BUF_SIZE));
  355 +
  356 + /* now update the dma last descriptor */
  357 + writel(last_desc, GMAC0_DMA_TX_PTR_ADDR);
  358 +
  359 + /* tx dma should be enabled so packet should go out */
  360 +
  361 + /* update txout */
  362 + dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1);
  363 +
  364 + return 0;
  365 +}
  366 +
  367 +bool gmac_check_tx_done(struct eth_dma *dma)
  368 +{
  369 + /* wait for tx to complete */
  370 + uint32_t intstatus;
  371 + bool xfrdone = false;
  372 +
  373 + debug("%s enter\n", __func__);
  374 +
  375 + intstatus = readl(GMAC0_INT_STATUS_ADDR);
  376 +
  377 + debug("int(0x%x)\n", intstatus);
  378 + if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) {
  379 + xfrdone = true;
  380 + /* clear the int bits */
  381 + intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3);
  382 + writel(intstatus, GMAC0_INT_STATUS_ADDR);
  383 + } else {
  384 + debug("Tx int(0x%x)\n", intstatus);
  385 + }
  386 +
  387 + return xfrdone;
  388 +}
  389 +
  390 +int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
  391 +{
  392 + void *bufp, *datap;
  393 + size_t rcvlen = 0, buflen = 0;
  394 + uint32_t stat0 = 0, stat1 = 0;
  395 + uint32_t control, offset;
  396 + uint8_t statbuf[HWRXOFF*2];
  397 +
  398 + int index, curr, active;
  399 + dma64dd_t *descp = NULL;
  400 +
  401 + /* udelay(50); */
  402 +
  403 + /*
  404 + * this api will check if a packet has been received.
  405 + * If so it will return the address of the buffer and current
  406 + * descriptor index will be incremented to the
  407 + * next descriptor. Once done with the frame the buffer should be
  408 + * added back onto the descriptor and the lastdscr should be updated
  409 + * to this descriptor.
  410 + */
  411 + index = dma->cur_rx_index;
  412 + offset = (uint32_t)(dma->rx_desc_aligned);
  413 + stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK;
  414 + stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK;
  415 + curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
  416 + active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
  417 +
  418 + /* check if any frame */
  419 + if (index == curr)
  420 + return -1;
  421 +
  422 + debug("received packet\n");
  423 + debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active);
  424 + /* remove warning */
  425 + if (index == active)
  426 + ;
  427 +
  428 + /* get the packet pointer that corresponds to the rx descriptor */
  429 + bufp = dma->rx_buf + index * RX_BUF_SIZE;
  430 +
  431 + descp = (dma64dd_t *)(dma->rx_desc_aligned) + index;
  432 + /* flush descriptor and buffer */
  433 + flush_dcache_range((unsigned long)descp,
  434 + (unsigned long)(descp + sizeof(dma64dd_t)));
  435 + flush_dcache_range((unsigned long)bufp,
  436 + (unsigned long)(bufp + RX_BUF_SIZE));
  437 +
  438 + buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);
  439 +
  440 + stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR);
  441 + stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR);
  442 +
  443 + debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n",
  444 + (uint32_t)bufp, index, buflen, stat0, stat1);
  445 +
  446 + dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1);
  447 +
  448 + /* get buffer offset */
  449 + control = readl(GMAC0_DMA_RX_CTRL_ADDR);
  450 + offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT;
  451 + rcvlen = *(uint16_t *)bufp;
  452 +
  453 + debug("Received %d bytes\n", rcvlen);
  454 + /* copy status into temp buf then copy data from rx buffer */
  455 + memcpy(statbuf, bufp, offset);
  456 + datap = (void *)((uint32_t)bufp + offset);
  457 + memcpy(buf, datap, rcvlen);
  458 +
  459 + /* update descriptor that is being added back on ring */
  460 + descp->ctrl2 = RX_BUF_SIZE;
  461 + descp->addrlow = (uint32_t)bufp;
  462 + descp->addrhigh = 0;
  463 + /* flush descriptor */
  464 + flush_dcache_range((unsigned long)descp,
  465 + (unsigned long)(descp + sizeof(dma64dd_t)));
  466 +
  467 + /* set the lastdscr for the rx ring */
  468 + writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
  469 +
  470 + return (int)rcvlen;
  471 +}
  472 +
  473 +static int gmac_disable_dma(struct eth_dma *dma, int dir)
  474 +{
  475 + int status;
  476 +
  477 + debug("%s enter\n", __func__);
  478 +
  479 + if (dir == MAC_DMA_TX) {
  480 + /* address PR8249/PR7577 issue */
  481 + /* suspend tx DMA first */
  482 + writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR);
  483 + SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
  484 + D64_XS0_XS_MASK)) !=
  485 + D64_XS0_XS_DISABLED) &&
  486 + (status != D64_XS0_XS_IDLE) &&
  487 + (status != D64_XS0_XS_STOPPED), 10000);
  488 +
  489 + /*
  490 + * PR2414 WAR: DMA engines are not disabled until
  491 + * transfer finishes
  492 + */
  493 + writel(0, GMAC0_DMA_TX_CTRL_ADDR);
  494 + SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
  495 + D64_XS0_XS_MASK)) !=
  496 + D64_XS0_XS_DISABLED), 10000);
  497 +
  498 + /* wait for the last transaction to complete */
  499 + udelay(2);
  500 +
  501 + status = (status == D64_XS0_XS_DISABLED);
  502 + } else {
  503 + /*
  504 + * PR2414 WAR: DMA engines are not disabled until
  505 + * transfer finishes
  506 + */
  507 + writel(0, GMAC0_DMA_RX_CTRL_ADDR);
  508 + SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) &
  509 + D64_RS0_RS_MASK)) !=
  510 + D64_RS0_RS_DISABLED), 10000);
  511 +
  512 + status = (status == D64_RS0_RS_DISABLED);
  513 + }
  514 +
  515 + return status;
  516 +}
  517 +
  518 +static int gmac_enable_dma(struct eth_dma *dma, int dir)
  519 +{
  520 + uint32_t control;
  521 +
  522 + debug("%s enter\n", __func__);
  523 +
  524 + if (dir == MAC_DMA_TX) {
  525 + dma->cur_tx_index = 0;
  526 +
  527 + /*
  528 + * These bits 20:18 (burstLen) of control register can be
  529 + * written but will take effect only if these bits are
  530 + * valid. So this will not affect previous versions
  531 + * of the DMA. They will continue to have those bits set to 0.
  532 + */
  533 + control = readl(GMAC0_DMA_TX_CTRL_ADDR);
  534 +
  535 + control |= D64_XC_XE;
  536 + if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
  537 + control |= D64_XC_PD;
  538 +
  539 + writel(control, GMAC0_DMA_TX_CTRL_ADDR);
  540 +
  541 + /* initailize the DMA channel */
  542 + writel((uint32_t)(dma->tx_desc_aligned),
  543 + GMAC0_DMA_TX_ADDR_LOW_ADDR);
  544 + writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
  545 + } else {
  546 + dma->cur_rx_index = 0;
  547 +
  548 + control = (readl(GMAC0_DMA_RX_CTRL_ADDR) &
  549 + D64_RC_AE) | D64_RC_RE;
  550 +
  551 + if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
  552 + control |= D64_RC_PD;
  553 +
  554 + if (g_dmactrlflags & DMA_CTRL_ROC)
  555 + control |= D64_RC_OC;
  556 +
  557 + /*
  558 + * These bits 20:18 (burstLen) of control register can be
  559 + * written but will take effect only if these bits are
  560 + * valid. So this will not affect previous versions
  561 + * of the DMA. They will continue to have those bits set to 0.
  562 + */
  563 + control &= ~D64_RC_BL_MASK;
  564 + /* Keep default Rx burstlen */
  565 + control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK;
  566 + control |= HWRXOFF << D64_RC_RO_SHIFT;
  567 +
  568 + writel(control, GMAC0_DMA_RX_CTRL_ADDR);
  569 +
  570 + /*
  571 + * the rx descriptor ring should have
  572 + * the addresses set properly;
  573 + * set the lastdscr for the rx ring
  574 + */
  575 + writel(((uint32_t)(dma->rx_desc_aligned) +
  576 + (RX_BUF_NUM - 1) * RX_BUF_SIZE) &
  577 + D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
  578 + }
  579 +
  580 + return 0;
  581 +}
  582 +
  583 +bool gmac_mii_busywait(unsigned int timeout)
  584 +{
  585 + uint32_t tmp = 0;
  586 +
  587 + while (timeout > 10) {
  588 + tmp = readl(GMAC_MII_CTRL_ADDR);
  589 + if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) {
  590 + udelay(10);
  591 + timeout -= 10;
  592 + } else {
  593 + break;
  594 + }
  595 + }
  596 + return tmp & (1 << GMAC_MII_BUSY_SHIFT);
  597 +}
  598 +
  599 +int gmac_miiphy_read(const char *devname, unsigned char phyaddr,
  600 + unsigned char reg, unsigned short *value)
  601 +{
  602 + uint32_t tmp = 0;
  603 +
  604 + (void)devname;
  605 +
  606 + /* Busy wait timeout is 1ms */
  607 + if (gmac_mii_busywait(1000)) {
  608 + error("%s: Prepare MII read: MII/MDIO busy\n", __func__);
  609 + return -1;
  610 + }
  611 +
  612 + /* Read operation */
  613 + tmp = GMAC_MII_DATA_READ_CMD;
  614 + tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
  615 + (reg << GMAC_MII_PHY_REG_SHIFT);
  616 + debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg);
  617 + writel(tmp, GMAC_MII_DATA_ADDR);
  618 +
  619 + if (gmac_mii_busywait(1000)) {
  620 + error("%s: MII read failure: MII/MDIO busy\n", __func__);
  621 + return -1;
  622 + }
  623 +
  624 + *value = readl(GMAC_MII_DATA_ADDR) & 0xffff;
  625 + debug("MII read data 0x%x\n", *value);
  626 + return 0;
  627 +}
  628 +
  629 +int gmac_miiphy_write(const char *devname, unsigned char phyaddr,
  630 + unsigned char reg, unsigned short value)
  631 +{
  632 + uint32_t tmp = 0;
  633 +
  634 + (void)devname;
  635 +
  636 + /* Busy wait timeout is 1ms */
  637 + if (gmac_mii_busywait(1000)) {
  638 + error("%s: Prepare MII write: MII/MDIO busy\n", __func__);
  639 + return -1;
  640 + }
  641 +
  642 + /* Write operation */
  643 + tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff);
  644 + tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
  645 + (reg << GMAC_MII_PHY_REG_SHIFT));
  646 + debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n",
  647 + tmp, phyaddr, reg, value);
  648 + writel(tmp, GMAC_MII_DATA_ADDR);
  649 +
  650 + if (gmac_mii_busywait(1000)) {
  651 + error("%s: MII write failure: MII/MDIO busy\n", __func__);
  652 + return -1;
  653 + }
  654 +
  655 + return 0;
  656 +}
  657 +
  658 +void gmac_init_reset(void)
  659 +{
  660 + debug("%s enter\n", __func__);
  661 +
  662 + /* set command config reg CC_SR */
  663 + reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
  664 + udelay(GMAC_RESET_DELAY);
  665 +}
  666 +
  667 +void gmac_clear_reset(void)
  668 +{
  669 + debug("%s enter\n", __func__);
  670 +
  671 + /* clear command config reg CC_SR */
  672 + reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
  673 + udelay(GMAC_RESET_DELAY);
  674 +}
  675 +
  676 +static void gmac_enable_local(bool en)
  677 +{
  678 + uint32_t cmdcfg;
  679 +
  680 + debug("%s enter\n", __func__);
  681 +
  682 + /* read command config reg */
  683 + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
  684 +
  685 + /* put mac in reset */
  686 + gmac_init_reset();
  687 +
  688 + cmdcfg |= CC_SR;
  689 +
  690 + /* first deassert rx_ena and tx_ena while in reset */
  691 + cmdcfg &= ~(CC_RE | CC_TE);
  692 + /* write command config reg */
  693 + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
  694 +
  695 + /* bring mac out of reset */
  696 + gmac_clear_reset();
  697 +
  698 + /* if not enable exit now */
  699 + if (!en)
  700 + return;
  701 +
  702 + /* enable the mac transmit and receive paths now */
  703 + udelay(2);
  704 + cmdcfg &= ~CC_SR;
  705 + cmdcfg |= (CC_RE | CC_TE);
  706 +
  707 + /* assert rx_ena and tx_ena when out of reset to enable the mac */
  708 + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
  709 +
  710 + return;
  711 +}
  712 +
  713 +int gmac_enable(void)
  714 +{
  715 + gmac_enable_local(1);
  716 +
  717 + /* clear interrupts */
  718 + writel(I_INTMASK, GMAC0_INT_STATUS_ADDR);
  719 + return 0;
  720 +}
  721 +
  722 +int gmac_disable(void)
  723 +{
  724 + gmac_enable_local(0);
  725 + return 0;
  726 +}
  727 +
  728 +int gmac_set_speed(int speed, int duplex)
  729 +{
  730 + uint32_t cmdcfg;
  731 + uint32_t hd_ena;
  732 + uint32_t speed_cfg;
  733 +
  734 + hd_ena = duplex ? 0 : CC_HD;
  735 + if (speed == 1000) {
  736 + speed_cfg = 2;
  737 + } else if (speed == 100) {
  738 + speed_cfg = 1;
  739 + } else if (speed == 10) {
  740 + speed_cfg = 0;
  741 + } else {
  742 + error("%s: Invalid GMAC speed(%d)!\n", __func__, speed);
  743 + return -1;
  744 + }
  745 +
  746 + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
  747 + cmdcfg &= ~(CC_ES_MASK | CC_HD);
  748 + cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena);
  749 +
  750 + printf("Change GMAC speed to %dMB\n", speed);
  751 + debug("GMAC speed cfg 0x%x\n", cmdcfg);
  752 + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
  753 +
  754 + return 0;
  755 +}
  756 +
  757 +int gmac_set_mac_addr(unsigned char *mac)
  758 +{
  759 + /* set our local address */
  760 + debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
  761 + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  762 + writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR);
  763 + writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR);
  764 +
  765 + return 0;
  766 +}
  767 +
  768 +int gmac_mac_init(struct eth_device *dev)
  769 +{
  770 + struct eth_info *eth = (struct eth_info *)(dev->priv);
  771 + struct eth_dma *dma = &(eth->dma);
  772 +
  773 + uint32_t tmp;
  774 + uint32_t cmdcfg;
  775 + int chipid;
  776 +
  777 + debug("%s enter\n", __func__);
  778 +
  779 + /* Always use GMAC0 */
  780 + printf("Using GMAC%d\n", 0);
  781 +
  782 + /* Reset AMAC0 core */
  783 + writel(0, AMAC0_IDM_RESET_ADDR);
  784 + tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);
  785 + /* Set clock */
  786 + tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT);
  787 + tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT);
  788 + /* Set Tx clock */
  789 + tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT);
  790 + writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR);
  791 +
  792 + /* reset gmac */
  793 + /*
  794 + * As AMAC is just reset, NO need?
  795 + * set eth_data into loopback mode to ensure no rx traffic
  796 + * gmac_loopback(eth_data, TRUE);
  797 + * ET_TRACE(("%s gmac loopback\n", __func__));
  798 + * udelay(1);
  799 + */
  800 +
  801 + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
  802 + cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML |
  803 + CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI |
  804 + CC_PAD_EN | CC_PF);
  805 + cmdcfg |= (CC_PROM | CC_NLC | CC_CFE);
  806 + /* put mac in reset */
  807 + gmac_init_reset();
  808 + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
  809 + gmac_clear_reset();
  810 +
  811 + /* enable clear MIB on read */
  812 + reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR);
  813 + /* PHY: set smi_master to drive mdc_clk */
  814 + reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE);
  815 +
  816 + /* clear persistent sw intstatus */
  817 + writel(0, GMAC0_INT_STATUS_ADDR);
  818 +
  819 + if (dma_init(dma) < 0) {
  820 + error("%s: GMAC dma_init failed\n", __func__);
  821 + goto err_exit;
  822 + }
  823 +
  824 + chipid = CHIPID;
  825 + printf("%s: Chip ID: 0x%x\n", __func__, chipid);
  826 +
  827 + /* set switch bypass mode */
  828 + tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);
  829 + tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT);
  830 +
  831 + /* Switch mode */
  832 + /* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */
  833 +
  834 + writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR);
  835 +
  836 + tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);
  837 + tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT);
  838 + writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR);
  839 +
  840 + /* Set MDIO to internal GPHY */
  841 + tmp = readl(GMAC_MII_CTRL_ADDR);
  842 + /* Select internal MDC/MDIO bus*/
  843 + tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT);
  844 + /* select MDC/MDIO connecting to on-chip internal PHYs */
  845 + tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT);
  846 + /*
  847 + * give bit[6:0](MDCDIV) with required divisor to set
  848 + * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ
  849 + */
  850 + tmp |= 0x1A;
  851 +
  852 + writel(tmp, GMAC_MII_CTRL_ADDR);
  853 +
  854 + if (gmac_mii_busywait(1000)) {
  855 + error("%s: Configure MDIO: MII/MDIO busy\n", __func__);
  856 + goto err_exit;
  857 + }
  858 +
  859 + /* Configure GMAC0 */
  860 + /* enable one rx interrupt per received frame */
  861 + writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR);
  862 +
  863 + /* read command config reg */
  864 + cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
  865 + /* enable 802.3x tx flow control (honor received PAUSE frames) */
  866 + cmdcfg &= ~CC_RPI;
  867 + /* enable promiscuous mode */
  868 + cmdcfg |= CC_PROM;
  869 + /* Disable loopback mode */
  870 + cmdcfg &= ~CC_ML;
  871 + /* set the speed */
  872 + cmdcfg &= ~(CC_ES_MASK | CC_HD);
  873 + /* Set to 1Gbps and full duplex by default */
  874 + cmdcfg |= (2 << CC_ES_SHIFT);
  875 +
  876 + /* put mac in reset */
  877 + gmac_init_reset();
  878 + /* write register */
  879 + writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
  880 + /* bring mac out of reset */
  881 + gmac_clear_reset();
  882 +
  883 + /* set max frame lengths; account for possible vlan tag */
  884 + writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR);
  885 +
  886 + return 0;
  887 +
  888 +err_exit:
  889 + dma_deinit(dma);
  890 + return -1;
  891 +}
  892 +
  893 +int gmac_add(struct eth_device *dev)
  894 +{
  895 + struct eth_info *eth = (struct eth_info *)(dev->priv);
  896 + struct eth_dma *dma = &(eth->dma);
  897 + void *tmp;
  898 +
  899 + /*
  900 + * Desc has to be 16-byte aligned ?
  901 + * If it is 8-byte aligned by malloc, fail Tx
  902 + */
  903 + tmp = malloc(sizeof(dma64dd_t) * TX_BUF_NUM + 8);
  904 + if (tmp == NULL) {
  905 + printf("%s: Failed to allocate TX desc Buffer\n", __func__);
  906 + return -1;
  907 + }
  908 +
  909 + dma->tx_desc = (void *)tmp;
  910 + dma->tx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
  911 + debug("TX Descriptor Buffer: %p; length: 0x%x\n",
  912 + dma->tx_desc_aligned, sizeof(dma64dd_t) * TX_BUF_NUM);
  913 +
  914 + tmp = malloc(TX_BUF_SIZE * TX_BUF_NUM);
  915 + if (tmp == NULL) {
  916 + printf("%s: Failed to allocate TX Data Buffer\n", __func__);
  917 + free(dma->tx_desc);
  918 + return -1;
  919 + }
  920 + dma->tx_buf = (uint8_t *)tmp;
  921 + debug("TX Data Buffer: %p; length: 0x%x\n",
  922 + dma->tx_buf, TX_BUF_SIZE * TX_BUF_NUM);
  923 +
  924 + /* Desc has to be 16-byte aligned ? */
  925 + tmp = malloc(sizeof(dma64dd_t) * RX_BUF_NUM + 8);
  926 + if (tmp == NULL) {
  927 + printf("%s: Failed to allocate RX Descriptor\n", __func__);
  928 + free(dma->tx_desc);
  929 + free(dma->tx_buf);
  930 + return -1;
  931 + }
  932 + dma->rx_desc = tmp;
  933 + dma->rx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
  934 + debug("RX Descriptor Buffer: %p, length: 0x%x\n",
  935 + dma->rx_desc_aligned, sizeof(dma64dd_t) * RX_BUF_NUM);
  936 +
  937 + tmp = malloc(RX_BUF_SIZE * RX_BUF_NUM);
  938 + if (tmp == NULL) {
  939 + printf("%s: Failed to allocate RX Data Buffer\n", __func__);
  940 + free(dma->tx_desc);
  941 + free(dma->tx_buf);
  942 + free(dma->rx_desc);
  943 + return -1;
  944 + }
  945 + dma->rx_buf = tmp;
  946 + debug("RX Data Buffer: %p; length: 0x%x\n",
  947 + dma->rx_buf, RX_BUF_SIZE * RX_BUF_NUM);
  948 +
  949 + g_dmactrlflags = 0;
  950 +
  951 + eth->phy_interface = PHY_INTERFACE_MODE_GMII;
  952 +
  953 + dma->tx_packet = gmac_tx_packet;
  954 + dma->check_tx_done = gmac_check_tx_done;
  955 +
  956 + dma->check_rx_done = gmac_check_rx_done;
  957 +
  958 + dma->enable_dma = gmac_enable_dma;
  959 + dma->disable_dma = gmac_disable_dma;
  960 +
  961 + eth->miiphy_read = gmac_miiphy_read;
  962 + eth->miiphy_write = gmac_miiphy_write;
  963 +
  964 + eth->mac_init = gmac_mac_init;
  965 + eth->disable_mac = gmac_disable;
  966 + eth->enable_mac = gmac_enable;
  967 + eth->set_mac_addr = gmac_set_mac_addr;
  968 + eth->set_mac_speed = gmac_set_speed;
  969 +
  970 + return 0;
  971 +}
drivers/net/bcm-sf2-eth-gmac.h
Diff comments   View file @ 799e125
  1 +/*
  2 + * Copyright 2014 Broadcom Corporation.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _BCM_SF2_ETH_GMAC_H_
  8 +#define _BCM_SF2_ETH_GMAC_H_
  9 +
  10 +#define BCM_SF2_ETH_MAC_NAME "gmac"
  11 +
  12 +#ifndef ETHHW_PORT_INT
  13 +#define ETHHW_PORT_INT 8
  14 +#endif
  15 +
  16 +#define GMAC0_REG_BASE 0x18042000
  17 +#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE
  18 +#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
  19 +#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
  20 +#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
  21 +
  22 +
  23 +#define GMAC_DMA_PTR_OFFSET 0x04
  24 +#define GMAC_DMA_ADDR_LOW_OFFSET 0x08
  25 +#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
  26 +#define GMAC_DMA_STATUS0_OFFSET 0x10
  27 +#define GMAC_DMA_STATUS1_OFFSET 0x14
  28 +
  29 +#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
  30 +#define GMAC0_DMA_TX_PTR_ADDR \
  31 + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
  32 +#define GMAC0_DMA_TX_ADDR_LOW_ADDR \
  33 + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
  34 +#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \
  35 + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
  36 +#define GMAC0_DMA_TX_STATUS0_ADDR \
  37 + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
  38 +#define GMAC0_DMA_TX_STATUS1_ADDR \
  39 + (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
  40 +
  41 +#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220)
  42 +#define GMAC0_DMA_RX_PTR_ADDR \
  43 + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
  44 +#define GMAC0_DMA_RX_ADDR_LOW_ADDR \
  45 + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
  46 +#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \
  47 + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
  48 +#define GMAC0_DMA_RX_STATUS0_ADDR \
  49 + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
  50 +#define GMAC0_DMA_RX_STATUS1_ADDR \
  51 + (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
  52 +
  53 +#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808)
  54 +#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c)
  55 +#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810)
  56 +#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814)
  57 +
  58 +#define GMAC0_IRL_FRAMECOUNT_SHIFT 24
  59 +
  60 +/* transmit channel control */
  61 +/* transmit enable */
  62 +#define D64_XC_XE 0x00000001
  63 +/* transmit suspend request */
  64 +#define D64_XC_SE 0x00000002
  65 +/* parity check disable */
  66 +#define D64_XC_PD 0x00000800
  67 +/* BurstLen bits */
  68 +#define D64_XC_BL_MASK 0x001C0000
  69 +#define D64_XC_BL_SHIFT 18
  70 +
  71 +/* transmit descriptor table pointer */
  72 +/* last valid descriptor */
  73 +#define D64_XP_LD_MASK 0x00001fff
  74 +
  75 +/* transmit channel status */
  76 +/* transmit state */
  77 +#define D64_XS0_XS_MASK 0xf0000000
  78 +#define D64_XS0_XS_SHIFT 28
  79 +#define D64_XS0_XS_DISABLED 0x00000000
  80 +#define D64_XS0_XS_ACTIVE 0x10000000
  81 +#define D64_XS0_XS_IDLE 0x20000000
  82 +#define D64_XS0_XS_STOPPED 0x30000000
  83 +#define D64_XS0_XS_SUSP 0x40000000
  84 +
  85 +/* receive channel control */
  86 +/* receive enable */
  87 +#define D64_RC_RE 0x00000001
  88 +/* address extension bits */
  89 +#define D64_RC_AE 0x00030000
  90 +/* overflow continue */
  91 +#define D64_RC_OC 0x00000400
  92 +/* parity check disable */
  93 +#define D64_RC_PD 0x00000800
  94 +/* receive frame offset */
  95 +#define D64_RC_RO_MASK 0x000000fe
  96 +#define D64_RC_RO_SHIFT 1
  97 +/* BurstLen bits */
  98 +#define D64_RC_BL_MASK 0x001C0000
  99 +#define D64_RC_BL_SHIFT 18
  100 +
  101 +/* flags for dma controller */
  102 +/* partity enable */
  103 +#define DMA_CTRL_PEN (1 << 0)
  104 +/* rx overflow continue */
  105 +#define DMA_CTRL_ROC (1 << 1)
  106 +
  107 +/* receive descriptor table pointer */
  108 +/* last valid descriptor */
  109 +#define D64_RP_LD_MASK 0x00001fff
  110 +
  111 +/* receive channel status */
  112 +/* current descriptor pointer */
  113 +#define D64_RS0_CD_MASK 0x00001fff
  114 +/* receive state */
  115 +#define D64_RS0_RS_MASK 0xf0000000
  116 +#define D64_RS0_RS_SHIFT 28
  117 +#define D64_RS0_RS_DISABLED 0x00000000
  118 +#define D64_RS0_RS_ACTIVE 0x10000000
  119 +#define D64_RS0_RS_IDLE 0x20000000
  120 +#define D64_RS0_RS_STOPPED 0x30000000
  121 +#define D64_RS0_RS_SUSP 0x40000000
  122 +
  123 +/* descriptor control flags 1 */
  124 +/* core specific flags */
  125 +#define D64_CTRL_COREFLAGS 0x0ff00000
  126 +/* end of descriptor table */
  127 +#define D64_CTRL1_EOT ((uint32_t)1 << 28)
  128 +/* interrupt on completion */
  129 +#define D64_CTRL1_IOC ((uint32_t)1 << 29)
  130 +/* end of frame */
  131 +#define D64_CTRL1_EOF ((uint32_t)1 << 30)
  132 +/* start of frame */
  133 +#define D64_CTRL1_SOF ((uint32_t)1 << 31)
  134 +
  135 +/* descriptor control flags 2 */
  136 +/* buffer byte count. real data len must <= 16KB */
  137 +#define D64_CTRL2_BC_MASK 0x00007fff
  138 +/* address extension bits */
  139 +#define D64_CTRL2_AE 0x00030000
  140 +#define D64_CTRL2_AE_SHIFT 16
  141 +/* parity bit */
  142 +#define D64_CTRL2_PARITY 0x00040000
  143 +/* control flags in the range [27:20] are core-specific and not defined here */
  144 +#define D64_CTRL_CORE_MASK 0x0ff00000
  145 +
  146 +#define DC_MROR 0x00000010
  147 +#define PC_MTE 0x00800000
  148 +
  149 +/* command config */
  150 +#define CC_TE 0x00000001
  151 +#define CC_RE 0x00000002
  152 +#define CC_ES_MASK 0x0000000c
  153 +#define CC_ES_SHIFT 2
  154 +#define CC_PROM 0x00000010
  155 +#define CC_PAD_EN 0x00000020
  156 +#define CC_CF 0x00000040
  157 +#define CC_PF 0x00000080
  158 +#define CC_RPI 0x00000100
  159 +#define CC_TAI 0x00000200
  160 +#define CC_HD 0x00000400
  161 +#define CC_HD_SHIFT 10
  162 +#define CC_SR 0x00002000
  163 +#define CC_ML 0x00008000
  164 +#define CC_AE 0x00400000
  165 +#define CC_CFE 0x00800000
  166 +#define CC_NLC 0x01000000
  167 +#define CC_RL 0x02000000
  168 +#define CC_RED 0x04000000
  169 +#define CC_PE 0x08000000
  170 +#define CC_TPI 0x10000000
  171 +#define CC_AT 0x20000000
  172 +
  173 +#define I_PDEE 0x00000400
  174 +#define I_PDE 0x00000800
  175 +#define I_DE 0x00001000
  176 +#define I_RDU 0x00002000
  177 +#define I_RFO 0x00004000
  178 +#define I_XFU 0x00008000
  179 +#define I_RI 0x00010000
  180 +#define I_XI0 0x01000000
  181 +#define I_XI1 0x02000000
  182 +#define I_XI2 0x04000000
  183 +#define I_XI3 0x08000000
  184 +#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)
  185 +#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)
  186 +
  187 +#define I_INTMASK 0x0f01fcff
  188 +
  189 +#define CHIP_DRU_BASE 0x0301d000
  190 +#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc)
  191 +#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194)
  192 +
  193 +#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0
  194 +#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13
  195 +
  196 +#define AMAC0_IDM_RESET_ADDR 0x18110800
  197 +#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408
  198 +#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6
  199 +#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5
  200 +#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3
  201 +
  202 +#define CHIPA_CHIP_ID_ADDR 0x18000000
  203 +#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
  204 +#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
  205 +#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
  206 +
  207 +#define GMAC_MII_CTRL_ADDR 0x18002000
  208 +#define GMAC_MII_CTRL_BYP_SHIFT 10
  209 +#define GMAC_MII_CTRL_EXT_SHIFT 9
  210 +#define GMAC_MII_DATA_ADDR 0x18002004
  211 +#define GMAC_MII_DATA_READ_CMD 0x60020000
  212 +#define GMAC_MII_DATA_WRITE_CMD 0x50020000
  213 +#define GMAC_MII_BUSY_SHIFT 8
  214 +#define GMAC_MII_PHY_ADDR_SHIFT 23
  215 +#define GMAC_MII_PHY_REG_SHIFT 18
  216 +
  217 +#define GMAC_RESET_DELAY 2
  218 +#define HWRXOFF 30
  219 +#define MAXNAMEL 8
  220 +#define NUMTXQ 4
  221 +
  222 +int gmac_add(struct eth_device *dev);
  223 +
  224 +#endif /* _BCM_SF2_ETH_GMAC_H_ */
drivers/net/bcm-sf2-eth.c
Diff comments   View file @ 799e125
  1 +/*
  2 + * Copyright 2014 Broadcom Corporation.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <net.h>
  10 +#include <config.h>
  11 +
  12 +#include <phy.h>
  13 +#include <miiphy.h>
  14 +
  15 +#include <asm/io.h>
  16 +
  17 +#include <netdev.h>
  18 +#include "bcm-sf2-eth.h"
  19 +
  20 +#if defined(CONFIG_BCM_SF2_ETH_GMAC)
  21 +#include "bcm-sf2-eth-gmac.h"
  22 +#else
  23 +#error "bcm_sf2_eth: NEED to define a MAC!"
  24 +#endif
  25 +
  26 +#define BCM_NET_MODULE_DESCRIPTION "Broadcom Starfighter2 Ethernet driver"
  27 +#define BCM_NET_MODULE_VERSION "0.1"
  28 +#define BCM_SF2_ETH_DEV_NAME "bcm_sf2"
  29 +
  30 +static const char banner[] =
  31 + BCM_NET_MODULE_DESCRIPTION " " BCM_NET_MODULE_VERSION "\n";
  32 +
  33 +static int bcm_sf2_eth_init(struct eth_device *dev)
  34 +{
  35 + struct eth_info *eth = (struct eth_info *)(dev->priv);
  36 + struct eth_dma *dma = &(eth->dma);
  37 + struct phy_device *phydev;
  38 + int rc = 0;
  39 + int i;
  40 +
  41 + rc = eth->mac_init(dev);
  42 + if (rc) {
  43 + error("%s: Couldn't cofigure MAC!\n", __func__);
  44 + return rc;
  45 + }
  46 +
  47 + /* disable DMA */
  48 + dma->disable_dma(dma, MAC_DMA_RX);
  49 + dma->disable_dma(dma, MAC_DMA_TX);
  50 +
  51 + eth->port_num = 0;
  52 + debug("Connecting PHY 0...\n");
  53 + phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
  54 + 0, dev, eth->phy_interface);
  55 + if (phydev != NULL) {
  56 + eth->port[0] = phydev;
  57 + eth->port_num += 1;
  58 + } else {
  59 + debug("No PHY found for port 0\n");
  60 + }
  61 +
  62 + for (i = 0; i < eth->port_num; i++)
  63 + phy_config(eth->port[i]);
  64 +
  65 + return rc;
  66 +}
  67 +
  68 +/*
  69 + * u-boot net functions
  70 + */
  71 +
  72 +static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length)
  73 +{
  74 + struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);
  75 + uint8_t *buf = (uint8_t *)packet;
  76 + int rc = 0;
  77 + int i = 0;
  78 +
  79 + debug("%s enter\n", __func__);
  80 +
  81 + /* load buf and start transmit */
  82 + rc = dma->tx_packet(dma, buf, length);
  83 + if (rc) {
  84 + debug("ERROR - Tx failed\n");
  85 + return rc;
  86 + }
  87 +
  88 + while (!(dma->check_tx_done(dma))) {
  89 + udelay(100);
  90 + debug(".");
  91 + i++;
  92 + if (i > 20) {
  93 + error("%s: Tx timeout: retried 20 times\n", __func__);
  94 + rc = -1;
  95 + break;
  96 + }
  97 + }
  98 +
  99 + debug("%s exit rc(0x%x)\n", __func__, rc);
  100 + return rc;
  101 +}
  102 +
  103 +static int bcm_sf2_eth_receive(struct eth_device *dev)
  104 +{
  105 + struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);
  106 + uint8_t *buf = (uint8_t *)NetRxPackets[0];
  107 + int rcvlen;
  108 + int rc = 0;
  109 + int i = 0;
  110 +
  111 + while (1) {
  112 + /* Poll Rx queue to get a packet */
  113 + rcvlen = dma->check_rx_done(dma, buf);
  114 + if (rcvlen < 0) {
  115 + /* No packet received */
  116 + rc = -1;
  117 + debug("\nNO More Rx\n");
  118 + break;
  119 + } else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) {
  120 + error("%s: Wrong Ethernet packet size (%d B), skip!\n",
  121 + __func__, rcvlen);
  122 + break;
  123 + } else {
  124 + debug("recieved\n");
  125 +
  126 + /* Forward received packet to uboot network handler */
  127 + NetReceive(buf, rcvlen);
  128 +
  129 + if (++i >= PKTBUFSRX)
  130 + i = 0;
  131 + buf = NetRxPackets[i];
  132 + }
  133 + }
  134 +
  135 + return rc;
  136 +}
  137 +
  138 +static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev)
  139 +{
  140 + struct eth_info *eth = (struct eth_info *)(dev->priv);
  141 +
  142 + printf(" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
  143 + dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2],
  144 + dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]);
  145 +
  146 + return eth->set_mac_addr(dev->enetaddr);
  147 +}
  148 +
  149 +static int bcm_sf2_eth_open(struct eth_device *dev, bd_t *bt)
  150 +{
  151 + struct eth_info *eth = (struct eth_info *)(dev->priv);
  152 + struct eth_dma *dma = &(eth->dma);
  153 + int i;
  154 +
  155 + debug("Enabling BCM SF2 Ethernet.\n");
  156 +
  157 + /* Set MAC address from env */
  158 + if (bcm_sf2_eth_write_hwaddr(dev) != 0) {
  159 + error("%s: MAC set error when opening !\n", __func__);
  160 + return -1;
  161 + }
  162 +
  163 + eth->enable_mac();
  164 +
  165 + /* enable tx and rx DMA */
  166 + dma->enable_dma(dma, MAC_DMA_RX);
  167 + dma->enable_dma(dma, MAC_DMA_TX);
  168 +
  169 + /*
  170 + * Need to start PHY here because link speed can change
  171 + * before each ethernet operation
  172 + */
  173 + for (i = 0; i < eth->port_num; i++) {
  174 + if (phy_startup(eth->port[i])) {
  175 + error("%s: PHY %d startup failed!\n", __func__, i);
  176 + if (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) {
  177 + error("%s: No default port %d!\n", __func__, i);
  178 + return -1;
  179 + }
  180 + }
  181 + }
  182 +
  183 + /* Set MAC speed using default port */
  184 + i = CONFIG_BCM_SF2_ETH_DEFAULT_PORT;
  185 + debug("PHY %d: speed:%d, duplex:%d, link:%d\n", i,
  186 + eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link);
  187 + eth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex);
  188 +
  189 + debug("Enable Ethernet Done.\n");
  190 +
  191 + return 0;
  192 +}
  193 +
  194 +static void bcm_sf2_eth_close(struct eth_device *dev)
  195 +{
  196 + struct eth_info *eth = (struct eth_info *)(dev->priv);
  197 + struct eth_dma *dma = &(eth->dma);
  198 +
  199 + /* disable DMA */
  200 + dma->disable_dma(dma, MAC_DMA_RX);
  201 + dma->disable_dma(dma, MAC_DMA_TX);
  202 +
  203 + eth->disable_mac();
  204 +}
  205 +
  206 +int bcm_sf2_eth_register(bd_t *bis, u8 dev_num)
  207 +{
  208 + struct eth_device *dev;
  209 + struct eth_info *eth;
  210 + int rc;
  211 +
  212 + dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  213 + if (dev == NULL) {
  214 + error("%s: Not enough memory!\n", __func__);
  215 + return -1;
  216 + }
  217 +
  218 + eth = (struct eth_info *)malloc(sizeof(struct eth_info));
  219 + if (eth == NULL) {
  220 + error("%s: Not enough memory!\n", __func__);
  221 + return -1;
  222 + }
  223 +
  224 + printf(banner);
  225 +
  226 + memset(dev, 0, sizeof(*dev));
  227 + sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME,
  228 + BCM_SF2_ETH_MAC_NAME, dev_num);
  229 +
  230 + dev->priv = (void *)eth;
  231 + dev->iobase = 0;
  232 +
  233 + dev->init = bcm_sf2_eth_open;
  234 + dev->halt = bcm_sf2_eth_close;
  235 + dev->send = bcm_sf2_eth_send;
  236 + dev->recv = bcm_sf2_eth_receive;
  237 + dev->write_hwaddr = bcm_sf2_eth_write_hwaddr;
  238 +
  239 +#ifdef CONFIG_BCM_SF2_ETH_GMAC
  240 + if (gmac_add(dev)) {
  241 + free(eth);
  242 + free(dev);
  243 + error("%s: Adding GMAC failed!\n", __func__);
  244 + return -1;
  245 + }
  246 +#else
  247 +#error "bcm_sf2_eth: NEED to register a MAC!"
  248 +#endif
  249 +
  250 + eth_register(dev);
  251 +
  252 +#ifdef CONFIG_CMD_MII
  253 + miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write);
  254 +#endif
  255 +
  256 + /* Initialization */
  257 + debug("Ethernet initialization ...");
  258 +
  259 + rc = bcm_sf2_eth_init(dev);
  260 + if (rc != 0) {
  261 + error("%s: configuration failed!\n", __func__);
  262 + return -1;
  263 + }
  264 +
  265 + printf("Basic ethernet functionality initialized\n");
  266 +
  267 + return 0;
  268 +}
drivers/net/bcm-sf2-eth.h
Diff comments   View file @ 799e125
  1 +/*
  2 + * Copyright 2014 Broadcom Corporation.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _BCM_SF2_ETH_H_
  8 +#define _BCM_SF2_ETH_H_
  9 +
  10 +#include <phy.h>
  11 +
  12 +#define RX_BUF_SIZE 2048
  13 +/* RX_BUF_NUM must be power of 2 */
  14 +#define RX_BUF_NUM 32
  15 +
  16 +#define TX_BUF_SIZE 2048
  17 +/* TX_BUF_NUM must be power of 2 */
  18 +#define TX_BUF_NUM 2
  19 +
  20 +/* Support 2 Ethernet ports now */
  21 +#define BCM_ETH_MAX_PORT_NUM 2
  22 +
  23 +#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT 0
  24 +
  25 +enum {
  26 + MAC_DMA_TX = 1,
  27 + MAC_DMA_RX = 2
  28 +};
  29 +
  30 +struct eth_dma {
  31 + void *tx_desc_aligned;
  32 + void *rx_desc_aligned;
  33 + void *tx_desc;
  34 + void *rx_desc;
  35 +
  36 + uint8_t *tx_buf;
  37 + uint8_t *rx_buf;
  38 +
  39 + int cur_tx_index;
  40 + int cur_rx_index;
  41 +
  42 + int (*tx_packet)(struct eth_dma *dma, void *packet, int length);
  43 + bool (*check_tx_done)(struct eth_dma *dma);
  44 +
  45 + int (*check_rx_done)(struct eth_dma *dma, uint8_t *buf);
  46 +
  47 + int (*enable_dma)(struct eth_dma *dma, int dir);
  48 + int (*disable_dma)(struct eth_dma *dma, int dir);
  49 +};
  50 +
  51 +struct eth_info {
  52 + struct eth_dma dma;
  53 + phy_interface_t phy_interface;
  54 + struct phy_device *port[BCM_ETH_MAX_PORT_NUM];
  55 + int port_num;
  56 +
  57 + int (*miiphy_read)(const char *devname, unsigned char phyaddr,
  58 + unsigned char reg, unsigned short *value);
  59 + int (*miiphy_write)(const char *devname, unsigned char phyaddr,
  60 + unsigned char reg, unsigned short value);
  61 +
  62 + int (*mac_init)(struct eth_device *dev);
  63 + int (*enable_mac)(void);
  64 + int (*disable_mac)(void);
  65 + int (*set_mac_addr)(unsigned char *mac);
  66 + int (*set_mac_speed)(int speed, int duplex);
  67 +
  68 +};
  69 +
  70 +#endif /* _BCM_SF2_ETH_H_ */
... ... @@ -31,6 +31,7 @@
31 31 int at91emac_register(bd_t *bis, unsigned long iobase);
32 32 int au1x00_enet_initialize(bd_t*);
33 33 int ax88180_initialize(bd_t *bis);
  34 +int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
34 35 int bfin_EMAC_initialize(bd_t *bis);
35 36 int calxedaxgmac_initialize(u32 id, ulong base_addr);
36 37 int cs8900_initialize(u8 dev_num, int base_addr);