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Commit 79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7

Authored by Bin Meng
1 parent ec2af6f82d
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

dm: pch: Add get_io_base op 

On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

Showing 2 changed files with 29 additions and 0 deletions Inline Diff

drivers/pch/pch-uclass.c
Diff comments   View file @ 79d4eb6
1 /* 1 /*
2 * Copyright (c) 2015 Google, Inc 2 * Copyright (c) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org> 3 * Written by Simon Glass <sjg@chromium.org>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <dm.h> 9 #include <dm.h>
10 #include <pch.h> 10 #include <pch.h>
11 #include <dm/root.h> 11 #include <dm/root.h>
12 12
13 DECLARE_GLOBAL_DATA_PTR; 13 DECLARE_GLOBAL_DATA_PTR;
14 14
15 int pch_get_spi_base(struct udevice *dev, ulong *sbasep) 15 int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
16 { 16 {
17 struct pch_ops *ops = pch_get_ops(dev); 17 struct pch_ops *ops = pch_get_ops(dev);
18 18
19 *sbasep = 0; 19 *sbasep = 0;
20 if (!ops->get_spi_base) 20 if (!ops->get_spi_base)
21 return -ENOSYS; 21 return -ENOSYS;
22 22
23 return ops->get_spi_base(dev, sbasep); 23 return ops->get_spi_base(dev, sbasep);
24 } 24 }
25 25
26 int pch_set_spi_protect(struct udevice *dev, bool protect) 26 int pch_set_spi_protect(struct udevice *dev, bool protect)
27 { 27 {
28 struct pch_ops *ops = pch_get_ops(dev); 28 struct pch_ops *ops = pch_get_ops(dev);
29 29
30 if (!ops->set_spi_protect) 30 if (!ops->set_spi_protect)
31 return -ENOSYS; 31 return -ENOSYS;
32 32
33 return ops->set_spi_protect(dev, protect); 33 return ops->set_spi_protect(dev, protect);
34 } 34 }
35 35
36 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep) 36 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
37 { 37 {
38 struct pch_ops *ops = pch_get_ops(dev); 38 struct pch_ops *ops = pch_get_ops(dev);
39 39
40 *gbasep = 0; 40 *gbasep = 0;
41 if (!ops->get_gpio_base) 41 if (!ops->get_gpio_base)
42 return -ENOSYS; 42 return -ENOSYS;
43 43
44 return ops->get_gpio_base(dev, gbasep); 44 return ops->get_gpio_base(dev, gbasep);
45 } 45 }
46 46
47 int pch_get_io_base(struct udevice *dev, u32 *iobasep)
48 {
49 struct pch_ops *ops = pch_get_ops(dev);
50
51 *iobasep = 0;
52 if (!ops->get_io_base)
53 return -ENOSYS;
54
55 return ops->get_io_base(dev, iobasep);
56 }
57
47 static int pch_uclass_post_bind(struct udevice *bus) 58 static int pch_uclass_post_bind(struct udevice *bus)
48 { 59 {
49 /* 60 /*
50 * Scan the device tree for devices 61 * Scan the device tree for devices
51 * 62 *
52 * Before relocation, only bind devices marked for pre-relocation 63 * Before relocation, only bind devices marked for pre-relocation
53 * use. 64 * use.
54 */ 65 */
55 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, 66 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
56 gd->flags & GD_FLG_RELOC ? false : true); 67 gd->flags & GD_FLG_RELOC ? false : true);
57 } 68 }
58 69
59 UCLASS_DRIVER(pch) = { 70 UCLASS_DRIVER(pch) = {
60 .id = UCLASS_PCH, 71 .id = UCLASS_PCH,
61 .name = "pch", 72 .name = "pch",
62 .post_bind = pch_uclass_post_bind, 73 .post_bind = pch_uclass_post_bind,
63 }; 74 };
64 75
1 /* 1 /*
2 * Copyright (c) 2015 Google, Inc 2 * Copyright (c) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org> 3 * Written by Simon Glass <sjg@chromium.org>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #ifndef __pch_h 8 #ifndef __pch_h
9 #define __pch_h 9 #define __pch_h
10 10
11 #define PCH_RCBA 0xf0 11 #define PCH_RCBA 0xf0
12 12
13 #define BIOS_CTRL_BIOSWE BIT(0) 13 #define BIOS_CTRL_BIOSWE BIT(0)
14 14
15 /* Operations for the Platform Controller Hub */ 15 /* Operations for the Platform Controller Hub */
16 struct pch_ops { 16 struct pch_ops {
17 /** 17 /**
18 * get_spi_base() - get the address of SPI base 18 * get_spi_base() - get the address of SPI base
19 * 19 *
20 * @dev: PCH device to check 20 * @dev: PCH device to check
21 * @sbasep: Returns address of SPI base if available, else 0 21 * @sbasep: Returns address of SPI base if available, else 0
22 * @return 0 if OK, -ve on error (e.g. there is no SPI base) 22 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
23 */ 23 */
24 int (*get_spi_base)(struct udevice *dev, ulong *sbasep); 24 int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
25 25
26 /** 26 /**
27 * set_spi_protect() - set whether SPI flash is protected or not 27 * set_spi_protect() - set whether SPI flash is protected or not
28 * 28 *
29 * @dev: PCH device to adjust 29 * @dev: PCH device to adjust
30 * @protect: true to protect, false to unprotect 30 * @protect: true to protect, false to unprotect
31 * 31 *
32 * @return 0 on success, -ENOSYS if not implemented 32 * @return 0 on success, -ENOSYS if not implemented
33 */ 33 */
34 int (*set_spi_protect)(struct udevice *dev, bool protect); 34 int (*set_spi_protect)(struct udevice *dev, bool protect);
35 35
36 /** 36 /**
37 * get_gpio_base() - get the address of GPIO base 37 * get_gpio_base() - get the address of GPIO base
38 * 38 *
39 * @dev: PCH device to check 39 * @dev: PCH device to check
40 * @gbasep: Returns address of GPIO base if available, else 0 40 * @gbasep: Returns address of GPIO base if available, else 0
41 * @return 0 if OK, -ve on error (e.g. there is no GPIO base) 41 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
42 */ 42 */
43 int (*get_gpio_base)(struct udevice *dev, u32 *gbasep); 43 int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
44
45 /**
46 * get_io_base() - get the address of IO base
47 *
48 * @dev: PCH device to check
49 * @iobasep: Returns address of IO base if available, else 0
50 * @return 0 if OK, -ve on error (e.g. there is no IO base)
51 */
52 int (*get_io_base)(struct udevice *dev, u32 *iobasep);
44 }; 53 };
45 54
46 #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops) 55 #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
47 56
48 /** 57 /**
49 * pch_get_spi_base() - get the address of SPI base 58 * pch_get_spi_base() - get the address of SPI base
50 * 59 *
51 * @dev: PCH device to check 60 * @dev: PCH device to check
52 * @sbasep: Returns address of SPI base if available, else 0 61 * @sbasep: Returns address of SPI base if available, else 0
53 * @return 0 if OK, -ve on error (e.g. there is no SPI base) 62 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
54 */ 63 */
55 int pch_get_spi_base(struct udevice *dev, ulong *sbasep); 64 int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
56 65
57 /** 66 /**
58 * set_spi_protect() - set whether SPI flash is protected or not 67 * set_spi_protect() - set whether SPI flash is protected or not
59 * 68 *
60 * @dev: PCH device to adjust 69 * @dev: PCH device to adjust
61 * @protect: true to protect, false to unprotect 70 * @protect: true to protect, false to unprotect
62 * 71 *
63 * @return 0 on success, -ENOSYS if not implemented 72 * @return 0 on success, -ENOSYS if not implemented
64 */ 73 */
65 int pch_set_spi_protect(struct udevice *dev, bool protect); 74 int pch_set_spi_protect(struct udevice *dev, bool protect);
66 75
67 /** 76 /**
68 * pch_get_gpio_base() - get the address of GPIO base 77 * pch_get_gpio_base() - get the address of GPIO base
69 * 78 *
70 * @dev: PCH device to check 79 * @dev: PCH device to check
71 * @gbasep: Returns address of GPIO base if available, else 0 80 * @gbasep: Returns address of GPIO base if available, else 0
72 * @return 0 if OK, -ve on error (e.g. there is no GPIO base) 81 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
73 */ 82 */
74 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep); 83 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
84
85 /**
86 * pch_get_io_base() - get the address of IO base
87 *
88 * @dev: PCH device to check
89 * @iobasep: Returns address of IO base if available, else 0
90 * @return 0 if OK, -ve on error (e.g. there is no IO base)
91 */
92 int pch_get_io_base(struct udevice *dev, u32 *iobasep);
75 93
76 #endif 94 #endif
77 95