dm: pch: Add get_io_base op

On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>

dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng
1 parent ec2af6f82d
Showing 2 changed files with 29 additions and 0 deletions Side-by-side Diff
drivers/pch/pch-uclass.c
include/pch.h
@@ -44,6 +44,17 @@
 	return ops->get_gpio_base(dev, gbasep);
 }
  
+int pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+	struct pch_ops *ops = pch_get_ops(dev);
+
+	*iobasep = 0;
+	if (!ops->get_io_base)
+		return -ENOSYS;
+
+	return ops->get_io_base(dev, iobasep);
+}
+
 static int pch_uclass_post_bind(struct udevice *bus)
 {
 	/*
@@ -41,6 +41,15 @@
 	 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
 	 */
 	int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
+
+	/**
+	 * get_io_base() - get the address of IO base
+	 *
+	 * @dev:	PCH device to check
+	 * @iobasep:	Returns address of IO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no IO base)
+	 */
+	int (*get_io_base)(struct udevice *dev, u32 *iobasep);
 };
  
 #define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
@@ -72,6 +81,15 @@
  * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
  */
 int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
+
+/**
+ * pch_get_io_base() - get the address of IO base
+ *
+ * @dev:	PCH device to check
+ * @iobasep:	Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+int pch_get_io_base(struct udevice *dev, u32 *iobasep);
  
 #endif
...	...	@@ -44,6 +44,17 @@
44	44	return ops->get_gpio_base(dev, gbasep);
45	45	}
46	46
	47	+int pch_get_io_base(struct udevice dev, u32 iobasep)
	48	+{
	49	+ struct pch_ops *ops = pch_get_ops(dev);
	50	+
	51	+ *iobasep = 0;
	52	+ if (!ops->get_io_base)
	53	+ return -ENOSYS;
	54	+
	55	+ return ops->get_io_base(dev, iobasep);
	56	+}
	57	+
47	58	static int pch_uclass_post_bind(struct udevice *bus)
48	59	{
49	60	/*
...	...	@@ -41,6 +41,15 @@
41	41	* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
42	42	*/
43	43	int (get_gpio_base)(struct udevice dev, u32 *gbasep);
	44	+
	45	+ /**
	46	+ * get_io_base() - get the address of IO base
	47	+ *
	48	+ * @dev: PCH device to check
	49	+ * @iobasep: Returns address of IO base if available, else 0
	50	+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
	51	+ */
	52	+ int (get_io_base)(struct udevice dev, u32 *iobasep);
44	53	};
45	54
46	55	#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
...	...	@@ -72,6 +81,15 @@
72	81	* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
73	82	*/
74	83	int pch_get_gpio_base(struct udevice dev, u32 gbasep);
	84	+
	85	+/**
	86	+ * pch_get_io_base() - get the address of IO base
	87	+ *
	88	+ * @dev: PCH device to check
	89	+ * @iobasep: Returns address of IO base if available, else 0
	90	+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
	91	+ */
	92	+int pch_get_io_base(struct udevice dev, u32 iobasep);
75	93
76	94	#endif