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Commit 7a2c1b13d70f38c38c4a4fe153265a861ebd5cd2

Authored by Simon Glass
Committed by Tom Rini
1 parent 93b25c0813
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: Remove openrd boards 

These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 11 changed files with 0 additions and 543 deletions Side-by-side Diff

arch/arm/mach-kirkwood/Kconfig
Diff comments   View file @ 7a2c1b1
... ... @@ -4,9 +4,6 @@
4 4 prompt "Marvell Kirkwood board select"
5 5 optional
6 6  
7   -config TARGET_OPENRD
8   - bool "Marvell OpenRD Board"
9   -
10 7 config TARGET_RD6281A
11 8 bool "RD6281A Board"
12 9  
... ... @@ -63,7 +60,6 @@
63 60 config SYS_SOC
64 61 default "kirkwood"
65 62  
66   -source "board/Marvell/openrd/Kconfig"
67 63 source "board/Marvell/rd6281a/Kconfig"
68 64 source "board/Marvell/dreamplug/Kconfig"
69 65 source "board/Marvell/guruplug/Kconfig"
board/Marvell/openrd/Kconfig
View file @ 7a2c1b1
1   -if TARGET_OPENRD
2   -
3   -config SYS_BOARD
4   - default "openrd"
5   -
6   -config SYS_VENDOR
7   - default "Marvell"
8   -
9   -config SYS_CONFIG_NAME
10   - default "openrd"
11   -
12   -endif
board/Marvell/openrd/MAINTAINERS
View file @ 7a2c1b1
1   -OPENRD BOARD
2   -M: Prafulla Wadaskar <prafulla@marvell.com>
3   -S: Maintained
4   -F: board/Marvell/openrd/
5   -F: include/configs/openrd.h
6   -F: configs/openrd_base_defconfig
7   -
8   -OPENRD_CLIENT BOARD
9   -#M: -
10   -S: Maintained
11   -F: configs/openrd_client_defconfig
12   -F: configs/openrd_ultimate_defconfig
board/Marvell/openrd/Makefile
View file @ 7a2c1b1
1   -#
2   -# (C) Copyright 2009
3   -# Net Insight <www.netinsight.net>
4   -# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
5   -#
6   -# Based on sheevaplug:
7   -# (C) Copyright 2009
8   -# Marvell Semiconductor <www.marvell.com>
9   -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10   -#
11   -# SPDX-License-Identifier: GPL-2.0+
12   -#
13   -
14   -obj-y := openrd.o
board/Marvell/openrd/kwbimage.cfg
View file @ 7a2c1b1
1   -#
2   -# (C) Copyright 2009
3   -# Marvell Semiconductor <www.marvell.com>
4   -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   -#
6   -# SPDX-License-Identifier: GPL-2.0+
7   -#
8   -# Refer doc/README.kwbimage for more details about how-to configure
9   -# and create kirkwood boot image
10   -#
11   -
12   -# Boot Media configurations
13   -BOOT_FROM nand
14   -NAND_ECC_MODE default
15   -NAND_PAGE_SIZE 0x0800
16   -
17   -# SOC registers configuration using bootrom header extension
18   -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
19   -
20   -# Configure RGMII-0 interface pad voltage to 1.8V
21   -DATA 0xFFD100e0 0x1b1b1b9b
22   -
23   -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
24   -DATA 0xFFD01400 0x43000c30 # DDR Configuration register
25   -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
26   -# bit23-14: zero
27   -# bit24: 1= enable exit self refresh mode on DDR access
28   -# bit25: 1 required
29   -# bit29-26: zero
30   -# bit31-30: 01
31   -
32   -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
33   -# bit 4: 0=addr/cmd in smame cycle
34   -# bit 5: 0=clk is driven during self refresh, we don't care for APX
35   -# bit 6: 0=use recommended falling edge of clk for addr/cmd
36   -# bit14: 0=input buffer always powered up
37   -# bit18: 1=cpu lock transaction enabled
38   -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39   -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
40   -# bit30-28: 3 required
41   -# bit31: 0=no additional STARTBURST delay
42   -
43   -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
44   -# bit3-0: TRAS lsbs
45   -# bit7-4: TRCD
46   -# bit11- 8: TRP
47   -# bit15-12: TWR
48   -# bit19-16: TWTR
49   -# bit20: TRAS msb
50   -# bit23-21: 0x0
51   -# bit27-24: TRRD
52   -# bit31-28: TRTP
53   -
54   -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
55   -# bit6-0: TRFC
56   -# bit8-7: TR2R
57   -# bit10-9: TR2W
58   -# bit12-11: TW2W
59   -# bit31-13: zero required
60   -
61   -DATA 0xFFD01410 0x000000cc # DDR Address Control
62   -# bit1-0: 00, Cs0width=x8
63   -# bit3-2: 11, Cs0size=1Gb
64   -# bit5-4: 00, Cs1width=x8
65   -# bit7-6: 11, Cs1size=1Gb
66   -# bit9-8: 00, Cs2width=nonexistent
67   -# bit11-10: 00, Cs2size =nonexistent
68   -# bit13-12: 00, Cs3width=nonexistent
69   -# bit15-14: 00, Cs3size =nonexistent
70   -# bit16: 0, Cs0AddrSel
71   -# bit17: 0, Cs1AddrSel
72   -# bit18: 0, Cs2AddrSel
73   -# bit19: 0, Cs3AddrSel
74   -# bit31-20: 0 required
75   -
76   -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
77   -# bit0: 0, OpenPage enabled
78   -# bit31-1: 0 required
79   -
80   -DATA 0xFFD01418 0x00000000 # DDR Operation
81   -# bit3-0: 0x0, DDR cmd
82   -# bit31-4: 0 required
83   -
84   -DATA 0xFFD0141C 0x00000C52 # DDR Mode
85   -# bit2-0: 2, BurstLen=2 required
86   -# bit3: 0, BurstType=0 required
87   -# bit6-4: 4, CL=5
88   -# bit7: 0, TestMode=0 normal
89   -# bit8: 0, DLL reset=0 normal
90   -# bit11-9: 6, auto-precharge write recovery ????????????
91   -# bit12: 0, PD must be zero
92   -# bit31-13: 0 required
93   -
94   -DATA 0xFFD01420 0x00000042 # DDR Extended Mode
95   -# bit0: 0, DDR DLL enabled
96   -# bit1: 1, DDR drive strength reduced
97   -# bit2: 0, DDR ODT control lsd (disabled)
98   -# bit5-3: 000, required
99   -# bit6: 1, DDR ODT control msb, (disabled)
100   -# bit9-7: 000, required
101   -# bit10: 0, differential DQS enabled
102   -# bit11: 0, required
103   -# bit12: 0, DDR output buffer enabled
104   -# bit31-13: 0 required
105   -
106   -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
107   -# bit2-0: 111, required
108   -# bit3 : 1 , MBUS Burst Chop disabled
109   -# bit6-4: 111, required
110   -# bit7 : 0
111   -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
112   -# bit9 : 0 , no half clock cycle addition to dataout
113   -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114   -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
115   -# bit15-12: 1111 required
116   -# bit31-16: 0 required
117   -
118   -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
119   -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
120   -
121   -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
122   -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
123   -# bit0: 1, Window enabled
124   -# bit1: 0, Write Protect disabled
125   -# bit3-2: 00, CS0 hit selected
126   -# bit23-4: ones, required
127   -# bit31-24: 0x0F, Size (i.e. 256MB)
128   -
129   -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
130   -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
131   -
132   -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
133   -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
134   -
135   -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
136   -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
137   -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
138   -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
139   -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
140   -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
141   -
142   -DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
143   -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
144   -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
145   -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
146   -# bit14: 1, M_STARTBURST_IN ODT: Enabled
147   -# bit15: 1, DDR IO ODT Unit: Use ODT block
148   -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
149   -#bit0=1, enable DDR init upon this register write
150   -
151   -# End of Header extension
152   -DATA 0x0 0x0
board/Marvell/openrd/openrd.c
View file @ 7a2c1b1
1   -/*
2   - * (C) Copyright 2009
3   - * Net Insight <www.netinsight.net>
4   - * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
5   - *
6   - * Based on sheevaplug.c:
7   - * (C) Copyright 2009
8   - * Marvell Semiconductor <www.marvell.com>
9   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <miiphy.h>
16   -#include <asm/arch/cpu.h>
17   -#include <asm/arch/soc.h>
18   -#include <asm/arch/mpp.h>
19   -#include "openrd.h"
20   -
21   -DECLARE_GLOBAL_DATA_PTR;
22   -
23   -int board_early_init_f(void)
24   -{
25   - /*
26   - * default gpio configuration
27   - * There are maximum 64 gpios controlled through 2 sets of registers
28   - * the below configuration configures mainly initial LED status
29   - */
30   - mvebu_config_gpio(OPENRD_OE_VAL_LOW,
31   - OPENRD_OE_VAL_HIGH,
32   - OPENRD_OE_LOW, OPENRD_OE_HIGH);
33   -
34   - /* Multi-Purpose Pins Functionality configuration */
35   - static const u32 kwmpp_config[] = {
36   - MPP0_NF_IO2,
37   - MPP1_NF_IO3,
38   - MPP2_NF_IO4,
39   - MPP3_NF_IO5,
40   - MPP4_NF_IO6,
41   - MPP5_NF_IO7,
42   - MPP6_SYSRST_OUTn,
43   - MPP7_GPO,
44   - MPP8_TW_SDA,
45   - MPP9_TW_SCK,
46   - MPP10_UART0_TXD,
47   - MPP11_UART0_RXD,
48   - MPP12_SD_CLK,
49   - MPP13_SD_CMD, /* Alt UART1_TXD */
50   - MPP14_SD_D0, /* Alt UART1_RXD */
51   - MPP15_SD_D1,
52   - MPP16_SD_D2,
53   - MPP17_SD_D3,
54   - MPP18_NF_IO0,
55   - MPP19_NF_IO1,
56   - MPP20_GE1_0,
57   - MPP21_GE1_1,
58   - MPP22_GE1_2,
59   - MPP23_GE1_3,
60   - MPP24_GE1_4,
61   - MPP25_GE1_5,
62   - MPP26_GE1_6,
63   - MPP27_GE1_7,
64   - MPP28_GPIO,
65   - MPP29_TSMP9,
66   - MPP30_GE1_10,
67   - MPP31_GE1_11,
68   - MPP32_GE1_12,
69   - MPP33_GE1_13,
70   - MPP34_GPIO, /* UART1 / SD sel */
71   - MPP35_TDM_CH0_TX_QL,
72   - MPP36_TDM_SPI_CS1,
73   - MPP37_TDM_CH2_TX_QL,
74   - MPP38_TDM_CH2_RX_QL,
75   - MPP39_AUDIO_I2SBCLK,
76   - MPP40_AUDIO_I2SDO,
77   - MPP41_AUDIO_I2SLRC,
78   - MPP42_AUDIO_I2SMCLK,
79   - MPP43_AUDIO_I2SDI,
80   - MPP44_AUDIO_EXTCLK,
81   - MPP45_TDM_PCLK,
82   - MPP46_TDM_FS,
83   - MPP47_TDM_DRX,
84   - MPP48_TDM_DTX,
85   - MPP49_TDM_CH0_RX_QL,
86   - 0
87   - };
88   -
89   - kirkwood_mpp_conf(kwmpp_config, NULL);
90   - return 0;
91   -}
92   -
93   -int board_init(void)
94   -{
95   - /*
96   - * arch number of board
97   - */
98   -#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
99   - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
100   -#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
101   - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
102   -#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
103   - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
104   -#endif
105   -
106   - /* adress of boot parameters */
107   - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
108   - return 0;
109   -}
110   -
111   -#ifdef CONFIG_RESET_PHY_R
112   -/* Configure and enable MV88E1116/88E1121 PHY */
113   -void mv_phy_init(char *name)
114   -{
115   - u16 reg;
116   - u16 devadr;
117   -
118   - if (miiphy_set_current_dev(name))
119   - return;
120   -
121   - /* command to read PHY dev address */
122   - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
123   - printf("Err..%s could not read PHY dev address\n",
124   - __FUNCTION__);
125   - return;
126   - }
127   -
128   - /*
129   - * Enable RGMII delay on Tx and Rx for CPU port
130   - * Ref: sec 4.7.2 of chip datasheet
131   - */
132   - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
133   - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
134   - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
135   - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
136   - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
137   -
138   - /* reset the phy */
139   - miiphy_reset(name, devadr);
140   -
141   - printf(PHY_NO" Initialized on %s\n", name);
142   -}
143   -
144   -void reset_phy(void)
145   -{
146   - mv_phy_init("egiga0");
147   -
148   -#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
149   - /* Kirkwood ethernet driver is written with the assumption that in case
150   - * of multiple PHYs, their addresses are consecutive. But unfortunately
151   - * in case of OpenRD-Client, PHY addresses are not consecutive.*/
152   - miiphy_write("egiga1", 0xEE, 0xEE, 24);
153   -#endif
154   -
155   -#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
156   - defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
157   - /* configure and initialize both PHY's */
158   - mv_phy_init("egiga1");
159   -#endif
160   -}
161   -#endif /* CONFIG_RESET_PHY_R */
board/Marvell/openrd/openrd.h
View file @ 7a2c1b1
1   -/*
2   - * (C) Copyright 2009
3   - * Net Insight <www.netinsight.net>
4   - * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
5   - *
6   - * Based on sheevaplug.h:
7   - * (C) Copyright 2009
8   - * Marvell Semiconductor <www.marvell.com>
9   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#ifndef __OPENRD_BASE_H
15   -#define __OPENRD_BASE_H
16   -
17   -#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
18   -#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
19   -#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
20   -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
21   -
22   -/* PHY related */
23   -#define MV88E1116_LED_FCTRL_REG 10
24   -#define MV88E1116_CPRSP_CR3_REG 21
25   -#define MV88E1116_MAC_CTRL_REG 21
26   -#define MV88E1116_PGADR_REG 22
27   -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
28   -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
29   -
30   -#endif /* __OPENRD_BASE_H */
configs/openrd_base_defconfig
View file @ 7a2c1b1
1   -CONFIG_ARM=y
2   -CONFIG_KIRKWOOD=y
3   -CONFIG_TARGET_OPENRD=y
4   -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
5   -# CONFIG_CMD_IMLS is not set
6   -# CONFIG_CMD_FLASH is not set
7   -# CONFIG_CMD_SETEXPR is not set
configs/openrd_client_defconfig
View file @ 7a2c1b1
1   -CONFIG_ARM=y
2   -CONFIG_KIRKWOOD=y
3   -CONFIG_TARGET_OPENRD=y
4   -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
5   -# CONFIG_CMD_IMLS is not set
6   -# CONFIG_CMD_FLASH is not set
7   -# CONFIG_CMD_SETEXPR is not set
configs/openrd_ultimate_defconfig
View file @ 7a2c1b1
1   -CONFIG_ARM=y
2   -CONFIG_KIRKWOOD=y
3   -CONFIG_TARGET_OPENRD=y
4   -CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
5   -# CONFIG_CMD_IMLS is not set
6   -# CONFIG_CMD_FLASH is not set
7   -# CONFIG_CMD_SETEXPR is not set
include/configs/openrd.h
View file @ 7a2c1b1
1   -/*
2   - * (C) Copyright 2009
3   - * Net Insight <www.netinsight.net>
4   - * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
5   - *
6   - * Based on sheevaplug.h:
7   - * (C) Copyright 2009
8   - * Marvell Semiconductor <www.marvell.com>
9   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#ifndef _CONFIG_OPENRD_H
15   -#define _CONFIG_OPENRD_H
16   -
17   -/*
18   - * Version number information
19   - */
20   -#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
21   -# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
22   -#else
23   -# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
24   -# define CONFIG_IDENT_STRING "\nOpenRD-Client"
25   -# else
26   -# ifdef CONFIG_BOARD_IS_OPENRD_BASE
27   -# define CONFIG_IDENT_STRING "\nOpenRD-Base"
28   -# else
29   -# error Unknown OpenRD board specified
30   -# endif
31   -# endif
32   -#endif
33   -
34   -/*
35   - * High Level Configuration Options (easy to change)
36   - */
37   -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
38   -#define CONFIG_KW88F6281 1 /* SOC Name */
39   -#define CONFIG_MACH_OPENRD_BASE /* Machine type */
40   -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
41   -
42   -/*
43   - * Commands configuration
44   - */
45   -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
46   -#define CONFIG_SYS_MVFS
47   -#define CONFIG_CMD_DHCP
48   -#define CONFIG_CMD_ENV
49   -#define CONFIG_CMD_MII
50   -#define CONFIG_CMD_MMC
51   -#define CONFIG_CMD_NAND
52   -#define CONFIG_CMD_PING
53   -#define CONFIG_CMD_USB
54   -#define CONFIG_CMD_IDE
55   -
56   -/*
57   - * mv-common.h should be defined after CMD configs since it used them
58   - * to enable certain macros
59   - */
60   -#include "mv-common.h"
61   -
62   -/*
63   - * Environment variables configurations
64   - */
65   -#ifdef CONFIG_CMD_NAND
66   -#define CONFIG_ENV_IS_IN_NAND 1
67   -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
68   -#else
69   -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
70   -#endif
71   -/*
72   - * max 4k env size is enough, but in case of nand
73   - * it has to be rounded to sector size
74   - */
75   -#define CONFIG_ENV_SIZE 0x20000 /* 128k */
76   -#define CONFIG_ENV_ADDR 0x60000
77   -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
78   -/*
79   - * Environment is right behind U-Boot in flash. Make sure U-Boot
80   - * doesn't grow into the environment area.
81   - */
82   -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
83   -
84   -/*
85   - * Default environment variables
86   - */
87   -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
88   - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
89   - "${x_bootcmd_usb}; bootm 0x6400000;"
90   -
91   -#define MTDIDS_DEFAULT "nand0=nand_mtd"
92   -#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
93   - "0x400000@0x100000(uImage),"\
94   - "0x1fb00000@0x500000(rootfs)"
95   -
96   -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
97   - "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
98   - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
99   - "x_bootcmd_usb=usb start\0" \
100   - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
101   - "mtdids="MTDIDS_DEFAULT"\0" \
102   - "mtdparts="MTDPARTS_DEFAULT"\0"
103   -
104   -/*
105   - * Ethernet Driver configuration
106   - */
107   -#ifdef CONFIG_CMD_NET
108   -# ifdef CONFIG_BOARD_IS_OPENRD_BASE
109   -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
110   -# else
111   -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
112   -# endif
113   -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
114   -# define CONFIG_PHY_BASE_ADR 0x0
115   -# define PHY_NO "88E1121"
116   -# else
117   -# define CONFIG_PHY_BASE_ADR 0x8
118   -# define PHY_NO "88E1116"
119   -# endif
120   -#endif /* CONFIG_CMD_NET */
121   -
122   -/*
123   - * SATA Driver configuration
124   - */
125   -#ifdef CONFIG_MVSATA_IDE
126   -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
127   -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
128   -#endif /*CONFIG_MVSATA_IDE*/
129   -
130   -#ifdef CONFIG_CMD_MMC
131   -#define CONFIG_MMC
132   -#define CONFIG_GENERIC_MMC
133   -#define CONFIG_MVEBU_MMC
134   -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
135   -#endif /* CONFIG_CMD_MMC */
136   -
137   -#endif /* _CONFIG_OPENRD_BASE_H */