Support for the MX31ADS evaluation board from Freescale

This patch adds support for the MX31ADS evaluation board from Freescale, initialization code is copied from RedBoot sources, also provided by Freescale. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

Support for the MX31ADS evaluation board from Freescale
This patch adds support for the MX31ADS evaluation board from Freescale, initialization code is copied from RedBoot sources, also provided by Freescale. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Guennadi Liakhovetski · Peter Pearse
1 parent c88ae20580
Showing 9 changed files with 683 additions and 0 deletions Side-by-side Diff
MAKEALL
Makefile
board/mx31ads/Makefile
board/mx31ads/config.mk
board/mx31ads/lowlevel_init.S
board/mx31ads/mx31ads.c
board/mx31ads/u-boot.lds
include/asm-arm/arch-mx31/mx31-regs.h
include/configs/mx31ads.h
@@ -505,6 +505,7 @@
 	apollon		\
 	imx31_litekit	\
 	imx31_phycore	\
+	mx31ads		\
 "
  
 #########################################################################
@@ -2604,6 +2604,9 @@
 imx31_phycore_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
  
+mx31ads_config		: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
+
 #========================================================================
 # i386
 #========================================================================
+#
+# (C) Copyright 2000-2008
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx31ads.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+TEXT_BASE = 0x87f00000
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x77777777
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =0x53F00000
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+
+	ldr r0, =0x53F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =0x43F04000
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =0x00302154
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =0xB8003000
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro  init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =0x43FAC200
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+	ldr r0, =WEIM_BASE
+	ldr r1, =0x0000D843
+	str r1, [r0, #0x40]
+	ldr r1, =0x22252521
+	str r1, [r0, #0x44]
+	ldr r1, =0x22220A00
+	str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Redboot initializes very early AIPS, what for?
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF */
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	init_cs4
+
+	/* Image Processing Unit: */
+	/* Too early to switch display on? */
+	/* Switch on Display Interface */
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	/* Clock Control Module: */
+	/* Use CKIH, MCU PLL off */
+	REG	CCM_CCMR, 0x074B0BF5
+
+	DELAY 0x40000
+	/* MCU PLL on */
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+	/* Switch to MCU PLL */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	/* PBC CPLD on CS4 */
+	mov	r1, #CS4_BASE
+	ldrh	r1, [r1, #0x2]
+	/* Is 27MHz switch set? */
+	ands	r1, r1, #0x16
+
+	/* 532-133-66.5 */
+	ldr	r0, =CCM_BASE
+	ldr	r1, =0xFF871D58
+	/* PDR0 */
+	str	r1, [r0, #0x4]
+	ldreq	r1, MPCTL_PARAM_532
+	ldrne	r1, MPCTL_PARAM_532_27
+	/* MPCTL */
+	str	r1, [r0, #0x10]
+
+	/* Set UPLL=240MHz, USB=60MHz */
+	ldr	r1, =0x49FCFE7F
+	/* PDR1 */
+	str	r1, [r0, #0x8]
+	ldreq	r1, UPCTL_PARAM_240
+	ldrne	r1, UPCTL_PARAM_240_27
+	/* UPCTL */
+	str	r1, [r0, #0x14]
+	/* default CLKO to 1/8 of the ARM core */
+	mov	r1, #0x000002C0
+	add	r1, r1, #0x00000006
+	/* COSR */
+	str	r1, [r0, #0x1c]
+
+	/* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
+/*	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |	\
+			PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) |	\
+			PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) |	\
+			PDR0_MCU_PODF(0)*/
+
+	/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+/*	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) |	\
+						PLL_MFN(0x23)*/
+	/* Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x006ac73a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+	mov	pc, lr
+
+MPCTL_PARAM_532:
+	.word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+	.word (((1-1) << 26) + ((15-1) << 16) + (9  << 10) + (13 << 0))
+UPCTL_PARAM_240:
+	.word (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
+UPCTL_PARAM_240_27:
+	.word (((2-1) << 26) + ((9 -1) << 16) + (8  << 10) + (8  << 0))
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int i;
+#if 0
+	/* CS0: Nor Flash */
+	/*
+	 * These are values from the RedBoot sources by Freescale. However,
+	 * under U-Boot with this configuration 32-bit accesses don't work,
+	 * lower 16 bits of data are read twice for each 32-bit read.
+	 */
+	__REG(CSCR_U(0)) = 0x23524E80;
+	__REG(CSCR_L(0)) = 0x10000D03; /* WRAP bit (1) is suspicious here, but
+					* disabling it doesn't help either */
+	__REG(CSCR_A(0)) = 0x00720900;
+#endif
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+	/* PBC setup */
+	/* Enable UART transceivers also reset the Ethernet/external UART */
+	readw(CS4_BASE + 4);
+
+	writew(0x8023, CS4_BASE + 4);
+
+	/* RedBoot also has an empty loop with 100000 iterations here -
+	 * clock doesn't run yet */
+	for (i = 0; i < 100000; i++)
+		;
+
+	/* Clear the reset, toggle the LEDs */
+	writew(0xDF, CS4_BASE + 6);
+
+	/* clock still doesn't run */
+	for (i = 0; i < 100000; i++)
+		;
+
+	/* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
+	readb(CS4_BASE + 8);
+	readb(CS4_BASE + 7);
+	readb(CS4_BASE + 8);
+	readb(CS4_BASE + 7);
+
+	gd->bd->bi_arch_number = 447;		/* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: MX31ADS\n");
+	return 0;
+}
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
@@ -133,5 +133,20 @@
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
 #define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
  
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE	0x70000000
+#define CSD0_BASE	0x80000000
+#define CSD1_BASE	0x90000000
+#define CS0_BASE	0xA0000000
+#define CS1_BASE	0xA8000000
+#define CS2_BASE	0xB0000000
+#define CS3_BASE	0xB2000000
+#define CS4_BASE	0xB4000000
+#define CS4_PSRAM_BASE	0xB5000000
+#define CS5_BASE	0xB6000000
+#define PCMCIA_MEM_BASE	0xC0000000
+
 #endif /* __ASM_ARCH_MX31_REGS_H */
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136		1	/* This is an arm1136 CPU core */
+#define CONFIG_MX31		1	/* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
+#define CONFIG_MX31_CLK32	32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Disabled for now due to build problems under Debian and
+ * a significant increase in the final file size: 144260 vs. 109536 Bytes
+ */
+#if 0
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+#endif
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128  /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MX31_UART	1
+#define CFG_MX31_UART1		1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.23.168
+#define CONFIG_SERVERIP		192.168.23.2
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
+		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"  					\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " 	\
+		"tftpboot 0x80000000 uImage-mx31; bootm\0"		\
+	"prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; " 		\
+		"protect off 0xa0000000 0xa001ffff; "			\
+		"erase 0xa0000000 0xa001ffff; "				\
+		"cp.b 0x80000000 0xa0000000 $(filesize)\0"
+
+#define CONFIG_DRIVER_CS8900	1
+#define CS8900_BASE		0xb4020300
+#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0		/* memtest works on */
+#define CFG_MEMTEST_END		0x10000
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		CSD0_BASE	/* default load address */
+
+#define CFG_HZ			32000
+
+#define CONFIG_CMDLINE_EDITING	1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below  */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE		CS0_BASE
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	262	/* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128KiB */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	(32 * 1024)
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
+/* S29WS256N NOR flash has 4 32KiB small sectors at beginning and end.
+ * The rest of 32MiB is in 128KiB big sectors.
+ * U-Boot occupies the low 4 sectors,
+ * if we put environment next to it, we will have to occupy 128KiB for it.
+ * Putting it at the top of flash we use only 32KiB. */
+#define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI			1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER		1 /* Use drivers/cfi_flash.c */
+#if 0 /* Doesn't work yet, work in progress */
+#define CFG_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes(~10x faster)*/
+#endif
+#define CFG_FLASH_PROTECTION		1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV	"nor0"
+
+#endif /* __CONFIG_H */
...	...	@@ -505,6 +505,7 @@
505	505	apollon \
506	506	imx31_litekit \
507	507	imx31_phycore \
	508	+ mx31ads \
508	509	"
509	510
510	511	#########################################################################
...	...	@@ -2604,6 +2604,9 @@
2604	2604	imx31_phycore_config : unconfig
2605	2605	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
2606	2606
	2607	+mx31ads_config : unconfig
	2608	+ @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
	2609	+
2607	2610	#========================================================================
2608	2611	# i386
2609	2612	#========================================================================
	1	+#
	2	+# (C) Copyright 2000-2008
	3	+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundatio; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+#
	24	+
	25	+include $(TOPDIR)/config.mk
	26	+
	27	+LIB = $(obj)lib$(BOARD).a
	28	+
	29	+COBJS := mx31ads.o
	30	+SOBJS := lowlevel_init.o
	31	+
	32	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	33	+OBJS := $(addprefix $(obj),$(COBJS))
	34	+SOBJS := $(addprefix $(obj),$(SOBJS))
	35	+
	36	+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
	37	+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
	38	+
	39	+clean:
	40	+ rm -f $(SOBJS) $(OBJS)
	41	+
	42	+distclean: clean
	43	+ rm -f $(LIB) core *.bak .depend
	44	+
	45	+#########################################################################
	46	+
	47	+# defines $(obj).depend target
	48	+include $(SRCTREE)/rules.mk
	49	+
	50	+sinclude $(obj).depend
	51	+
	52	+#########################################################################
	1	+/*
	2	+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or
	5	+ * modify it under the terms of the GNU General Public License as
	6	+ * published by the Free Software Foundation; either version 2 of
	7	+ * the License, or (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program; if not, write to the Free Software
	16	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	+ * MA 02111-1307 USA
	18	+ */
	19	+
	20	+#include <asm/arch/mx31-regs.h>
	21	+
	22	+.macro REG reg, val
	23	+ ldr r2, =\reg
	24	+ ldr r3, =\val
	25	+ str r3, [r2]
	26	+.endm
	27	+
	28	+.macro REG8 reg, val
	29	+ ldr r2, =\reg
	30	+ ldr r3, =\val
	31	+ strb r3, [r2]
	32	+.endm
	33	+
	34	+.macro DELAY loops
	35	+ ldr r2, =\loops
	36	+1:
	37	+ subs r2, r2, #1
	38	+ nop
	39	+ bcs 1b
	40	+.endm
	41	+
	42	+/* RedBoot: AIPS setup - Only setup MPROTx registers.
	43	+ * The PACR default values are good.*/
	44	+.macro init_aips
	45	+ /*
	46	+ * Set all MPROTx to be non-bufferable, trusted for R/W,
	47	+ * not forced to user-mode.
	48	+ */
	49	+ ldr r0, =0x43F00000
	50	+ ldr r1, =0x77777777
	51	+ str r1, [r0, #0x00]
	52	+ str r1, [r0, #0x04]
	53	+ ldr r0, =0x53F00000
	54	+ str r1, [r0, #0x00]
	55	+ str r1, [r0, #0x04]
	56	+
	57	+ /*
	58	+ * Clear the on and off peripheral modules Supervisor Protect bit
	59	+ * for SDMA to access them. Did not change the AIPS control registers
	60	+ * (offset 0x20) access type
	61	+ */
	62	+ ldr r0, =0x43F00000
	63	+ ldr r1, =0x0
	64	+ str r1, [r0, #0x40]
	65	+ str r1, [r0, #0x44]
	66	+ str r1, [r0, #0x48]
	67	+ str r1, [r0, #0x4C]
	68	+ ldr r1, [r0, #0x50]
	69	+ and r1, r1, #0x00FFFFFF
	70	+ str r1, [r0, #0x50]
	71	+
	72	+ ldr r0, =0x53F00000
	73	+ ldr r1, =0x0
	74	+ str r1, [r0, #0x40]
	75	+ str r1, [r0, #0x44]
	76	+ str r1, [r0, #0x48]
	77	+ str r1, [r0, #0x4C]
	78	+ ldr r1, [r0, #0x50]
	79	+ and r1, r1, #0x00FFFFFF
	80	+ str r1, [r0, #0x50]
	81	+.endm /* init_aips */
	82	+
	83	+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
	84	+.macro init_max
	85	+ ldr r0, =0x43F04000
	86	+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
	87	+ ldr r1, =0x00302154
	88	+ str r1, [r0, #0x000] /* for S0 */
	89	+ str r1, [r0, #0x100] /* for S1 */
	90	+ str r1, [r0, #0x200] /* for S2 */
	91	+ str r1, [r0, #0x300] /* for S3 */
	92	+ str r1, [r0, #0x400] /* for S4 */
	93	+ /* SGPCR - always park on last master */
	94	+ ldr r1, =0x10
	95	+ str r1, [r0, #0x010] /* for S0 */
	96	+ str r1, [r0, #0x110] /* for S1 */
	97	+ str r1, [r0, #0x210] /* for S2 */
	98	+ str r1, [r0, #0x310] /* for S3 */
	99	+ str r1, [r0, #0x410] /* for S4 */
	100	+ /* MGPCR - restore default values */
	101	+ ldr r1, =0x0
	102	+ str r1, [r0, #0x800] /* for M0 */
	103	+ str r1, [r0, #0x900] /* for M1 */
	104	+ str r1, [r0, #0xA00] /* for M2 */
	105	+ str r1, [r0, #0xB00] /* for M3 */
	106	+ str r1, [r0, #0xC00] /* for M4 */
	107	+ str r1, [r0, #0xD00] /* for M5 */
	108	+.endm /* init_max */
	109	+
	110	+/* RedBoot: M3IF setup */
	111	+.macro init_m3if
	112	+ /* Configure M3IF registers */
	113	+ ldr r1, =0xB8003000
	114	+ /*
	115	+ * M3IF Control Register (M3IFCTL)
	116	+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
	117	+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
	118	+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
	119	+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
	120	+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
	121	+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
	122	+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
	123	+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
	124	+ * ------------
	125	+ * 0x00000040
	126	+ */
	127	+ ldr r0, =0x00000040
	128	+ str r0, [r1] /* M3IF control reg */
	129	+.endm /* init_m3if */
	130	+
	131	+/* RedBoot: To support 133MHz DDR */
	132	+.macro init_drive_strength
	133	+ /*
	134	+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
	135	+ * in SW_PAD_CTL registers
	136	+ */
	137	+
	138	+ /* SDCLK */
	139	+ ldr r1, =0x43FAC200
	140	+ ldr r0, [r1, #0x6C]
	141	+ bic r0, r0, #(1 << 12)
	142	+ str r0, [r1, #0x6C]
	143	+
	144	+ /* CAS */
	145	+ ldr r0, [r1, #0x70]
	146	+ bic r0, r0, #(1 << 22)
	147	+ str r0, [r1, #0x70]
	148	+
	149	+ /* RAS */
	150	+ ldr r0, [r1, #0x74]
	151	+ bic r0, r0, #(1 << 2)
	152	+ str r0, [r1, #0x74]
	153	+
	154	+ /* CS2 (CSD0) */
	155	+ ldr r0, [r1, #0x7C]
	156	+ bic r0, r0, #(1 << 22)
	157	+ str r0, [r1, #0x7C]
	158	+
	159	+ /* DQM3 */
	160	+ ldr r0, [r1, #0x84]
	161	+ bic r0, r0, #(1 << 22)
	162	+ str r0, [r1, #0x84]
	163	+
	164	+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
	165	+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
	166	+pad_loop:
	167	+ ldr r0, [r1, #0x88]
	168	+ bic r0, r0, #(1 << 22)
	169	+ bic r0, r0, #(1 << 12)
	170	+ bic r0, r0, #(1 << 2)
	171	+ str r0, [r1, #0x88]
	172	+ add r1, r1, #4
	173	+ subs r2, r2, #0x1
	174	+ bne pad_loop
	175	+.endm /* init_drive_strength */
	176	+
	177	+/* CPLD on CS4 setup */
	178	+.macro init_cs4
	179	+ ldr r0, =WEIM_BASE
	180	+ ldr r1, =0x0000D843
	181	+ str r1, [r0, #0x40]
	182	+ ldr r1, =0x22252521
	183	+ str r1, [r0, #0x44]
	184	+ ldr r1, =0x22220A00
	185	+ str r1, [r0, #0x48]
	186	+.endm /* init_cs4 */
	187	+
	188	+.globl lowlevel_init
	189	+lowlevel_init:
	190	+
	191	+ /* Redboot initializes very early AIPS, what for?
	192	+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
	193	+ * M3IF */
	194	+ /* Also setup the Peripheral Port Remap register inside the core */
	195	+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
	196	+ mcr p15, 0, r0, c15, c2, 4
	197	+
	198	+ init_aips
	199	+
	200	+ init_max
	201	+
	202	+ init_m3if
	203	+
	204	+ init_drive_strength
	205	+
	206	+ init_cs4
	207	+
	208	+ /* Image Processing Unit: */
	209	+ /* Too early to switch display on? */
	210	+ /* Switch on Display Interface */
	211	+ REG IPU_CONF, IPU_CONF_DI_EN
	212	+ /* Clock Control Module: */
	213	+ /* Use CKIH, MCU PLL off */
	214	+ REG CCM_CCMR, 0x074B0BF5
	215	+
	216	+ DELAY 0x40000
	217	+ /* MCU PLL on */
	218	+ REG CCM_CCMR, 0x074B0BF5 \| CCMR_MPE
	219	+ /* Switch to MCU PLL */
	220	+ REG CCM_CCMR, (0x074B0BF5 \| CCMR_MPE) & ~CCMR_MDS
	221	+
	222	+ /* PBC CPLD on CS4 */
	223	+ mov r1, #CS4_BASE
	224	+ ldrh r1, [r1, #0x2]
	225	+ /* Is 27MHz switch set? */
	226	+ ands r1, r1, #0x16
	227	+
	228	+ /* 532-133-66.5 */
	229	+ ldr r0, =CCM_BASE
	230	+ ldr r1, =0xFF871D58
	231	+ /* PDR0 */
	232	+ str r1, [r0, #0x4]
	233	+ ldreq r1, MPCTL_PARAM_532
	234	+ ldrne r1, MPCTL_PARAM_532_27
	235	+ /* MPCTL */
	236	+ str r1, [r0, #0x10]
	237	+
	238	+ /* Set UPLL=240MHz, USB=60MHz */
	239	+ ldr r1, =0x49FCFE7F
	240	+ /* PDR1 */
	241	+ str r1, [r0, #0x8]
	242	+ ldreq r1, UPCTL_PARAM_240
	243	+ ldrne r1, UPCTL_PARAM_240_27
	244	+ /* UPCTL */
	245	+ str r1, [r0, #0x14]
	246	+ /* default CLKO to 1/8 of the ARM core */
	247	+ mov r1, #0x000002C0
	248	+ add r1, r1, #0x00000006
	249	+ /* COSR */
	250	+ str r1, [r0, #0x1c]
	251	+
	252	+ /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
	253	+/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) \| PDR0_PER_PODF(7) \| \
	254	+ PDR0_HSP_PODF(2) \| PDR0_NFC_PODF(6) \| \
	255	+ PDR0_IPG_PODF(1) \| PDR0_MAX_PODF(2) \| \
	256	+ PDR0_MCU_PODF(0)*/
	257	+
	258	+ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
	259	+/* REG CCM_MPCTL, PLL_PD(0) \| PLL_MFD(0x33) \| PLL_MFI(7) \| \
	260	+ PLL_MFN(0x23)*/
	261	+ /* Default: 1, 4, 12, 1 */
	262	+ REG CCM_SPCTL, PLL_PD(1) \| PLL_MFD(4) \| PLL_MFI(12) \| PLL_MFN(1)
	263	+
	264	+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
	265	+ REG 0xB8001010, 0x00000004
	266	+ REG 0xB8001004, 0x006ac73a
	267	+ REG 0xB8001000, 0x92100000
	268	+ REG 0x80000f00, 0x12344321
	269	+ REG 0xB8001000, 0xa2100000
	270	+ REG 0x80000000, 0x12344321
	271	+ REG 0x80000000, 0x12344321
	272	+ REG 0xB8001000, 0xb2100000
	273	+ REG8 0x80000033, 0xda
	274	+ REG8 0x81000000, 0xff
	275	+ REG 0xB8001000, 0x82226080
	276	+ REG 0x80000000, 0xDEADBEEF
	277	+ REG 0xB8001010, 0x0000000c
	278	+
	279	+ mov pc, lr
	280	+
	281	+MPCTL_PARAM_532:
	282	+ .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
	283	+MPCTL_PARAM_532_27:
	284	+ .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
	285	+UPCTL_PARAM_240:
	286	+ .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
	287	+UPCTL_PARAM_240_27:
	288	+ .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
	1	+/*
	2	+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	+ *
	4	+ * See file CREDITS for list of people who contributed to this
	5	+ * project.
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or
	8	+ * modify it under the terms of the GNU General Public License as
	9	+ * published by the Free Software Foundation; either version 2 of
	10	+ * the License, or (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+ * MA 02111-1307 USA
	21	+ */
	22	+
	23	+#include <common.h>
	24	+#include <asm/io.h>
	25	+#include <asm/arch/mx31.h>
	26	+#include <asm/arch/mx31-regs.h>
	27	+
	28	+DECLARE_GLOBAL_DATA_PTR;
	29	+
	30	+int dram_init(void)
	31	+{
	32	+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	33	+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	34	+
	35	+ return 0;
	36	+}
	37	+
	38	+int board_init(void)
	39	+{
	40	+ int i;
	41	+#if 0
	42	+ /* CS0: Nor Flash */
	43	+ /*
	44	+ * These are values from the RedBoot sources by Freescale. However,
	45	+ * under U-Boot with this configuration 32-bit accesses don't work,
	46	+ * lower 16 bits of data are read twice for each 32-bit read.
	47	+ */
	48	+ __REG(CSCR_U(0)) = 0x23524E80;
	49	+ __REG(CSCR_L(0)) = 0x10000D03; /* WRAP bit (1) is suspicious here, but
	50	+ * disabling it doesn't help either */
	51	+ __REG(CSCR_A(0)) = 0x00720900;
	52	+#endif
	53	+
	54	+ /* setup pins for UART1 */
	55	+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
	56	+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
	57	+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
	58	+ mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
	59	+
	60	+ /* PBC setup */
	61	+ /* Enable UART transceivers also reset the Ethernet/external UART */
	62	+ readw(CS4_BASE + 4);
	63	+
	64	+ writew(0x8023, CS4_BASE + 4);
	65	+
	66	+ /* RedBoot also has an empty loop with 100000 iterations here -
	67	+ * clock doesn't run yet */
	68	+ for (i = 0; i < 100000; i++)
	69	+ ;
	70	+
	71	+ /* Clear the reset, toggle the LEDs */
	72	+ writew(0xDF, CS4_BASE + 6);
	73	+
	74	+ /* clock still doesn't run */
	75	+ for (i = 0; i < 100000; i++)
	76	+ ;
	77	+
	78	+ /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
	79	+ readb(CS4_BASE + 8);
	80	+ readb(CS4_BASE + 7);
	81	+ readb(CS4_BASE + 8);
	82	+ readb(CS4_BASE + 7);
	83	+
	84	+ gd->bd->bi_arch_number = 447; /* board id for linux */
	85	+ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
	86	+
	87	+ return 0;
	88	+}
	89	+
	90	+int checkboard(void)
	91	+{
	92	+ printf("Board: MX31ADS\n");
	93	+ return 0;
	94	+}
	1	+/*
	2	+ * January 2004 - Changed to support H4 device
	3	+ * Copyright (c) 2004 Texas Instruments
	4	+ *
	5	+ * (C) Copyright 2002
	6	+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
	28	+OUTPUT_ARCH(arm)
	29	+ENTRY(_start)
	30	+SECTIONS
	31	+{
	32	+ . = 0x00000000;
	33	+
	34	+ . = ALIGN(4);
	35	+ .text :
	36	+ {
	37	+ cpu/arm1136/start.o (.text)
	38	+ *(.text)
	39	+ }
	40	+
	41	+ . = ALIGN(4);
	42	+ .rodata : { *(.rodata) }
	43	+
	44	+ . = ALIGN(4);
	45	+ .data : { *(.data) }
	46	+
	47	+ . = ALIGN(4);
	48	+ .got : { *(.got) }
	49	+
	50	+ . = .;
	51	+ __u_boot_cmd_start = .;
	52	+ .u_boot_cmd : { *(.u_boot_cmd) }
	53	+ __u_boot_cmd_end = .;
	54	+
	55	+ . = ALIGN(4);
	56	+ __bss_start = .;
	57	+ .bss : { *(.bss) }
	58	+ _end = .;
	59	+}
...	...	@@ -133,5 +133,20 @@
133	133	#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) \| MUX_CTL_CSPI2_MOSI)
134	134	#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) \| MUX_CTL_CSPI2_MISO)
135	135
	136	+/*
	137	+ * Memory regions and CS
	138	+ */
	139	+#define IPU_MEM_BASE 0x70000000
	140	+#define CSD0_BASE 0x80000000
	141	+#define CSD1_BASE 0x90000000
	142	+#define CS0_BASE 0xA0000000
	143	+#define CS1_BASE 0xA8000000
	144	+#define CS2_BASE 0xB0000000
	145	+#define CS3_BASE 0xB2000000
	146	+#define CS4_BASE 0xB4000000
	147	+#define CS4_PSRAM_BASE 0xB5000000
	148	+#define CS5_BASE 0xB6000000
	149	+#define PCMCIA_MEM_BASE 0xC0000000
	150	+
136	151	#endif /* __ASM_ARCH_MX31_REGS_H */
	1	+/*
	2	+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	+ *
	4	+ * Configuration settings for the MX31ADS Freescale board.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or
	7	+ * modify it under the terms of the GNU General Public License as
	8	+ * published by the Free Software Foundation; either version 2 of
	9	+ * the License, or (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	+ * MA 02111-1307 USA
	20	+ */
	21	+
	22	+#ifndef __CONFIG_H
	23	+#define __CONFIG_H
	24	+
	25	+#include <asm/arch/mx31-regs.h>
	26	+
	27	+ /* High Level Configuration Options */
	28	+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	29	+#define CONFIG_MX31 1 /* in a mx31 */
	30	+#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
	31	+#define CONFIG_MX31_CLK32 32000
	32	+
	33	+#define CONFIG_DISPLAY_CPUINFO
	34	+#define CONFIG_DISPLAY_BOARDINFO
	35	+
	36	+/*
	37	+ * Disabled for now due to build problems under Debian and
	38	+ * a significant increase in the final file size: 144260 vs. 109536 Bytes
	39	+ */
	40	+#if 0
	41	+#define CONFIG_OF_LIBFDT 1
	42	+#define CONFIG_FIT 1
	43	+#define CONFIG_FIT_VERBOSE 1
	44	+#endif
	45	+
	46	+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	47	+#define CONFIG_SETUP_MEMORY_TAGS 1
	48	+#define CONFIG_INITRD_TAG 1
	49	+
	50	+/*
	51	+ * Size of malloc() pool
	52	+ */
	53	+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
	54	+#define CFG_GBL_DATA_SIZE 128 /* num bytes reserved for initial data */
	55	+
	56	+/*
	57	+ * Hardware drivers
	58	+ */
	59	+
	60	+#define CONFIG_MX31_UART 1
	61	+#define CFG_MX31_UART1 1
	62	+
	63	+/* allow to overwrite serial and ethaddr */
	64	+#define CONFIG_ENV_OVERWRITE
	65	+#define CONFIG_CONS_INDEX 1
	66	+#define CONFIG_BAUDRATE 115200
	67	+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
	68	+
	69	+/***********************************************************
	70	+ * Command definition
	71	+ ***********************************************************/
	72	+
	73	+#include <config_cmd_default.h>
	74	+
	75	+#define CONFIG_CMD_MII
	76	+#define CONFIG_CMD_PING
	77	+
	78	+#define CONFIG_BOOTDELAY 3
	79	+
	80	+#define CONFIG_NETMASK 255.255.255.0
	81	+#define CONFIG_IPADDR 192.168.23.168
	82	+#define CONFIG_SERVERIP 192.168.23.2
	83	+
	84	+#define CONFIG_EXTRA_ENV_SETTINGS \
	85	+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
	86	+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
	87	+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	88	+ "bootcmd=run bootcmd_net\0" \
	89	+ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
	90	+ "tftpboot 0x80000000 uImage-mx31; bootm\0" \
	91	+ "prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; " \
	92	+ "protect off 0xa0000000 0xa001ffff; " \
	93	+ "erase 0xa0000000 0xa001ffff; " \
	94	+ "cp.b 0x80000000 0xa0000000 $(filesize)\0"
	95	+
	96	+#define CONFIG_DRIVER_CS8900 1
	97	+#define CS8900_BASE 0xb4020300
	98	+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
	99	+
	100	+/*
	101	+ * Miscellaneous configurable options
	102	+ */
	103	+#define CFG_LONGHELP /* undef to save memory */
	104	+#define CFG_PROMPT "=> "
	105	+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	106	+/* Print Buffer Size */
	107	+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
	108	+#define CFG_MAXARGS 16 /* max number of command args */
	109	+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	110	+
	111	+#define CFG_MEMTEST_START 0 /* memtest works on */
	112	+#define CFG_MEMTEST_END 0x10000
	113	+
	114	+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	115	+
	116	+#define CFG_LOAD_ADDR CSD0_BASE /* default load address */
	117	+
	118	+#define CFG_HZ 32000
	119	+
	120	+#define CONFIG_CMDLINE_EDITING 1
	121	+
	122	+/*-----------------------------------------------------------------------
	123	+ * Stack sizes
	124	+ *
	125	+ * The stack sizes are set up in start.S using the settings below */
	126	+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	127	+
	128	+/*-----------------------------------------------------------------------
	129	+ * Physical Memory Map
	130	+ */
	131	+#define CONFIG_NR_DRAM_BANKS 1
	132	+#define PHYS_SDRAM_1 CSD0_BASE
	133	+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
	134	+
	135	+/*-----------------------------------------------------------------------
	136	+ * FLASH and environment organization
	137	+ */
	138	+#define CFG_FLASH_BASE CS0_BASE
	139	+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	140	+#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
	141	+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
	142	+#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128KiB */
	143	+
	144	+#define CFG_ENV_IS_IN_FLASH 1
	145	+#define CFG_ENV_SECT_SIZE (32 * 1024)
	146	+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
	147	+/* S29WS256N NOR flash has 4 32KiB small sectors at beginning and end.
	148	+ * The rest of 32MiB is in 128KiB big sectors.
	149	+ * U-Boot occupies the low 4 sectors,
	150	+ * if we put environment next to it, we will have to occupy 128KiB for it.
	151	+ * Putting it at the top of flash we use only 32KiB. */
	152	+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE)
	153	+
	154	+/*-----------------------------------------------------------------------
	155	+ * CFI FLASH driver setup
	156	+ */
	157	+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
	158	+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
	159	+#if 0 /* Doesn't work yet, work in progress */
	160	+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes(~10x faster)*/
	161	+#endif
	162	+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
	163	+
	164	+/*
	165	+ * JFFS2 partitions
	166	+ */
	167	+#undef CONFIG_JFFS2_CMDLINE
	168	+#define CONFIG_JFFS2_DEV "nor0"
	169	+
	170	+#endif /* __CONFIG_H */